drv_timer.c 2.0 KB

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  1. /*
  2. * Copyright (c) 2006-2020, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-03-19 WangHuachen the first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <stdint.h>
  13. #include "drv_timer.h"
  14. #define TTC0_0_BASEADDR XPAR_PSU_TTC_0_BASEADDR
  15. #define TTC0_0_CLK_FREQ_HZ XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
  16. static void rt_hw_timer_isr(int vector, void *param)
  17. {
  18. rt_tick_increase();
  19. /* clear interrupt */
  20. TTC_ISR(TTC0_0_BASEADDR);
  21. }
  22. static int rt_hw_timer_init(void)
  23. {
  24. /* Stop timer */
  25. TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_DIS_MASK;
  26. /* Initialize TTC */
  27. TTC_CNT_CNTRL(TTC0_0_BASEADDR) = TTC_CNT_CNTRL_RESET_VALUE;
  28. TTC_CLK_CNTRL(TTC0_0_BASEADDR) = 0x00;
  29. TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = 0x00;
  30. TTC_MATCH_0(TTC0_0_BASEADDR) = 0x00;
  31. TTC_MATCH_1(TTC0_0_BASEADDR) = 0x00;
  32. TTC_MATCH_2(TTC0_0_BASEADDR) = 0x00;
  33. TTC_IER(TTC0_0_BASEADDR) = 0x00;
  34. TTC_ISR(TTC0_0_BASEADDR) = 0x00;
  35. /* Reset counter */
  36. TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_RST_MASK;
  37. /* Interval mode select */
  38. TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_INT_MASK;
  39. /* Setup interval */
  40. TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = TTC0_0_CLK_FREQ_HZ / RT_TICK_PER_SECOND;
  41. /* Clear all of the prescaler control bits in the register */
  42. TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK |
  43. TTC_CLK_CNTRL_PS_EN_MASK);
  44. /* We do not need a prescaler*/
  45. /* Register the ticker handler with the GIC */
  46. rt_hw_interrupt_install(XPAR_XTTCPS_0_INTR, rt_hw_timer_isr, RT_NULL, "tick");
  47. /* Enable TTC interrupts in the GIC */
  48. rt_hw_interrupt_umask(XPAR_XTTCPS_0_INTR);
  49. /* Enable interval interrupt */
  50. TTC_IER(TTC0_0_BASEADDR) |= TTC_IXR_INTERVAL_MASK;
  51. /* Start timer */
  52. TTC_CNT_CNTRL(TTC0_0_BASEADDR) &=~ TTC_CNT_CNTRL_DIS_MASK;
  53. return RT_EOK;
  54. }
  55. INIT_BOARD_EXPORT(rt_hw_timer_init);