drv_pwm.c 17 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-13 zylx first version
  9. * 2021-01-23 thread-liu Fix the timer clock frequency doubling problem
  10. */
  11. #include <board.h>
  12. #ifdef RT_USING_PWM
  13. #include "drv_config.h"
  14. #include <drivers/rt_drv_pwm.h>
  15. //#define DRV_DEBUG
  16. #define LOG_TAG "drv.pwm"
  17. #include <drv_log.h>
  18. #define MAX_PERIOD 65535
  19. #define MIN_PERIOD 3
  20. #define MIN_PULSE 2
  21. extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
  22. enum
  23. {
  24. #ifdef BSP_USING_PWM1
  25. PWM1_INDEX,
  26. #endif
  27. #ifdef BSP_USING_PWM2
  28. PWM2_INDEX,
  29. #endif
  30. #ifdef BSP_USING_PWM3
  31. PWM3_INDEX,
  32. #endif
  33. #ifdef BSP_USING_PWM4
  34. PWM4_INDEX,
  35. #endif
  36. #ifdef BSP_USING_PWM5
  37. PWM5_INDEX,
  38. #endif
  39. #ifdef BSP_USING_PWM6
  40. PWM6_INDEX,
  41. #endif
  42. #ifdef BSP_USING_PWM7
  43. PWM7_INDEX,
  44. #endif
  45. #ifdef BSP_USING_PWM8
  46. PWM8_INDEX,
  47. #endif
  48. #ifdef BSP_USING_PWM9
  49. PWM9_INDEX,
  50. #endif
  51. #ifdef BSP_USING_PWM10
  52. PWM10_INDEX,
  53. #endif
  54. #ifdef BSP_USING_PWM11
  55. PWM11_INDEX,
  56. #endif
  57. #ifdef BSP_USING_PWM12
  58. PWM12_INDEX,
  59. #endif
  60. #ifdef BSP_USING_PWM13
  61. PWM13_INDEX,
  62. #endif
  63. #ifdef BSP_USING_PWM14
  64. PWM14_INDEX,
  65. #endif
  66. #ifdef BSP_USING_PWM15
  67. PWM15_INDEX,
  68. #endif
  69. #ifdef BSP_USING_PWM16
  70. PWM16_INDEX,
  71. #endif
  72. #ifdef BSP_USING_PWM17
  73. PWM17_INDEX,
  74. #endif
  75. };
  76. struct stm32_pwm
  77. {
  78. struct rt_device_pwm pwm_device;
  79. TIM_HandleTypeDef tim_handle;
  80. rt_uint8_t channel;
  81. char *name;
  82. };
  83. static struct stm32_pwm stm32_pwm_obj[] =
  84. {
  85. #ifdef BSP_USING_PWM1
  86. PWM1_CONFIG,
  87. #endif
  88. #ifdef BSP_USING_PWM2
  89. PWM2_CONFIG,
  90. #endif
  91. #ifdef BSP_USING_PWM3
  92. PWM3_CONFIG,
  93. #endif
  94. #ifdef BSP_USING_PWM4
  95. PWM4_CONFIG,
  96. #endif
  97. #ifdef BSP_USING_PWM5
  98. PWM5_CONFIG,
  99. #endif
  100. #ifdef BSP_USING_PWM6
  101. PWM6_CONFIG,
  102. #endif
  103. #ifdef BSP_USING_PWM7
  104. PWM7_CONFIG,
  105. #endif
  106. #ifdef BSP_USING_PWM8
  107. PWM8_CONFIG,
  108. #endif
  109. #ifdef BSP_USING_PWM9
  110. PWM9_CONFIG,
  111. #endif
  112. #ifdef BSP_USING_PWM10
  113. PWM10_CONFIG,
  114. #endif
  115. #ifdef BSP_USING_PWM11
  116. PWM11_CONFIG,
  117. #endif
  118. #ifdef BSP_USING_PWM12
  119. PWM12_CONFIG,
  120. #endif
  121. #ifdef BSP_USING_PWM13
  122. PWM13_CONFIG,
  123. #endif
  124. #ifdef BSP_USING_PWM14
  125. PWM14_CONFIG,
  126. #endif
  127. #ifdef BSP_USING_PWM15
  128. PWM15_CONFIG,
  129. #endif
  130. #ifdef BSP_USING_PWM16
  131. PWM16_CONFIG,
  132. #endif
  133. #ifdef BSP_USING_PWM17
  134. PWM17_CONFIG,
  135. #endif
  136. };
  137. /* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
  138. static void pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
  139. {
  140. uint32_t flatency = 0;
  141. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  142. RT_ASSERT(pclk1_doubler != RT_NULL);
  143. RT_ASSERT(pclk1_doubler != RT_NULL);
  144. HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
  145. *pclk1_doubler = 1;
  146. *pclk2_doubler = 1;
  147. #if defined(SOC_SERIES_STM32MP1)
  148. if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
  149. {
  150. *pclk1_doubler = 2;
  151. }
  152. if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
  153. {
  154. *pclk2_doubler = 2;
  155. }
  156. #else
  157. if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
  158. {
  159. *pclk1_doubler = 2;
  160. }
  161. #if !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0))
  162. if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
  163. {
  164. *pclk2_doubler = 2;
  165. }
  166. #endif
  167. #endif
  168. }
  169. static rt_uint64_t tim_clock_get(TIM_HandleTypeDef *htim)
  170. {
  171. rt_uint32_t pclk1_doubler, pclk2_doubler;
  172. rt_uint64_t tim_clock;
  173. pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  174. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  175. if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
  176. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)|| defined(SOC_SERIES_STM32F3)
  177. if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
  178. #elif defined(SOC_SERIES_STM32MP1)
  179. if (htim->Instance == TIM4)
  180. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  181. if (0)
  182. #endif
  183. {
  184. #if !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)) /* don't have HAL_RCC_GetPCLK2Freq */
  185. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler);
  186. #endif
  187. }
  188. else
  189. {
  190. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  191. }
  192. return tim_clock;
  193. }
  194. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
  195. static struct rt_pwm_ops drv_ops =
  196. {
  197. drv_pwm_control
  198. };
  199. static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
  200. {
  201. /* Converts the channel number to the channel number of Hal library */
  202. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  203. if (!configuration->complementary)
  204. {
  205. if (!enable)
  206. {
  207. HAL_TIM_PWM_Stop(htim, channel);
  208. }
  209. else
  210. {
  211. HAL_TIM_PWM_Start(htim, channel);
  212. }
  213. }
  214. else if (configuration->complementary)
  215. {
  216. if (!enable)
  217. {
  218. HAL_TIMEx_PWMN_Stop(htim, channel);
  219. }
  220. else
  221. {
  222. HAL_TIMEx_PWMN_Start(htim, channel);
  223. }
  224. }
  225. return RT_EOK;
  226. }
  227. static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  228. {
  229. /* Converts the channel number to the channel number of Hal library */
  230. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  231. rt_uint64_t tim_clock;
  232. tim_clock = tim_clock_get(htim);
  233. if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
  234. {
  235. tim_clock = tim_clock / 2;
  236. }
  237. else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
  238. {
  239. tim_clock = tim_clock / 4;
  240. }
  241. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  242. tim_clock /= 1000000UL;
  243. configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  244. configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  245. return RT_EOK;
  246. }
  247. static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  248. {
  249. rt_uint32_t period, pulse;
  250. rt_uint64_t tim_clock, psc;
  251. /* Converts the channel number to the channel number of Hal library */
  252. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  253. tim_clock = tim_clock_get(htim);
  254. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  255. tim_clock /= 1000000UL;
  256. period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL ;
  257. psc = period / MAX_PERIOD + 1;
  258. period = period / psc;
  259. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  260. if (period < MIN_PERIOD)
  261. {
  262. period = MIN_PERIOD;
  263. }
  264. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  265. pulse = (rt_uint64_t)configuration->pulse * tim_clock / psc / 1000ULL;
  266. if (pulse < MIN_PULSE)
  267. {
  268. pulse = MIN_PULSE;
  269. }
  270. else if (pulse > period)
  271. {
  272. pulse = period;
  273. }
  274. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  275. /* If you want the PWM setting to take effect immediately,
  276. please uncommon the following code, but it will cause the last PWM cycle not complete. */
  277. //__HAL_TIM_SET_COUNTER(htim, 0);
  278. //HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE); /* Update frequency value */
  279. return RT_EOK;
  280. }
  281. static rt_err_t drv_pwm_set_period(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  282. {
  283. rt_uint32_t period;
  284. rt_uint64_t tim_clock, psc;
  285. tim_clock = tim_clock_get(htim);
  286. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  287. tim_clock /= 1000000UL;
  288. period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL ;
  289. psc = period / MAX_PERIOD + 1;
  290. period = period / psc;
  291. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  292. if (period < MIN_PERIOD)
  293. {
  294. period = MIN_PERIOD;
  295. }
  296. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  297. return RT_EOK;
  298. }
  299. static rt_err_t drv_pwm_set_pulse(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  300. {
  301. rt_uint32_t period, pulse;
  302. rt_uint64_t tim_clock;
  303. /* Converts the channel number to the channel number of Hal library */
  304. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  305. tim_clock = tim_clock_get(htim);
  306. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  307. tim_clock /= 1000000UL;
  308. period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  309. pulse = (rt_uint64_t)configuration->pulse * (__HAL_TIM_GET_AUTORELOAD(htim) + 1) / period;
  310. if (pulse < MIN_PULSE)
  311. {
  312. pulse = MIN_PULSE;
  313. }
  314. else if (pulse > period)
  315. {
  316. pulse = period;
  317. }
  318. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  319. return RT_EOK;
  320. }
  321. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
  322. {
  323. struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
  324. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
  325. switch (cmd)
  326. {
  327. case PWM_CMD_ENABLE:
  328. return drv_pwm_enable(htim, configuration, RT_TRUE);
  329. case PWM_CMD_DISABLE:
  330. return drv_pwm_enable(htim, configuration, RT_FALSE);
  331. case PWM_CMD_SET:
  332. return drv_pwm_set(htim, configuration);
  333. case PWM_CMD_SET_PERIOD:
  334. return drv_pwm_set_period(htim, configuration);
  335. case PWM_CMD_SET_PULSE:
  336. return drv_pwm_set_pulse(htim, configuration);
  337. case PWM_CMD_GET:
  338. return drv_pwm_get(htim, configuration);
  339. default:
  340. return RT_EINVAL;
  341. }
  342. }
  343. static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
  344. {
  345. rt_err_t result = RT_EOK;
  346. TIM_HandleTypeDef *tim = RT_NULL;
  347. TIM_OC_InitTypeDef oc_config = {0};
  348. TIM_MasterConfigTypeDef master_config = {0};
  349. TIM_ClockConfigTypeDef clock_config = {0};
  350. RT_ASSERT(device != RT_NULL);
  351. tim = (TIM_HandleTypeDef *)&device->tim_handle;
  352. /* configure the timer to pwm mode */
  353. tim->Init.Prescaler = 0;
  354. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  355. tim->Init.Period = 0;
  356. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  357. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
  358. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  359. #endif
  360. if (HAL_TIM_Base_Init(tim) != HAL_OK)
  361. {
  362. LOG_E("%s pwm init failed", device->name);
  363. result = -RT_ERROR;
  364. goto __exit;
  365. }
  366. if (HAL_TIM_PWM_Init(tim) != HAL_OK)
  367. {
  368. LOG_E("%s pwm init failed", device->name);
  369. result = -RT_ERROR;
  370. goto __exit;
  371. }
  372. clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  373. if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
  374. {
  375. LOG_E("%s clock init failed", device->name);
  376. result = -RT_ERROR;
  377. goto __exit;
  378. }
  379. master_config.MasterOutputTrigger = TIM_TRGO_RESET;
  380. master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  381. if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
  382. {
  383. LOG_E("%s master config failed", device->name);
  384. result = -RT_ERROR;
  385. goto __exit;
  386. }
  387. oc_config.OCMode = TIM_OCMODE_PWM1;
  388. oc_config.Pulse = 0;
  389. oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
  390. oc_config.OCFastMode = TIM_OCFAST_DISABLE;
  391. oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  392. oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
  393. /* config pwm channel */
  394. if (device->channel & 0x01)
  395. {
  396. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
  397. {
  398. LOG_E("%s channel1 config failed", device->name);
  399. result = -RT_ERROR;
  400. goto __exit;
  401. }
  402. }
  403. if (device->channel & 0x02)
  404. {
  405. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
  406. {
  407. LOG_E("%s channel2 config failed", device->name);
  408. result = -RT_ERROR;
  409. goto __exit;
  410. }
  411. }
  412. if (device->channel & 0x04)
  413. {
  414. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
  415. {
  416. LOG_E("%s channel3 config failed", device->name);
  417. result = -RT_ERROR;
  418. goto __exit;
  419. }
  420. }
  421. if (device->channel & 0x08)
  422. {
  423. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
  424. {
  425. LOG_E("%s channel4 config failed", device->name);
  426. result = -RT_ERROR;
  427. goto __exit;
  428. }
  429. }
  430. /* pwm pin configuration */
  431. HAL_TIM_MspPostInit(tim);
  432. /* enable update request source */
  433. __HAL_TIM_URS_ENABLE(tim);
  434. __exit:
  435. return result;
  436. }
  437. static void pwm_get_channel(void)
  438. {
  439. #ifdef BSP_USING_PWM1_CH1
  440. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
  441. #endif
  442. #ifdef BSP_USING_PWM1_CH2
  443. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
  444. #endif
  445. #ifdef BSP_USING_PWM1_CH3
  446. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
  447. #endif
  448. #ifdef BSP_USING_PWM1_CH4
  449. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
  450. #endif
  451. #ifdef BSP_USING_PWM2_CH1
  452. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
  453. #endif
  454. #ifdef BSP_USING_PWM2_CH2
  455. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
  456. #endif
  457. #ifdef BSP_USING_PWM2_CH3
  458. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
  459. #endif
  460. #ifdef BSP_USING_PWM2_CH4
  461. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
  462. #endif
  463. #ifdef BSP_USING_PWM3_CH1
  464. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
  465. #endif
  466. #ifdef BSP_USING_PWM3_CH2
  467. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
  468. #endif
  469. #ifdef BSP_USING_PWM3_CH3
  470. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
  471. #endif
  472. #ifdef BSP_USING_PWM3_CH4
  473. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
  474. #endif
  475. #ifdef BSP_USING_PWM4_CH1
  476. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
  477. #endif
  478. #ifdef BSP_USING_PWM4_CH2
  479. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
  480. #endif
  481. #ifdef BSP_USING_PWM4_CH3
  482. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
  483. #endif
  484. #ifdef BSP_USING_PWM4_CH4
  485. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
  486. #endif
  487. #ifdef BSP_USING_PWM5_CH1
  488. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
  489. #endif
  490. #ifdef BSP_USING_PWM5_CH2
  491. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
  492. #endif
  493. #ifdef BSP_USING_PWM5_CH3
  494. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
  495. #endif
  496. #ifdef BSP_USING_PWM5_CH4
  497. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
  498. #endif
  499. #ifdef BSP_USING_PWM6_CH1
  500. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
  501. #endif
  502. #ifdef BSP_USING_PWM6_CH2
  503. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
  504. #endif
  505. #ifdef BSP_USING_PWM6_CH3
  506. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
  507. #endif
  508. #ifdef BSP_USING_PWM6_CH4
  509. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
  510. #endif
  511. #ifdef BSP_USING_PWM7_CH1
  512. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
  513. #endif
  514. #ifdef BSP_USING_PWM7_CH2
  515. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
  516. #endif
  517. #ifdef BSP_USING_PWM7_CH3
  518. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
  519. #endif
  520. #ifdef BSP_USING_PWM7_CH4
  521. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
  522. #endif
  523. #ifdef BSP_USING_PWM8_CH1
  524. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
  525. #endif
  526. #ifdef BSP_USING_PWM8_CH2
  527. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
  528. #endif
  529. #ifdef BSP_USING_PWM8_CH3
  530. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
  531. #endif
  532. #ifdef BSP_USING_PWM8_CH4
  533. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
  534. #endif
  535. #ifdef BSP_USING_PWM9_CH1
  536. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
  537. #endif
  538. #ifdef BSP_USING_PWM9_CH2
  539. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
  540. #endif
  541. #ifdef BSP_USING_PWM9_CH3
  542. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
  543. #endif
  544. #ifdef BSP_USING_PWM9_CH4
  545. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
  546. #endif
  547. #ifdef BSP_USING_PWM10_CH1
  548. stm32_pwm_obj[PWM10_INDEX].channel |= 1 << 0;
  549. #endif
  550. #ifdef BSP_USING_PWM11_CH1
  551. stm32_pwm_obj[PWM11_INDEX].channel |= 1 << 0;
  552. #endif
  553. #ifdef BSP_USING_PWM12_CH1
  554. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
  555. #endif
  556. #ifdef BSP_USING_PWM12_CH2
  557. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
  558. #endif
  559. #ifdef BSP_USING_PWM13_CH1
  560. stm32_pwm_obj[PWM13_INDEX].channel |= 1 << 0;
  561. #endif
  562. #ifdef BSP_USING_PWM14_CH1
  563. stm32_pwm_obj[PWM14_INDEX].channel |= 1 << 0;
  564. #endif
  565. #ifdef BSP_USING_PWM15_CH1
  566. stm32_pwm_obj[PWM15_INDEX].channel |= 1 << 0;
  567. #endif
  568. #ifdef BSP_USING_PWM16_CH1
  569. stm32_pwm_obj[PWM16_INDEX].channel |= 1 << 0;
  570. #endif
  571. #ifdef BSP_USING_PWM17_CH1
  572. stm32_pwm_obj[PWM17_INDEX].channel |= 1 << 0;
  573. #endif
  574. }
  575. static int stm32_pwm_init(void)
  576. {
  577. int i = 0;
  578. int result = RT_EOK;
  579. pwm_get_channel();
  580. for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
  581. {
  582. /* pwm init */
  583. if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
  584. {
  585. LOG_E("%s init failed", stm32_pwm_obj[i].name);
  586. result = -RT_ERROR;
  587. goto __exit;
  588. }
  589. else
  590. {
  591. LOG_D("%s init success", stm32_pwm_obj[i].name);
  592. /* register pwm device */
  593. if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
  594. {
  595. LOG_D("%s register success", stm32_pwm_obj[i].name);
  596. }
  597. else
  598. {
  599. LOG_E("%s register failed", stm32_pwm_obj[i].name);
  600. result = -RT_ERROR;
  601. }
  602. }
  603. }
  604. __exit:
  605. return result;
  606. }
  607. INIT_DEVICE_EXPORT(stm32_pwm_init);
  608. #endif /* RT_USING_PWM */