drv_gpio.c 4.2 KB

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  1. /*
  2. * Copyright (c) 2020-2021, Bluetrum Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-11-19 greedyhao first version
  9. */
  10. #include "drv_gpio.h"
  11. #ifdef RT_USING_PIN
  12. // #define DRV_DEBUG
  13. #define LOG_TAG "drv.gpio"
  14. #include <drv_log.h>
  15. struct port_info
  16. {
  17. uint8_t start_pin;
  18. uint8_t delta_pin;
  19. uint8_t total_pin;
  20. };
  21. /* It needs to be adjusted to the hardware. */
  22. static const struct port_info port_table[] =
  23. {
  24. {0, 8, 0}, /* PA0-PA7 */
  25. {0, 5, 8}, /* PB0-PB5 */
  26. {0, 8, 13}, /* PE0-PE7 */
  27. {0, 6, 21}, /* PF0-PF6 */
  28. };
  29. static const hal_sfr_t port_sfr[] =
  30. {
  31. GPIOA_BASE,
  32. GPIOB_BASE,
  33. GPIOE_BASE,
  34. GPIOF_BASE,
  35. };
  36. static uint8_t _pin_port(uint32_t pin)
  37. {
  38. uint8_t port = 0;
  39. for (port = 0; port < 3; port++) {
  40. if (pin < (port_table[port].total_pin + port_table[port].delta_pin)) {
  41. break;
  42. }
  43. }
  44. return port;
  45. }
  46. #define PIN_NUM(port, no) ((uint8_t)(port_table[port].total_pin + no - port_table[port].start_pin))
  47. #define PIN_PORT(pin) _pin_port(pin)
  48. #define PORT_SFR(port) (port_sfr[(port)])
  49. #define PIN_NO(pin) (uint8_t)((pin) & 0xFu)
  50. // #define PIN_ABPIN(pin) (uint8_t)(port_table[PIN_PORT(pin)].total_pin + PIN_NO(pin))
  51. static rt_base_t ab32_pin_get(const char *name)
  52. {
  53. rt_base_t pin = 0;
  54. int hw_port_num, hw_pin_num = 0;
  55. int i, name_len;
  56. name_len = rt_strlen(name);
  57. if ((name_len < 4) || (name_len >= 6))
  58. {
  59. return -RT_EINVAL;
  60. }
  61. if ((name[0] != 'P') || (name[2] != '.'))
  62. {
  63. return -RT_EINVAL;
  64. }
  65. if ((name[1] >= 'A') && (name[1] <= 'B'))
  66. {
  67. hw_port_num = (int)(name[1] - 'A');
  68. }
  69. else if ((name[1] >= 'E') && (name[1] <= 'G'))
  70. {
  71. hw_port_num = (int)(name[1] - 'A') - 2; /* Without 'C' and 'D'. */
  72. }
  73. else
  74. {
  75. return -RT_EINVAL;
  76. }
  77. for (i = 3; i < name_len; i++)
  78. {
  79. hw_pin_num *= 10;
  80. hw_pin_num += name[i] - '0';
  81. }
  82. pin = PIN_NUM(hw_port_num, hw_pin_num);
  83. LOG_D("name=%s", name);
  84. LOG_D("hw_port_num=%d hw_pin_num=%d pin=%d", hw_port_num, hw_pin_num, pin);
  85. return pin;
  86. }
  87. static void ab32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  88. {
  89. uint8_t port = PIN_PORT(pin);
  90. uint8_t gpio_pin = pin - port_table[port].total_pin;
  91. hal_gpio_write(PORT_SFR(port), gpio_pin, (uint8_t)value);
  92. }
  93. static int ab32_pin_read(rt_device_t dev, rt_base_t pin)
  94. {
  95. uint8_t port = PIN_PORT(pin);
  96. uint8_t gpio_pin = pin - port_table[port].total_pin;
  97. return hal_gpio_read(PORT_SFR(port), gpio_pin);
  98. }
  99. static void ab32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  100. {
  101. struct gpio_init gpio_init;
  102. uint8_t port = PIN_PORT(pin);
  103. gpio_init.pin = BIT(pin - port_table[port].total_pin);
  104. gpio_init.de = GPIO_DIGITAL;
  105. gpio_init.af_con = GPIO_AFDIS;
  106. LOG_D("port=%d pin=%d", port, gpio_init.pin);
  107. switch (mode)
  108. {
  109. case PIN_MODE_INPUT:
  110. case PIN_MODE_INPUT_PULLUP:
  111. gpio_init.pull = GPIO_PULLUP;
  112. gpio_init.dir = GPIO_DIR_INPUT;
  113. break;
  114. case PIN_MODE_INPUT_PULLDOWN:
  115. gpio_init.pull = GPIO_PULLDOWN;
  116. gpio_init.dir = GPIO_DIR_INPUT;
  117. break;
  118. case PIN_MODE_OUTPUT:
  119. case PIN_MODE_OUTPUT_OD:
  120. default:
  121. gpio_init.pull = GPIO_NOPULL;
  122. gpio_init.dir = GPIO_DIR_OUTPUT;
  123. break;
  124. }
  125. hal_gpio_init(PORT_SFR(port), &gpio_init);
  126. }
  127. static rt_err_t ab32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  128. rt_uint32_t mode, void (*hdr)(void *args), void *args)
  129. {
  130. return -RT_ERROR;
  131. }
  132. static rt_err_t ab32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
  133. {
  134. return -RT_ERROR;
  135. }
  136. static rt_err_t ab32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
  137. rt_uint32_t enabled)
  138. {
  139. return -RT_ERROR;
  140. }
  141. const static struct rt_pin_ops _ab32_pin_ops =
  142. {
  143. ab32_pin_mode,
  144. ab32_pin_write,
  145. ab32_pin_read,
  146. ab32_pin_attach_irq,
  147. ab32_pin_dettach_irq,
  148. ab32_pin_irq_enable,
  149. ab32_pin_get,
  150. };
  151. int rt_hw_pin_init(void)
  152. {
  153. return rt_device_pin_register("pin", &_ab32_pin_ops, RT_NULL);
  154. }
  155. #endif