drv_gpio.c 4.3 KB

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  1. /*
  2. * Copyright (c) 2020-2021, Bluetrum Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-11-19 greedyhao first version
  9. */
  10. #include "drv_gpio.h"
  11. #ifdef RT_USING_PIN
  12. // #define DRV_DEBUG
  13. #define LOG_TAG "drv.gpio"
  14. #include <drv_log.h>
  15. struct port_info
  16. {
  17. rt_uint8_t start_pin;
  18. rt_uint8_t delta_pin;
  19. rt_uint8_t total_pin;
  20. };
  21. /* It needs to be adjusted to the hardware. */
  22. static const struct port_info port_table[] =
  23. {
  24. {0, 8, 0}, /* PA0-PA7 */
  25. {0, 5, 8}, /* PB0-PB4 */
  26. {0, 8, 13}, /* PE0-PE7 */
  27. {0, 6, 21}, /* PF0-PF5 */
  28. };
  29. static const hal_sfr_t port_sfr[] =
  30. {
  31. GPIOA_BASE,
  32. GPIOB_BASE,
  33. GPIOE_BASE,
  34. GPIOF_BASE,
  35. };
  36. static rt_uint8_t _pin_port(rt_uint32_t pin)
  37. {
  38. rt_uint8_t port = 0;
  39. for (port = 0; port < 3; port++) {
  40. if (pin < (port_table[port].total_pin + port_table[port].delta_pin)) {
  41. break;
  42. }
  43. }
  44. return port;
  45. }
  46. #define PIN_NUM(port, no) ((rt_uint8_t)(port_table[port].total_pin + no - port_table[port].start_pin))
  47. #define PIN_PORT(pin) _pin_port(pin)
  48. #define PORT_SFR(port) (port_sfr[(port)])
  49. #define PIN_NO(pin) (rt_uint8_t)((pin) & 0xFu)
  50. static rt_base_t ab32_pin_get(const char *name)
  51. {
  52. rt_base_t pin = 0;
  53. int hw_port_num, hw_pin_num = 0;
  54. int i, name_len;
  55. name_len = rt_strlen(name);
  56. if ((name_len < 4) || (name_len >= 6))
  57. {
  58. return -RT_EINVAL;
  59. }
  60. if ((name[0] != 'P') || (name[2] != '.'))
  61. {
  62. return -RT_EINVAL;
  63. }
  64. if ((name[1] >= 'A') && (name[1] <= 'B'))
  65. {
  66. hw_port_num = (int)(name[1] - 'A');
  67. }
  68. else if ((name[1] >= 'E') && (name[1] <= 'G'))
  69. {
  70. hw_port_num = (int)(name[1] - 'A') - 2; /* Without 'C' and 'D'. */
  71. }
  72. else
  73. {
  74. return -RT_EINVAL;
  75. }
  76. for (i = 3; i < name_len; i++)
  77. {
  78. hw_pin_num *= 10;
  79. hw_pin_num += name[i] - '0';
  80. }
  81. pin = PIN_NUM(hw_port_num, hw_pin_num);
  82. LOG_D("name=%s", name);
  83. LOG_D("hw_port_num=%d hw_pin_num=%d pin=%d", hw_port_num, hw_pin_num, pin);
  84. return pin;
  85. }
  86. static void ab32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  87. {
  88. rt_uint8_t port = PIN_PORT(pin);
  89. rt_uint8_t gpio_pin = pin - port_table[port].total_pin;
  90. hal_gpio_write(PORT_SFR(port), gpio_pin, (rt_uint8_t)value);
  91. }
  92. static int ab32_pin_read(rt_device_t dev, rt_base_t pin)
  93. {
  94. rt_uint8_t port = PIN_PORT(pin);
  95. rt_uint8_t gpio_pin = pin - port_table[port].total_pin;
  96. return hal_gpio_read(PORT_SFR(port), gpio_pin);
  97. }
  98. static void ab32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  99. {
  100. struct gpio_init gpio_init;
  101. rt_uint8_t port = PIN_PORT(pin);
  102. gpio_init.pin = BIT(pin - port_table[port].total_pin);
  103. gpio_init.de = GPIO_DIGITAL;
  104. gpio_init.af_con = GPIO_AFDIS;
  105. LOG_D("port=%d pin=%d", port, gpio_init.pin);
  106. switch (mode)
  107. {
  108. case PIN_MODE_INPUT:
  109. gpio_init.pull = GPIO_NOPULL;
  110. gpio_init.dir = GPIO_DIR_INPUT;
  111. break;
  112. case PIN_MODE_INPUT_PULLUP:
  113. gpio_init.pull = GPIO_PULLUP;
  114. gpio_init.dir = GPIO_DIR_INPUT;
  115. break;
  116. case PIN_MODE_INPUT_PULLDOWN:
  117. gpio_init.pull = GPIO_PULLDOWN;
  118. gpio_init.dir = GPIO_DIR_INPUT;
  119. break;
  120. case PIN_MODE_OUTPUT:
  121. case PIN_MODE_OUTPUT_OD:
  122. default:
  123. gpio_init.pull = GPIO_NOPULL;
  124. gpio_init.dir = GPIO_DIR_OUTPUT;
  125. break;
  126. }
  127. hal_gpio_init(PORT_SFR(port), &gpio_init);
  128. }
  129. static rt_err_t ab32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  130. rt_uint32_t mode, void (*hdr)(void *args), void *args)
  131. {
  132. return -RT_ERROR;
  133. }
  134. static rt_err_t ab32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
  135. {
  136. return -RT_ERROR;
  137. }
  138. static rt_err_t ab32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
  139. rt_uint32_t enabled)
  140. {
  141. return -RT_ERROR;
  142. }
  143. const static struct rt_pin_ops _ab32_pin_ops =
  144. {
  145. ab32_pin_mode,
  146. ab32_pin_write,
  147. ab32_pin_read,
  148. ab32_pin_attach_irq,
  149. ab32_pin_dettach_irq,
  150. ab32_pin_irq_enable,
  151. ab32_pin_get,
  152. };
  153. int rt_hw_pin_init(void)
  154. {
  155. return rt_device_pin_register("pin", &_ab32_pin_ops, RT_NULL);
  156. }
  157. #endif