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sdram_port.h

sdram_port.h 2.4 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2006-2021, RT-Thread Development Team
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  *
    6. 

  6.  * Change Logs:
    7. 

  7.  * Date           Author       Notes
    8. 

  8.  * 2018-12-04     zylx         The first version for STM32F4xx
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __SDRAM_PORT_H__
    12. 

  12. #define __SDRAM_PORT_H__
    13. 

  13. 

  14. /* parameters for sdram peripheral */
    15. 

  15. /* Bank1 or Bank2 */
    16. 

  16. #define SDRAM_TARGET_BANK               1
    17. 

  17. /* stm32h7 Bank1:0XC0000000  Bank2:0XD0000000 */
    18. 

  18. #define SDRAM_BANK_ADDR                 ((uint32_t)0XC0000000)
    19. 

  19. /* data width: 8, 16, 32 */
    20. 

  20. #define SDRAM_DATA_WIDTH                16
    21. 

  21. /* column bit numbers: 8, 9, 10, 11 */
    22. 

  22. #define SDRAM_COLUMN_BITS               9
    23. 

  23. /* row bit numbers: 11, 12, 13 */
    24. 

  24. #define SDRAM_ROW_BITS                  13
    25. 

  25. /* cas latency clock number: 1, 2, 3 */
    26. 

  26. #define SDRAM_CAS_LATENCY               2
    27. 

  27. /* read pipe delay: 0, 1, 2 */
    28. 

  28. #define SDRAM_RPIPE_DELAY               0
    29. 

  29. /* clock divid: 2, 3 */
    30. 

  30. #define SDCLOCK_PERIOD                  2
    31. 

  31. /* refresh rate counter */
    32. 

  32. #define SDRAM_REFRESH_COUNT             ((uint32_t)0x02A5)
    33. 

  33. #define SDRAM_SIZE                      ((uint32_t)0x2000000)
    34. 

  34. 

  35. /* Timing configuration for W9825G6KH-6 */
    36. 

  36. /* 100 MHz of HCKL3 clock frequency (200MHz/2) */
    37. 

  37. /* TMRD: 2 Clock cycles */
    38. 

  38. #define LOADTOACTIVEDELAY               2
    39. 

  39. /* TXSR: 8x10ns */
    40. 

  40. #define EXITSELFREFRESHDELAY            8
    41. 

  41. /* TRAS: 5x10ns */
    42. 

  42. #define SELFREFRESHTIME                 6
    43. 

  43. /* TRC:  7x10ns */
    44. 

  44. #define ROWCYCLEDELAY                   6
    45. 

  45. /* TWR:  2 Clock cycles */
    46. 

  46. #define WRITERECOVERYTIME               2
    47. 

  47. /* TRP:  2x10ns */
    48. 

  48. #define RPDELAY                         2
    49. 

  49. /* TRCD: 2x10ns */
    50. 

  50. #define RCDDELAY                        2
    51. 

  51. 

  52. /* memory mode register */
    53. 

  53. #define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
    54. 

  54. #define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
    55. 

  55. #define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
    56. 

  56. #define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
    57. 

  57. #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
    58. 

  58. #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
    59. 

  59. #define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
    60. 

  60. #define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
    61. 

  61. #define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
    62. 

  62. #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
    63. 

  63. #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
    64. 

  64. 

  65. #endif
    66.