drv_mfx.c 7.4 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-08-08 thread-liu first version
  9. */
  10. #include "board.h"
  11. #include "mfxstm32l152.h"
  12. #define DRV_DEBUG
  13. #define LOG_TAG "drv.mfx"
  14. #include <drv_log.h>
  15. #define CHIP_ADDRESS 0x42 /* mfx address */
  16. #define I2C_NAME "i2c2"
  17. struct st_mfx
  18. {
  19. struct rt_device dev;
  20. struct rt_i2c_bus_device *i2c_bus;
  21. rt_uint8_t id;
  22. rt_uint16_t type;
  23. };
  24. static struct st_mfx rt_mfx = {0};
  25. static IO_DrvTypeDef *IoDrv = NULL;
  26. static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint16_t len, rt_uint8_t *buf)
  27. {
  28. struct rt_i2c_msg msg[2] = {0, 0};
  29. RT_ASSERT(bus != RT_NULL);
  30. msg[0].addr = CHIP_ADDRESS;
  31. msg[0].flags = RT_I2C_WR;
  32. msg[0].buf = &reg;
  33. msg[0].len = 1;
  34. msg[1].addr = CHIP_ADDRESS;
  35. msg[1].flags = RT_I2C_RD;
  36. msg[1].len = len;
  37. msg[1].buf = buf;
  38. if (rt_i2c_transfer(bus, msg, 2) == 2)
  39. {
  40. return RT_EOK;
  41. }
  42. return RT_ERROR;
  43. }
  44. /* i2c write reg */
  45. static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t data)
  46. {
  47. rt_uint8_t buf[2];
  48. struct rt_i2c_msg msgs;
  49. RT_ASSERT(bus != RT_NULL);
  50. buf[0] = reg;
  51. buf[1] = data;
  52. msgs.addr = CHIP_ADDRESS;
  53. msgs.flags = RT_I2C_WR;
  54. msgs.buf = buf;
  55. msgs.len = sizeof(buf);
  56. if (rt_i2c_transfer(bus, &msgs, 1) == 1)
  57. {
  58. return RT_EOK;
  59. }
  60. return RT_ERROR;
  61. }
  62. void MFX_IO_Init(void)
  63. {
  64. rt_mfx.i2c_bus = rt_i2c_bus_device_find(I2C_NAME);
  65. if (rt_mfx.i2c_bus == RT_NULL)
  66. {
  67. LOG_E("can't find %c deivce", I2C_NAME);
  68. }
  69. }
  70. void MFX_IO_DeInit(void)
  71. {
  72. }
  73. void MFX_IO_ITConfig(void)
  74. {
  75. static rt_uint8_t mfx_io_it_enabled = 0;
  76. GPIO_InitTypeDef gpio_init_structure;
  77. if(mfx_io_it_enabled == 0)
  78. {
  79. mfx_io_it_enabled = 1;
  80. /* Enable the GPIO EXTI clock */
  81. __HAL_RCC_GPIOI_CLK_ENABLE();
  82. gpio_init_structure.Pin = GPIO_PIN_8;
  83. gpio_init_structure.Pull = GPIO_NOPULL;
  84. gpio_init_structure.Speed = GPIO_SPEED_FREQ_LOW;
  85. gpio_init_structure.Mode = GPIO_MODE_IT_RISING;
  86. HAL_GPIO_Init(GPIOI, &gpio_init_structure);
  87. /* Enable and set GPIO EXTI Interrupt to the lowest priority */
  88. HAL_NVIC_SetPriority((IRQn_Type)(EXTI8_IRQn), 0x04, 0x00);
  89. HAL_NVIC_EnableIRQ((IRQn_Type)(EXTI8_IRQn));
  90. }
  91. }
  92. void MFX_IO_Write(rt_uint16_t Addr, rt_uint8_t Reg, rt_uint8_t Value)
  93. {
  94. write_reg(rt_mfx.i2c_bus, Reg, Value);
  95. }
  96. rt_uint8_t MFX_IO_Read(rt_uint16_t Addr, rt_uint8_t Reg)
  97. {
  98. rt_uint8_t value = 0;
  99. read_reg(rt_mfx.i2c_bus, Reg, 1, &value);
  100. return value;
  101. }
  102. rt_uint16_t MFX_IO_ReadMultiple(rt_uint16_t Addr, rt_uint8_t Reg, rt_uint8_t *Buffer, rt_uint16_t Length)
  103. {
  104. return read_reg(rt_mfx.i2c_bus, Reg, Length, Buffer);
  105. }
  106. rt_weak void MFX_IO_Delay(rt_uint32_t Delay)
  107. {
  108. rt_thread_delay(Delay);
  109. }
  110. rt_weak void MFX_IO_Wakeup(void)
  111. {
  112. }
  113. rt_weak void MFX_IO_EnableWakeupPin(void)
  114. {
  115. }
  116. rt_uint8_t BSP_IO_DeInit(void)
  117. {
  118. IoDrv = NULL;
  119. return RT_EOK;
  120. }
  121. rt_uint32_t BSP_IO_ITGetStatus(rt_uint32_t IoPin)
  122. {
  123. /* Return the IO Pin IT status */
  124. return (IoDrv->ITStatus(0, IoPin));
  125. }
  126. /**
  127. * @brief Clears all the IO IT pending bits.
  128. * @retval None
  129. */
  130. void BSP_IO_ITClear(void)
  131. {
  132. /* Clear all IO IT pending bits */
  133. IoDrv->ClearIT(0, MFXSTM32L152_GPIO_PINS_ALL);
  134. }
  135. void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear)
  136. {
  137. /* Clear only the selected list of IO IT pending bits */
  138. IoDrv->ClearIT(0, IO_Pins_To_Clear);
  139. }
  140. /**
  141. * @brief Configures the IO pin(s) according to IO mode structure value.
  142. * @param IoPin: IO pin(s) to be configured.
  143. * This parameter can be one of the following values:
  144. * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
  145. * @param IoMode: IO pin mode to configure
  146. * This parameter can be one of the following values:
  147. * @arg IO_MODE_INPUT
  148. * @arg IO_MODE_OUTPUT
  149. * @arg IO_MODE_IT_RISING_EDGE
  150. * @arg IO_MODE_IT_FALLING_EDGE
  151. * @arg IO_MODE_IT_LOW_LEVEL
  152. * @arg IO_MODE_IT_HIGH_LEVEL
  153. * @arg IO_MODE_ANALOG
  154. * @arg IO_MODE_OFF
  155. * @arg IO_MODE_INPUT_PU,
  156. * @arg IO_MODE_INPUT_PD,
  157. * @arg IO_MODE_OUTPUT_OD,
  158. * @arg IO_MODE_OUTPUT_OD_PU,
  159. * @arg IO_MODE_OUTPUT_OD_PD,
  160. * @arg IO_MODE_OUTPUT_PP,
  161. * @arg IO_MODE_OUTPUT_PP_PU,
  162. * @arg IO_MODE_OUTPUT_PP_PD,
  163. * @arg IO_MODE_IT_RISING_EDGE_PU
  164. * @arg IO_MODE_IT_FALLING_EDGE_PU
  165. * @arg IO_MODE_IT_LOW_LEVEL_PU
  166. * @arg IO_MODE_IT_HIGH_LEVEL_PU
  167. * @arg IO_MODE_IT_RISING_EDGE_PD
  168. * @arg IO_MODE_IT_FALLING_EDGE_PD
  169. * @arg IO_MODE_IT_LOW_LEVEL_PD
  170. * @arg IO_MODE_IT_HIGH_LEVEL_PD
  171. * @retval RT_EOK if all initializations are OK. Other value if error.
  172. */
  173. rt_uint8_t rt_mfx_pin_mode(rt_uint32_t IoPin, IO_ModeTypedef IoMode)
  174. {
  175. /* Configure the selected IO pin(s) mode */
  176. IoDrv->Config(0, IoPin, IoMode);
  177. return RT_EOK;
  178. }
  179. /**
  180. * @brief Sets the IRQ_OUT pin polarity and type
  181. * @param IoIrqOutPinPolarity: High/Low
  182. * @param IoIrqOutPinType: OpenDrain/PushPull
  183. * @retval OK
  184. */
  185. rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOutPinType)
  186. {
  187. if((rt_mfx.id == MFXSTM32L152_ID_1) || (rt_mfx.id == MFXSTM32L152_ID_2))
  188. {
  189. /* Initialize the IO driver structure */
  190. mfxstm32l152_SetIrqOutPinPolarity(0, IoIrqOutPinPolarity);
  191. mfxstm32l152_SetIrqOutPinType(0, IoIrqOutPinType);
  192. }
  193. return RT_EOK;
  194. }
  195. /**
  196. * @brief Sets the selected pins state.
  197. * @param IoPin: Selected pins to write.
  198. * This parameter can be any combination of the IO pins.
  199. * @param PinState: New pins state to write
  200. * @retval None
  201. */
  202. void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState)
  203. {
  204. /* Set the Pin state */
  205. IoDrv->WritePin(0, IoPin, PinState);
  206. }
  207. /**
  208. * @brief Gets the selected pins current state.
  209. * @param IoPin: Selected pins to read.
  210. * This parameter can be any combination of the IO pins.
  211. * @retval The current pins state
  212. */
  213. rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin)
  214. {
  215. return(IoDrv->ReadPin(0, IoPin));
  216. }
  217. /**
  218. * @brief Toggles the selected pins state.
  219. * @param IoPin: Selected pins to toggle.
  220. * This parameter can be any combination of the IO pins.
  221. * @note This function is only used to toggle one pin in the same time
  222. * @retval None
  223. */
  224. void rt_mfx_pin_toggle(rt_uint32_t IoPin)
  225. {
  226. /* Toggle the current pin state */
  227. if(IoDrv->ReadPin(0, IoPin) != 0)
  228. {
  229. IoDrv->WritePin(0, IoPin, 0); /* Reset */
  230. }
  231. else
  232. {
  233. IoDrv->WritePin(0, IoPin, 1); /* Set */
  234. }
  235. }
  236. int rt_mfx_init(void)
  237. {
  238. /* Read ID and verify the MFX is ready */
  239. rt_mfx.id = mfxstm32l152_io_drv.ReadID(0);
  240. if((rt_mfx.id == MFXSTM32L152_ID_1) || (rt_mfx.id == MFXSTM32L152_ID_2))
  241. {
  242. /* Initialize the IO driver structure */
  243. IoDrv = &mfxstm32l152_io_drv;
  244. /* Initialize MFX */
  245. IoDrv->Init(0);
  246. IoDrv->Start(0, IO_PIN_ALL);
  247. LOG_I("mfx init success, id: 0x%x", rt_mfx.id);
  248. return RT_EOK;
  249. }
  250. LOG_I("mfx init error, id: 0x%x", rt_mfx.id);
  251. return RT_ERROR;
  252. }
  253. INIT_DEVICE_EXPORT(rt_mfx_init);