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efm32g_cmu.h

efm32g_cmu.h 118 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file
    3. 

  3.  * @brief efm32g_cmu Register and Bit Field definitions
    4. 

  4.  * @author Energy Micro AS
    5. 

  5.  * @version 3.0.0
    6. 

  6.  ******************************************************************************
    7. 

  7.  * @section License
    8. 

  8.  * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
    9. 

  9.  ******************************************************************************
    10. 

  10.  *
    11. 

  11.  * Permission is granted to anyone to use this software for any purpose,
    12. 

  12.  * including commercial applications, and to alter it and redistribute it
    13. 

  13.  * freely, subject to the following restrictions:
    14. 

  14.  *
    15. 

  15.  * 1. The origin of this software must not be misrepresented; you must not
    16. 

  16.  *    claim that you wrote the original software.
    17. 

  17.  * 2. Altered source versions must be plainly marked as such, and must not be
    18. 

  18.  *    misrepresented as being the original software.
    19. 

  19.  * 3. This notice may not be removed or altered from any source distribution.
    20. 

  20.  *
    21. 

  21.  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
    22. 

  22.  * obligation to support this Software. Energy Micro AS is providing the
    23. 

  23.  * Software "AS IS", with no express or implied warranties of any kind,
    24. 

  24.  * including, but not limited to, any implied warranties of merchantability
    25. 

  25.  * or fitness for any particular purpose or warranties against infringement
    26. 

  26.  * of any proprietary rights of a third party.
    27. 

  27.  *
    28. 

  28.  * Energy Micro AS will not be liable for any consequential, incidental, or
    29. 

  29.  * special damages, or any other relief, or for any claim by any third party,
    30. 

  30.  * arising from your use of this Software.
    31. 

  31.  *
    32. 

  32.  *****************************************************************************/
    33. 

  33. /**************************************************************************//**
    34. 

  34.  * @defgroup EFM32G_CMU
    35. 

  35.  * @{
    36. 

  36.  * @brief EFM32G_CMU Register Declaration
    37. 

  37.  *****************************************************************************/
    38. 

  38. typedef struct
    39. 

  39. {
    40. 

  40.   __IO uint32_t CTRL;         /**< CMU Control Register  */
    41. 

  41.   __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register  */
    42. 

  42.   __IO uint32_t HFPERCLKDIV;  /**< High Frequency Peripheral Clock Division Register  */
    43. 

  43.   __IO uint32_t HFRCOCTRL;    /**< HFRCO Control Register  */
    44. 

  44.   __IO uint32_t LFRCOCTRL;    /**< LFRCO Control Register  */
    45. 

  45.   __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register  */
    46. 

  46.   __IO uint32_t CALCTRL;      /**< Calibration Control Register  */
    47. 

  47.   __IO uint32_t CALCNT;       /**< Calibration Counter Register  */
    48. 

  48.   __IO uint32_t OSCENCMD;     /**< Oscillator Enable/Disable Command Register  */
    49. 

  49.   __IO uint32_t CMD;          /**< Command Register  */
    50. 

  50.   __IO uint32_t LFCLKSEL;     /**< Low Frequency Clock Select Register  */
    51. 

  51.   __I uint32_t  STATUS;       /**< Status Register  */
    52. 

  52.   __I uint32_t  IF;           /**< Interrupt Flag Register  */
    53. 

  53.   __IO uint32_t IFS;          /**< Interrupt Flag Set Register  */
    54. 

  54.   __IO uint32_t IFC;          /**< Interrupt Flag Clear Register  */
    55. 

  55.   __IO uint32_t IEN;          /**< Interrupt Enable Register  */
    56. 

  56.   __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0  */
    57. 

  57.   __IO uint32_t HFPERCLKEN0;  /**< High Frequency Peripheral Clock Enable Register 0  */
    58. 

  58.   uint32_t      RESERVED0[2]; /**< Reserved for future use **/
    59. 

  59.   __I uint32_t  SYNCBUSY;     /**< Synchronization Busy Register  */
    60. 

  60.   __IO uint32_t FREEZE;       /**< Freeze Register  */
    61. 

  61.   __IO uint32_t LFACLKEN0;    /**< Low Frequency A Clock Enable Register 0  (Async Reg)  */
    62. 

  62.   uint32_t      RESERVED1[1]; /**< Reserved for future use **/
    63. 

  63.   __IO uint32_t LFBCLKEN0;    /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
    64. 

  64.   uint32_t      RESERVED2[1]; /**< Reserved for future use **/
    65. 

  65.   __IO uint32_t LFAPRESC0;    /**< Low Frequency A Prescaler Register 0 (Async Reg)  */
    66. 

  66.   uint32_t      RESERVED3[1]; /**< Reserved for future use **/
    67. 

  67.   __IO uint32_t LFBPRESC0;    /**< Low Frequency B Prescaler Register 0  (Async Reg)  */
    68. 

  68.   uint32_t      RESERVED4[1]; /**< Reserved for future use **/
    69. 

  69.   __IO uint32_t PCNTCTRL;     /**< PCNT Control Register  */
    70. 

  70.   __IO uint32_t LCDCTRL;      /**< LCD Control Register  */
    71. 

  71.   __IO uint32_t ROUTE;        /**< I/O Routing Register  */
    72. 

  72.   __IO uint32_t LOCK;         /**< Configuration Lock Register  */
    73. 

  73. } CMU_TypeDef;                /** @} */
    74. 

  74. 

  75. /**************************************************************************//**
    76. 

  76.  * @defgroup EFM32G_CMU_BitFields
    77. 

  77.  * @{
    78. 

  78.  *****************************************************************************/
    79. 

  79. 

  80. /* Bit fields for CMU CTRL */
    81. 

  81. #define _CMU_CTRL_RESETVALUE                       0x000C262CUL                             /**< Default value for CMU_CTRL */
    82. 

  82. #define _CMU_CTRL_MASK                             0x00FE3EEFUL                             /**< Mask for CMU_CTRL */
    83. 

  83. #define _CMU_CTRL_HFXOMODE_SHIFT                   0                                        /**< Shift value for CMU_HFXOMODE */
    84. 

  84. #define _CMU_CTRL_HFXOMODE_MASK                    0x3UL                                    /**< Bit mask for CMU_HFXOMODE */
    85. 

  85. #define _CMU_CTRL_HFXOMODE_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
    86. 

  86. #define _CMU_CTRL_HFXOMODE_XTAL                    0x00000000UL                             /**< Mode XTAL for CMU_CTRL */
    87. 

  87. #define _CMU_CTRL_HFXOMODE_BUFEXTCLK               0x00000001UL                             /**< Mode BUFEXTCLK for CMU_CTRL */
    88. 

  88. #define _CMU_CTRL_HFXOMODE_DIGEXTCLK               0x00000002UL                             /**< Mode DIGEXTCLK for CMU_CTRL */
    89. 

  89. #define CMU_CTRL_HFXOMODE_DEFAULT                  (_CMU_CTRL_HFXOMODE_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_CTRL */
    90. 

  90. #define CMU_CTRL_HFXOMODE_XTAL                     (_CMU_CTRL_HFXOMODE_XTAL << 0)           /**< Shifted mode XTAL for CMU_CTRL */
    91. 

  91. #define CMU_CTRL_HFXOMODE_BUFEXTCLK                (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)      /**< Shifted mode BUFEXTCLK for CMU_CTRL */
    92. 

  92. #define CMU_CTRL_HFXOMODE_DIGEXTCLK                (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)      /**< Shifted mode DIGEXTCLK for CMU_CTRL */
    93. 

  93. #define _CMU_CTRL_HFXOBOOST_SHIFT                  2                                        /**< Shift value for CMU_HFXOBOOST */
    94. 

  94. #define _CMU_CTRL_HFXOBOOST_MASK                   0xCUL                                    /**< Bit mask for CMU_HFXOBOOST */
    95. 

  95. #define _CMU_CTRL_HFXOBOOST_50PCENT                0x00000000UL                             /**< Mode 50PCENT for CMU_CTRL */
    96. 

  96. #define _CMU_CTRL_HFXOBOOST_70PCENT                0x00000001UL                             /**< Mode 70PCENT for CMU_CTRL */
    97. 

  97. #define _CMU_CTRL_HFXOBOOST_80PCENT                0x00000002UL                             /**< Mode 80PCENT for CMU_CTRL */
    98. 

  98. #define _CMU_CTRL_HFXOBOOST_DEFAULT                0x00000003UL                             /**< Mode DEFAULT for CMU_CTRL */
    99. 

  99. #define _CMU_CTRL_HFXOBOOST_100PCENT               0x00000003UL                             /**< Mode 100PCENT for CMU_CTRL */
    100. 

  100. #define CMU_CTRL_HFXOBOOST_50PCENT                 (_CMU_CTRL_HFXOBOOST_50PCENT << 2)       /**< Shifted mode 50PCENT for CMU_CTRL */
    101. 

  101. #define CMU_CTRL_HFXOBOOST_70PCENT                 (_CMU_CTRL_HFXOBOOST_70PCENT << 2)       /**< Shifted mode 70PCENT for CMU_CTRL */
    102. 

  102. #define CMU_CTRL_HFXOBOOST_80PCENT                 (_CMU_CTRL_HFXOBOOST_80PCENT << 2)       /**< Shifted mode 80PCENT for CMU_CTRL */
    103. 

  103. #define CMU_CTRL_HFXOBOOST_DEFAULT                 (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)       /**< Shifted mode DEFAULT for CMU_CTRL */
    104. 

  104. #define CMU_CTRL_HFXOBOOST_100PCENT                (_CMU_CTRL_HFXOBOOST_100PCENT << 2)      /**< Shifted mode 100PCENT for CMU_CTRL */
    105. 

  105. #define _CMU_CTRL_HFXOBUFCUR_SHIFT                 5                                        /**< Shift value for CMU_HFXOBUFCUR */
    106. 

  106. #define _CMU_CTRL_HFXOBUFCUR_MASK                  0x60UL                                   /**< Bit mask for CMU_HFXOBUFCUR */
    107. 

  107. #define _CMU_CTRL_HFXOBUFCUR_DEFAULT               0x00000001UL                             /**< Mode DEFAULT for CMU_CTRL */
    108. 

  108. #define CMU_CTRL_HFXOBUFCUR_DEFAULT                (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)      /**< Shifted mode DEFAULT for CMU_CTRL */
    109. 

  109. #define CMU_CTRL_HFXOGLITCHDETEN                   (0x1UL << 7)                             /**< HFXO Glitch Detector Enable */
    110. 

  110. #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT            7                                        /**< Shift value for CMU_HFXOGLITCHDETEN */
    111. 

  111. #define _CMU_CTRL_HFXOGLITCHDETEN_MASK             0x80UL                                   /**< Bit mask for CMU_HFXOGLITCHDETEN */
    112. 

  112. #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
    113. 

  113. #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
    114. 

  114. #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                9                                        /**< Shift value for CMU_HFXOTIMEOUT */
    115. 

  115. #define _CMU_CTRL_HFXOTIMEOUT_MASK                 0x600UL                                  /**< Bit mask for CMU_HFXOTIMEOUT */
    116. 

  116. #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES              0x00000000UL                             /**< Mode 8CYCLES for CMU_CTRL */
    117. 

  117. #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES            0x00000001UL                             /**< Mode 256CYCLES for CMU_CTRL */
    118. 

  118. #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES             0x00000002UL                             /**< Mode 1KCYCLES for CMU_CTRL */
    119. 

  119. #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT              0x00000003UL                             /**< Mode DEFAULT for CMU_CTRL */
    120. 

  120. #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES            0x00000003UL                             /**< Mode 16KCYCLES for CMU_CTRL */
    121. 

  121. #define CMU_CTRL_HFXOTIMEOUT_8CYCLES               (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)     /**< Shifted mode 8CYCLES for CMU_CTRL */
    122. 

  122. #define CMU_CTRL_HFXOTIMEOUT_256CYCLES             (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)   /**< Shifted mode 256CYCLES for CMU_CTRL */
    123. 

  123. #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)    /**< Shifted mode 1KCYCLES for CMU_CTRL */
    124. 

  124. #define CMU_CTRL_HFXOTIMEOUT_DEFAULT               (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)     /**< Shifted mode DEFAULT for CMU_CTRL */
    125. 

  125. #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES             (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)   /**< Shifted mode 16KCYCLES for CMU_CTRL */
    126. 

  126. #define _CMU_CTRL_LFXOMODE_SHIFT                   11                                       /**< Shift value for CMU_LFXOMODE */
    127. 

  127. #define _CMU_CTRL_LFXOMODE_MASK                    0x1800UL                                 /**< Bit mask for CMU_LFXOMODE */
    128. 

  128. #define _CMU_CTRL_LFXOMODE_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
    129. 

  129. #define _CMU_CTRL_LFXOMODE_XTAL                    0x00000000UL                             /**< Mode XTAL for CMU_CTRL */
    130. 

  130. #define _CMU_CTRL_LFXOMODE_BUFEXTCLK               0x00000001UL                             /**< Mode BUFEXTCLK for CMU_CTRL */
    131. 

  131. #define _CMU_CTRL_LFXOMODE_DIGEXTCLK               0x00000002UL                             /**< Mode DIGEXTCLK for CMU_CTRL */
    132. 

  132. #define CMU_CTRL_LFXOMODE_DEFAULT                  (_CMU_CTRL_LFXOMODE_DEFAULT << 11)       /**< Shifted mode DEFAULT for CMU_CTRL */
    133. 

  133. #define CMU_CTRL_LFXOMODE_XTAL                     (_CMU_CTRL_LFXOMODE_XTAL << 11)          /**< Shifted mode XTAL for CMU_CTRL */
    134. 

  134. #define CMU_CTRL_LFXOMODE_BUFEXTCLK                (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)     /**< Shifted mode BUFEXTCLK for CMU_CTRL */
    135. 

  135. #define CMU_CTRL_LFXOMODE_DIGEXTCLK                (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)     /**< Shifted mode DIGEXTCLK for CMU_CTRL */
    136. 

  136. #define CMU_CTRL_LFXOBOOST                         (0x1UL << 13)                            /**< LFXO Start-up Boost Current */
    137. 

  137. #define _CMU_CTRL_LFXOBOOST_SHIFT                  13                                       /**< Shift value for CMU_LFXOBOOST */
    138. 

  138. #define _CMU_CTRL_LFXOBOOST_MASK                   0x2000UL                                 /**< Bit mask for CMU_LFXOBOOST */
    139. 

  139. #define _CMU_CTRL_LFXOBOOST_70PCENT                0x00000000UL                             /**< Mode 70PCENT for CMU_CTRL */
    140. 

  140. #define _CMU_CTRL_LFXOBOOST_DEFAULT                0x00000001UL                             /**< Mode DEFAULT for CMU_CTRL */
    141. 

  141. #define _CMU_CTRL_LFXOBOOST_100PCENT               0x00000001UL                             /**< Mode 100PCENT for CMU_CTRL */
    142. 

  142. #define CMU_CTRL_LFXOBOOST_70PCENT                 (_CMU_CTRL_LFXOBOOST_70PCENT << 13)      /**< Shifted mode 70PCENT for CMU_CTRL */
    143. 

  143. #define CMU_CTRL_LFXOBOOST_DEFAULT                 (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)      /**< Shifted mode DEFAULT for CMU_CTRL */
    144. 

  144. #define CMU_CTRL_LFXOBOOST_100PCENT                (_CMU_CTRL_LFXOBOOST_100PCENT << 13)     /**< Shifted mode 100PCENT for CMU_CTRL */
    145. 

  145. #define CMU_CTRL_LFXOBUFCUR                        (0x1UL << 17)                            /**< LFXO Boost Buffer Current */
    146. 

  146. #define _CMU_CTRL_LFXOBUFCUR_SHIFT                 17                                       /**< Shift value for CMU_LFXOBUFCUR */
    147. 

  147. #define _CMU_CTRL_LFXOBUFCUR_MASK                  0x20000UL                                /**< Bit mask for CMU_LFXOBUFCUR */
    148. 

  148. #define _CMU_CTRL_LFXOBUFCUR_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
    149. 

  149. #define CMU_CTRL_LFXOBUFCUR_DEFAULT                (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)     /**< Shifted mode DEFAULT for CMU_CTRL */
    150. 

  150. #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                18                                       /**< Shift value for CMU_LFXOTIMEOUT */
    151. 

  151. #define _CMU_CTRL_LFXOTIMEOUT_MASK                 0xC0000UL                                /**< Bit mask for CMU_LFXOTIMEOUT */
    152. 

  152. #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES              0x00000000UL                             /**< Mode 8CYCLES for CMU_CTRL */
    153. 

  153. #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES             0x00000001UL                             /**< Mode 1KCYCLES for CMU_CTRL */
    154. 

  154. #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES            0x00000002UL                             /**< Mode 16KCYCLES for CMU_CTRL */
    155. 

  155. #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT              0x00000003UL                             /**< Mode DEFAULT for CMU_CTRL */
    156. 

  156. #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES            0x00000003UL                             /**< Mode 32KCYCLES for CMU_CTRL */
    157. 

  157. #define CMU_CTRL_LFXOTIMEOUT_8CYCLES               (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)    /**< Shifted mode 8CYCLES for CMU_CTRL */
    158. 

  158. #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)   /**< Shifted mode 1KCYCLES for CMU_CTRL */
    159. 

  159. #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES             (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)  /**< Shifted mode 16KCYCLES for CMU_CTRL */
    160. 

  160. #define CMU_CTRL_LFXOTIMEOUT_DEFAULT               (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)    /**< Shifted mode DEFAULT for CMU_CTRL */
    161. 

  161. #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES             (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)  /**< Shifted mode 32KCYCLES for CMU_CTRL */
    162. 

  162. #define _CMU_CTRL_CLKOUTSEL0_SHIFT                 20                                       /**< Shift value for CMU_CLKOUTSEL0 */
    163. 

  163. #define _CMU_CTRL_CLKOUTSEL0_MASK                  0x700000UL                               /**< Bit mask for CMU_CLKOUTSEL0 */
    164. 

  164. #define _CMU_CTRL_CLKOUTSEL0_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
    165. 

  165. #define _CMU_CTRL_CLKOUTSEL0_HFRCO                 0x00000000UL                             /**< Mode HFRCO for CMU_CTRL */
    166. 

  166. #define _CMU_CTRL_CLKOUTSEL0_HFXO                  0x00000001UL                             /**< Mode HFXO for CMU_CTRL */
    167. 

  167. #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                0x00000002UL                             /**< Mode HFCLK2 for CMU_CTRL */
    168. 

  168. #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                0x00000003UL                             /**< Mode HFCLK4 for CMU_CTRL */
    169. 

  169. #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                0x00000004UL                             /**< Mode HFCLK8 for CMU_CTRL */
    170. 

  170. #define _CMU_CTRL_CLKOUTSEL0_HFCLK16               0x00000005UL                             /**< Mode HFCLK16 for CMU_CTRL */
    171. 

  171. #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                0x00000006UL                             /**< Mode ULFRCO for CMU_CTRL */
    172. 

  172. #define CMU_CTRL_CLKOUTSEL0_DEFAULT                (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)     /**< Shifted mode DEFAULT for CMU_CTRL */
    173. 

  173. #define CMU_CTRL_CLKOUTSEL0_HFRCO                  (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)       /**< Shifted mode HFRCO for CMU_CTRL */
    174. 

  174. #define CMU_CTRL_CLKOUTSEL0_HFXO                   (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)        /**< Shifted mode HFXO for CMU_CTRL */
    175. 

  175. #define CMU_CTRL_CLKOUTSEL0_HFCLK2                 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)      /**< Shifted mode HFCLK2 for CMU_CTRL */
    176. 

  176. #define CMU_CTRL_CLKOUTSEL0_HFCLK4                 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)      /**< Shifted mode HFCLK4 for CMU_CTRL */
    177. 

  177. #define CMU_CTRL_CLKOUTSEL0_HFCLK8                 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)      /**< Shifted mode HFCLK8 for CMU_CTRL */
    178. 

  178. #define CMU_CTRL_CLKOUTSEL0_HFCLK16                (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)     /**< Shifted mode HFCLK16 for CMU_CTRL */
    179. 

  179. #define CMU_CTRL_CLKOUTSEL0_ULFRCO                 (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      /**< Shifted mode ULFRCO for CMU_CTRL */
    180. 

  180. #define CMU_CTRL_CLKOUTSEL1                        (0x1UL << 23)                            /**< Clock Output Select 1 */
    181. 

  181. #define _CMU_CTRL_CLKOUTSEL1_SHIFT                 23                                       /**< Shift value for CMU_CLKOUTSEL1 */
    182. 

  182. #define _CMU_CTRL_CLKOUTSEL1_MASK                  0x800000UL                               /**< Bit mask for CMU_CLKOUTSEL1 */
    183. 

  183. #define _CMU_CTRL_CLKOUTSEL1_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_CTRL */
    184. 

  184. #define _CMU_CTRL_CLKOUTSEL1_LFRCO                 0x00000000UL                             /**< Mode LFRCO for CMU_CTRL */
    185. 

  185. #define _CMU_CTRL_CLKOUTSEL1_LFXO                  0x00000001UL                             /**< Mode LFXO for CMU_CTRL */
    186. 

  186. #define CMU_CTRL_CLKOUTSEL1_DEFAULT                (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)     /**< Shifted mode DEFAULT for CMU_CTRL */
    187. 

  187. #define CMU_CTRL_CLKOUTSEL1_LFRCO                  (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)       /**< Shifted mode LFRCO for CMU_CTRL */
    188. 

  188. #define CMU_CTRL_CLKOUTSEL1_LFXO                   (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)        /**< Shifted mode LFXO for CMU_CTRL */
    189. 

  189. 

  190. /* Bit fields for CMU HFCORECLKDIV */
    191. 

  191. #define _CMU_HFCORECLKDIV_RESETVALUE               0x00000000UL                                   /**< Default value for CMU_HFCORECLKDIV */
    192. 

  192. #define _CMU_HFCORECLKDIV_MASK                     0x0000000FUL                                   /**< Mask for CMU_HFCORECLKDIV */
    193. 

  193. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT       0                                              /**< Shift value for CMU_HFCORECLKDIV */
    194. 

  194. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK        0xFUL                                          /**< Bit mask for CMU_HFCORECLKDIV */
    195. 

  195. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT     0x00000000UL                                   /**< Mode DEFAULT for CMU_HFCORECLKDIV */
    196. 

  196. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK       0x00000000UL                                   /**< Mode HFCLK for CMU_HFCORECLKDIV */
    197. 

  197. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2      0x00000001UL                                   /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
    198. 

  198. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4      0x00000002UL                                   /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
    199. 

  199. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8      0x00000003UL                                   /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
    200. 

  200. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16     0x00000004UL                                   /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
    201. 

  201. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32     0x00000005UL                                   /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
    202. 

  202. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64     0x00000006UL                                   /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
    203. 

  203. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128    0x00000007UL                                   /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
    204. 

  204. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256    0x00000008UL                                   /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
    205. 

  205. #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512    0x00000009UL                                   /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
    206. 

  206. #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
    207. 

  207. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)    /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
    208. 

  208. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)   /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
    209. 

  209. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)   /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
    210. 

  210. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)   /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
    211. 

  211. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)  /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
    212. 

  212. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)  /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
    213. 

  213. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)  /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
    214. 

  214. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
    215. 

  215. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
    216. 

  216. #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
    217. 

  217. 

  218. /* Bit fields for CMU HFPERCLKDIV */
    219. 

  219. #define _CMU_HFPERCLKDIV_RESETVALUE                0x00000100UL                                 /**< Default value for CMU_HFPERCLKDIV */
    220. 

  220. #define _CMU_HFPERCLKDIV_MASK                      0x0000010FUL                                 /**< Mask for CMU_HFPERCLKDIV */
    221. 

  221. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT         0                                            /**< Shift value for CMU_HFPERCLKDIV */
    222. 

  222. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK          0xFUL                                        /**< Bit mask for CMU_HFPERCLKDIV */
    223. 

  223. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT       0x00000000UL                                 /**< Mode DEFAULT for CMU_HFPERCLKDIV */
    224. 

  224. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK         0x00000000UL                                 /**< Mode HFCLK for CMU_HFPERCLKDIV */
    225. 

  225. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2        0x00000001UL                                 /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
    226. 

  226. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4        0x00000002UL                                 /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
    227. 

  227. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8        0x00000003UL                                 /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
    228. 

  228. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16       0x00000004UL                                 /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
    229. 

  229. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32       0x00000005UL                                 /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
    230. 

  230. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64       0x00000006UL                                 /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
    231. 

  231. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128      0x00000007UL                                 /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
    232. 

  232. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256      0x00000008UL                                 /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
    233. 

  233. #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512      0x00000009UL                                 /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
    234. 

  234. #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
    235. 

  235. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
    236. 

  236. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
    237. 

  237. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
    238. 

  238. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
    239. 

  239. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
    240. 

  240. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
    241. 

  241. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
    242. 

  242. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
    243. 

  243. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
    244. 

  244. #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
    245. 

  245. #define CMU_HFPERCLKDIV_HFPERCLKEN                 (0x1UL << 8)                                 /**< HFPERCLK Enable */
    246. 

  246. #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT          8                                            /**< Shift value for CMU_HFPERCLKEN */
    247. 

  247. #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK           0x100UL                                      /**< Bit mask for CMU_HFPERCLKEN */
    248. 

  248. #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT        0x00000001UL                                 /**< Mode DEFAULT for CMU_HFPERCLKDIV */
    249. 

  249. #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
    250. 

  250. 

  251. /* Bit fields for CMU HFRCOCTRL */
    252. 

  252. #define _CMU_HFRCOCTRL_RESETVALUE                  0x00000380UL                           /**< Default value for CMU_HFRCOCTRL */
    253. 

  253. #define _CMU_HFRCOCTRL_MASK                        0x0001F7FFUL                           /**< Mask for CMU_HFRCOCTRL */
    254. 

  254. #define _CMU_HFRCOCTRL_TUNING_SHIFT                0                                      /**< Shift value for CMU_TUNING */
    255. 

  255. #define _CMU_HFRCOCTRL_TUNING_MASK                 0xFFUL                                 /**< Bit mask for CMU_TUNING */
    256. 

  256. #define _CMU_HFRCOCTRL_TUNING_DEFAULT              0x00000080UL                           /**< Mode DEFAULT for CMU_HFRCOCTRL */
    257. 

  257. #define CMU_HFRCOCTRL_TUNING_DEFAULT               (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
    258. 

  258. #define _CMU_HFRCOCTRL_BAND_SHIFT                  8                                      /**< Shift value for CMU_BAND */
    259. 

  259. #define _CMU_HFRCOCTRL_BAND_MASK                   0x700UL                                /**< Bit mask for CMU_BAND */
    260. 

  260. #define _CMU_HFRCOCTRL_BAND_1MHZ                   0x00000000UL                           /**< Mode 1MHZ for CMU_HFRCOCTRL */
    261. 

  261. #define _CMU_HFRCOCTRL_BAND_7MHZ                   0x00000001UL                           /**< Mode 7MHZ for CMU_HFRCOCTRL */
    262. 

  262. #define _CMU_HFRCOCTRL_BAND_11MHZ                  0x00000002UL                           /**< Mode 11MHZ for CMU_HFRCOCTRL */
    263. 

  263. #define _CMU_HFRCOCTRL_BAND_DEFAULT                0x00000003UL                           /**< Mode DEFAULT for CMU_HFRCOCTRL */
    264. 

  264. #define _CMU_HFRCOCTRL_BAND_14MHZ                  0x00000003UL                           /**< Mode 14MHZ for CMU_HFRCOCTRL */
    265. 

  265. #define _CMU_HFRCOCTRL_BAND_21MHZ                  0x00000004UL                           /**< Mode 21MHZ for CMU_HFRCOCTRL */
    266. 

  266. #define _CMU_HFRCOCTRL_BAND_28MHZ                  0x00000005UL                           /**< Mode 28MHZ for CMU_HFRCOCTRL */
    267. 

  267. #define CMU_HFRCOCTRL_BAND_1MHZ                    (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
    268. 

  268. #define CMU_HFRCOCTRL_BAND_7MHZ                    (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
    269. 

  269. #define CMU_HFRCOCTRL_BAND_11MHZ                   (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
    270. 

  270. #define CMU_HFRCOCTRL_BAND_DEFAULT                 (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
    271. 

  271. #define CMU_HFRCOCTRL_BAND_14MHZ                   (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
    272. 

  272. #define CMU_HFRCOCTRL_BAND_21MHZ                   (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
    273. 

  273. #define CMU_HFRCOCTRL_BAND_28MHZ                   (_CMU_HFRCOCTRL_BAND_28MHZ << 8)       /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
    274. 

  274. #define _CMU_HFRCOCTRL_SUDELAY_SHIFT               12                                     /**< Shift value for CMU_SUDELAY */
    275. 

  275. #define _CMU_HFRCOCTRL_SUDELAY_MASK                0x1F000UL                              /**< Bit mask for CMU_SUDELAY */
    276. 

  276. #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFRCOCTRL */
    277. 

  277. #define CMU_HFRCOCTRL_SUDELAY_DEFAULT              (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
    278. 

  278. 

  279. /* Bit fields for CMU LFRCOCTRL */
    280. 

  280. #define _CMU_LFRCOCTRL_RESETVALUE                  0x00000040UL                         /**< Default value for CMU_LFRCOCTRL */
    281. 

  281. #define _CMU_LFRCOCTRL_MASK                        0x0000007FUL                         /**< Mask for CMU_LFRCOCTRL */
    282. 

  282. #define _CMU_LFRCOCTRL_TUNING_SHIFT                0                                    /**< Shift value for CMU_TUNING */
    283. 

  283. #define _CMU_LFRCOCTRL_TUNING_MASK                 0x7FUL                               /**< Bit mask for CMU_TUNING */
    284. 

  284. #define _CMU_LFRCOCTRL_TUNING_DEFAULT              0x00000040UL                         /**< Mode DEFAULT for CMU_LFRCOCTRL */
    285. 

  285. #define CMU_LFRCOCTRL_TUNING_DEFAULT               (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
    286. 

  286. 

  287. /* Bit fields for CMU AUXHFRCOCTRL */
    288. 

  288. #define _CMU_AUXHFRCOCTRL_RESETVALUE               0x00000080UL                            /**< Default value for CMU_AUXHFRCOCTRL */
    289. 

  289. #define _CMU_AUXHFRCOCTRL_MASK                     0x000000FFUL                            /**< Mask for CMU_AUXHFRCOCTRL */
    290. 

  290. #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT             0                                       /**< Shift value for CMU_TUNING */
    291. 

  291. #define _CMU_AUXHFRCOCTRL_TUNING_MASK              0xFFUL                                  /**< Bit mask for CMU_TUNING */
    292. 

  292. #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT           0x00000080UL                            /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
    293. 

  293. #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT            (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
    294. 

  294. 

  295. /* Bit fields for CMU CALCTRL */
    296. 

  296. #define _CMU_CALCTRL_RESETVALUE                    0x00000000UL                       /**< Default value for CMU_CALCTRL */
    297. 

  297. #define _CMU_CALCTRL_MASK                          0x00000007UL                       /**< Mask for CMU_CALCTRL */
    298. 

  298. #define _CMU_CALCTRL_UPSEL_SHIFT                   0                                  /**< Shift value for CMU_UPSEL */
    299. 

  299. #define _CMU_CALCTRL_UPSEL_MASK                    0x7UL                              /**< Bit mask for CMU_UPSEL */
    300. 

  300. #define _CMU_CALCTRL_UPSEL_DEFAULT                 0x00000000UL                       /**< Mode DEFAULT for CMU_CALCTRL */
    301. 

  301. #define _CMU_CALCTRL_UPSEL_HFXO                    0x00000000UL                       /**< Mode HFXO for CMU_CALCTRL */
    302. 

  302. #define _CMU_CALCTRL_UPSEL_LFXO                    0x00000001UL                       /**< Mode LFXO for CMU_CALCTRL */
    303. 

  303. #define _CMU_CALCTRL_UPSEL_HFRCO                   0x00000002UL                       /**< Mode HFRCO for CMU_CALCTRL */
    304. 

  304. #define _CMU_CALCTRL_UPSEL_LFRCO                   0x00000003UL                       /**< Mode LFRCO for CMU_CALCTRL */
    305. 

  305. #define _CMU_CALCTRL_UPSEL_AUXHFRCO                0x00000004UL                       /**< Mode AUXHFRCO for CMU_CALCTRL */
    306. 

  306. #define CMU_CALCTRL_UPSEL_DEFAULT                  (_CMU_CALCTRL_UPSEL_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_CALCTRL */
    307. 

  307. #define CMU_CALCTRL_UPSEL_HFXO                     (_CMU_CALCTRL_UPSEL_HFXO << 0)     /**< Shifted mode HFXO for CMU_CALCTRL */
    308. 

  308. #define CMU_CALCTRL_UPSEL_LFXO                     (_CMU_CALCTRL_UPSEL_LFXO << 0)     /**< Shifted mode LFXO for CMU_CALCTRL */
    309. 

  309. #define CMU_CALCTRL_UPSEL_HFRCO                    (_CMU_CALCTRL_UPSEL_HFRCO << 0)    /**< Shifted mode HFRCO for CMU_CALCTRL */
    310. 

  310. #define CMU_CALCTRL_UPSEL_LFRCO                    (_CMU_CALCTRL_UPSEL_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_CALCTRL */
    311. 

  311. #define CMU_CALCTRL_UPSEL_AUXHFRCO                 (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
    312. 

  312. 

  313. /* Bit fields for CMU CALCNT */
    314. 

  314. #define _CMU_CALCNT_RESETVALUE                     0x00000000UL                      /**< Default value for CMU_CALCNT */
    315. 

  315. #define _CMU_CALCNT_MASK                           0x000FFFFFUL                      /**< Mask for CMU_CALCNT */
    316. 

  316. #define _CMU_CALCNT_CALCNT_SHIFT                   0                                 /**< Shift value for CMU_CALCNT */
    317. 

  317. #define _CMU_CALCNT_CALCNT_MASK                    0xFFFFFUL                         /**< Bit mask for CMU_CALCNT */
    318. 

  318. #define _CMU_CALCNT_CALCNT_DEFAULT                 0x00000000UL                      /**< Mode DEFAULT for CMU_CALCNT */
    319. 

  319. #define CMU_CALCNT_CALCNT_DEFAULT                  (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
    320. 

  320. 

  321. /* Bit fields for CMU OSCENCMD */
    322. 

  322. #define _CMU_OSCENCMD_RESETVALUE                   0x00000000UL                             /**< Default value for CMU_OSCENCMD */
    323. 

  323. #define _CMU_OSCENCMD_MASK                         0x000003FFUL                             /**< Mask for CMU_OSCENCMD */
    324. 

  324. #define CMU_OSCENCMD_HFRCOEN                       (0x1UL << 0)                             /**< HFRCO Enable */
    325. 

  325. #define _CMU_OSCENCMD_HFRCOEN_SHIFT                0                                        /**< Shift value for CMU_HFRCOEN */
    326. 

  326. #define _CMU_OSCENCMD_HFRCOEN_MASK                 0x1UL                                    /**< Bit mask for CMU_HFRCOEN */
    327. 

  327. #define _CMU_OSCENCMD_HFRCOEN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    328. 

  328. #define CMU_OSCENCMD_HFRCOEN_DEFAULT               (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    329. 

  329. #define CMU_OSCENCMD_HFRCODIS                      (0x1UL << 1)                             /**< HFRCO Disable */
    330. 

  330. #define _CMU_OSCENCMD_HFRCODIS_SHIFT               1                                        /**< Shift value for CMU_HFRCODIS */
    331. 

  331. #define _CMU_OSCENCMD_HFRCODIS_MASK                0x2UL                                    /**< Bit mask for CMU_HFRCODIS */
    332. 

  332. #define _CMU_OSCENCMD_HFRCODIS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    333. 

  333. #define CMU_OSCENCMD_HFRCODIS_DEFAULT              (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    334. 

  334. #define CMU_OSCENCMD_HFXOEN                        (0x1UL << 2)                             /**< HFXO Enable */
    335. 

  335. #define _CMU_OSCENCMD_HFXOEN_SHIFT                 2                                        /**< Shift value for CMU_HFXOEN */
    336. 

  336. #define _CMU_OSCENCMD_HFXOEN_MASK                  0x4UL                                    /**< Bit mask for CMU_HFXOEN */
    337. 

  337. #define _CMU_OSCENCMD_HFXOEN_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    338. 

  338. #define CMU_OSCENCMD_HFXOEN_DEFAULT                (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    339. 

  339. #define CMU_OSCENCMD_HFXODIS                       (0x1UL << 3)                             /**< HFXO Disable */
    340. 

  340. #define _CMU_OSCENCMD_HFXODIS_SHIFT                3                                        /**< Shift value for CMU_HFXODIS */
    341. 

  341. #define _CMU_OSCENCMD_HFXODIS_MASK                 0x8UL                                    /**< Bit mask for CMU_HFXODIS */
    342. 

  342. #define _CMU_OSCENCMD_HFXODIS_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    343. 

  343. #define CMU_OSCENCMD_HFXODIS_DEFAULT               (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    344. 

  344. #define CMU_OSCENCMD_AUXHFRCOEN                    (0x1UL << 4)                             /**< AUXHFRCO Enable */
    345. 

  345. #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT             4                                        /**< Shift value for CMU_AUXHFRCOEN */
    346. 

  346. #define _CMU_OSCENCMD_AUXHFRCOEN_MASK              0x10UL                                   /**< Bit mask for CMU_AUXHFRCOEN */
    347. 

  347. #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    348. 

  348. #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    349. 

  349. #define CMU_OSCENCMD_AUXHFRCODIS                   (0x1UL << 5)                             /**< AUXHFRCO Disable */
    350. 

  350. #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT            5                                        /**< Shift value for CMU_AUXHFRCODIS */
    351. 

  351. #define _CMU_OSCENCMD_AUXHFRCODIS_MASK             0x20UL                                   /**< Bit mask for CMU_AUXHFRCODIS */
    352. 

  352. #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    353. 

  353. #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    354. 

  354. #define CMU_OSCENCMD_LFRCOEN                       (0x1UL << 6)                             /**< LFRCO Enable */
    355. 

  355. #define _CMU_OSCENCMD_LFRCOEN_SHIFT                6                                        /**< Shift value for CMU_LFRCOEN */
    356. 

  356. #define _CMU_OSCENCMD_LFRCOEN_MASK                 0x40UL                                   /**< Bit mask for CMU_LFRCOEN */
    357. 

  357. #define _CMU_OSCENCMD_LFRCOEN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    358. 

  358. #define CMU_OSCENCMD_LFRCOEN_DEFAULT               (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    359. 

  359. #define CMU_OSCENCMD_LFRCODIS                      (0x1UL << 7)                             /**< LFRCO Disable */
    360. 

  360. #define _CMU_OSCENCMD_LFRCODIS_SHIFT               7                                        /**< Shift value for CMU_LFRCODIS */
    361. 

  361. #define _CMU_OSCENCMD_LFRCODIS_MASK                0x80UL                                   /**< Bit mask for CMU_LFRCODIS */
    362. 

  362. #define _CMU_OSCENCMD_LFRCODIS_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    363. 

  363. #define CMU_OSCENCMD_LFRCODIS_DEFAULT              (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    364. 

  364. #define CMU_OSCENCMD_LFXOEN                        (0x1UL << 8)                             /**< LFXO Enable */
    365. 

  365. #define _CMU_OSCENCMD_LFXOEN_SHIFT                 8                                        /**< Shift value for CMU_LFXOEN */
    366. 

  366. #define _CMU_OSCENCMD_LFXOEN_MASK                  0x100UL                                  /**< Bit mask for CMU_LFXOEN */
    367. 

  367. #define _CMU_OSCENCMD_LFXOEN_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    368. 

  368. #define CMU_OSCENCMD_LFXOEN_DEFAULT                (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    369. 

  369. #define CMU_OSCENCMD_LFXODIS                       (0x1UL << 9)                             /**< LFXO Disable */
    370. 

  370. #define _CMU_OSCENCMD_LFXODIS_SHIFT                9                                        /**< Shift value for CMU_LFXODIS */
    371. 

  371. #define _CMU_OSCENCMD_LFXODIS_MASK                 0x200UL                                  /**< Bit mask for CMU_LFXODIS */
    372. 

  372. #define _CMU_OSCENCMD_LFXODIS_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
    373. 

  373. #define CMU_OSCENCMD_LFXODIS_DEFAULT               (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
    374. 

  374. 

  375. /* Bit fields for CMU CMD */
    376. 

  376. #define _CMU_CMD_RESETVALUE                        0x00000000UL                     /**< Default value for CMU_CMD */
    377. 

  377. #define _CMU_CMD_MASK                              0x0000000FUL                     /**< Mask for CMU_CMD */
    378. 

  378. #define _CMU_CMD_HFCLKSEL_SHIFT                    0                                /**< Shift value for CMU_HFCLKSEL */
    379. 

  379. #define _CMU_CMD_HFCLKSEL_MASK                     0x7UL                            /**< Bit mask for CMU_HFCLKSEL */
    380. 

  380. #define _CMU_CMD_HFCLKSEL_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for CMU_CMD */
    381. 

  381. #define _CMU_CMD_HFCLKSEL_HFRCO                    0x00000001UL                     /**< Mode HFRCO for CMU_CMD */
    382. 

  382. #define _CMU_CMD_HFCLKSEL_HFXO                     0x00000002UL                     /**< Mode HFXO for CMU_CMD */
    383. 

  383. #define _CMU_CMD_HFCLKSEL_LFRCO                    0x00000003UL                     /**< Mode LFRCO for CMU_CMD */
    384. 

  384. #define _CMU_CMD_HFCLKSEL_LFXO                     0x00000004UL                     /**< Mode LFXO for CMU_CMD */
    385. 

  385. #define CMU_CMD_HFCLKSEL_DEFAULT                   (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
    386. 

  386. #define CMU_CMD_HFCLKSEL_HFRCO                     (_CMU_CMD_HFCLKSEL_HFRCO << 0)   /**< Shifted mode HFRCO for CMU_CMD */
    387. 

  387. #define CMU_CMD_HFCLKSEL_HFXO                      (_CMU_CMD_HFCLKSEL_HFXO << 0)    /**< Shifted mode HFXO for CMU_CMD */
    388. 

  388. #define CMU_CMD_HFCLKSEL_LFRCO                     (_CMU_CMD_HFCLKSEL_LFRCO << 0)   /**< Shifted mode LFRCO for CMU_CMD */
    389. 

  389. #define CMU_CMD_HFCLKSEL_LFXO                      (_CMU_CMD_HFCLKSEL_LFXO << 0)    /**< Shifted mode LFXO for CMU_CMD */
    390. 

  390. #define CMU_CMD_CALSTART                           (0x1UL << 3)                     /**< Calibration Start */
    391. 

  391. #define _CMU_CMD_CALSTART_SHIFT                    3                                /**< Shift value for CMU_CALSTART */
    392. 

  392. #define _CMU_CMD_CALSTART_MASK                     0x8UL                            /**< Bit mask for CMU_CALSTART */
    393. 

  393. #define _CMU_CMD_CALSTART_DEFAULT                  0x00000000UL                     /**< Mode DEFAULT for CMU_CMD */
    394. 

  394. #define CMU_CMD_CALSTART_DEFAULT                   (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
    395. 

  395. 

  396. /* Bit fields for CMU LFCLKSEL */
    397. 

  397. #define _CMU_LFCLKSEL_RESETVALUE                   0x00000005UL                             /**< Default value for CMU_LFCLKSEL */
    398. 

  398. #define _CMU_LFCLKSEL_MASK                         0x0000000FUL                             /**< Mask for CMU_LFCLKSEL */
    399. 

  399. #define _CMU_LFCLKSEL_LFA_SHIFT                    0                                        /**< Shift value for CMU_LFA */
    400. 

  400. #define _CMU_LFCLKSEL_LFA_MASK                     0x3UL                                    /**< Bit mask for CMU_LFA */
    401. 

  401. #define _CMU_LFCLKSEL_LFA_DISABLED                 0x00000000UL                             /**< Mode DISABLED for CMU_LFCLKSEL */
    402. 

  402. #define _CMU_LFCLKSEL_LFA_DEFAULT                  0x00000001UL                             /**< Mode DEFAULT for CMU_LFCLKSEL */
    403. 

  403. #define _CMU_LFCLKSEL_LFA_LFRCO                    0x00000001UL                             /**< Mode LFRCO for CMU_LFCLKSEL */
    404. 

  404. #define _CMU_LFCLKSEL_LFA_LFXO                     0x00000002UL                             /**< Mode LFXO for CMU_LFCLKSEL */
    405. 

  405. #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2          0x00000003UL                             /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
    406. 

  406. #define CMU_LFCLKSEL_LFA_DISABLED                  (_CMU_LFCLKSEL_LFA_DISABLED << 0)        /**< Shifted mode DISABLED for CMU_LFCLKSEL */
    407. 

  407. #define CMU_LFCLKSEL_LFA_DEFAULT                   (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
    408. 

  408. #define CMU_LFCLKSEL_LFA_LFRCO                     (_CMU_LFCLKSEL_LFA_LFRCO << 0)           /**< Shifted mode LFRCO for CMU_LFCLKSEL */
    409. 

  409. #define CMU_LFCLKSEL_LFA_LFXO                      (_CMU_LFCLKSEL_LFA_LFXO << 0)            /**< Shifted mode LFXO for CMU_LFCLKSEL */
    410. 

  410. #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
    411. 

  411. #define _CMU_LFCLKSEL_LFB_SHIFT                    2                                        /**< Shift value for CMU_LFB */
    412. 

  412. #define _CMU_LFCLKSEL_LFB_MASK                     0xCUL                                    /**< Bit mask for CMU_LFB */
    413. 

  413. #define _CMU_LFCLKSEL_LFB_DISABLED                 0x00000000UL                             /**< Mode DISABLED for CMU_LFCLKSEL */
    414. 

  414. #define _CMU_LFCLKSEL_LFB_DEFAULT                  0x00000001UL                             /**< Mode DEFAULT for CMU_LFCLKSEL */
    415. 

  415. #define _CMU_LFCLKSEL_LFB_LFRCO                    0x00000001UL                             /**< Mode LFRCO for CMU_LFCLKSEL */
    416. 

  416. #define _CMU_LFCLKSEL_LFB_LFXO                     0x00000002UL                             /**< Mode LFXO for CMU_LFCLKSEL */
    417. 

  417. #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2          0x00000003UL                             /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
    418. 

  418. #define CMU_LFCLKSEL_LFB_DISABLED                  (_CMU_LFCLKSEL_LFB_DISABLED << 2)        /**< Shifted mode DISABLED for CMU_LFCLKSEL */
    419. 

  419. #define CMU_LFCLKSEL_LFB_DEFAULT                   (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
    420. 

  420. #define CMU_LFCLKSEL_LFB_LFRCO                     (_CMU_LFCLKSEL_LFB_LFRCO << 2)           /**< Shifted mode LFRCO for CMU_LFCLKSEL */
    421. 

  421. #define CMU_LFCLKSEL_LFB_LFXO                      (_CMU_LFCLKSEL_LFB_LFXO << 2)            /**< Shifted mode LFXO for CMU_LFCLKSEL */
    422. 

  422. #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
    423. 

  423. 

  424. /* Bit fields for CMU STATUS */
    425. 

  425. #define _CMU_STATUS_RESETVALUE                     0x00000403UL                           /**< Default value for CMU_STATUS */
    426. 

  426. #define _CMU_STATUS_MASK                           0x00007FFFUL                           /**< Mask for CMU_STATUS */
    427. 

  427. #define CMU_STATUS_HFRCOENS                        (0x1UL << 0)                           /**< HFRCO Enable Status */
    428. 

  428. #define _CMU_STATUS_HFRCOENS_SHIFT                 0                                      /**< Shift value for CMU_HFRCOENS */
    429. 

  429. #define _CMU_STATUS_HFRCOENS_MASK                  0x1UL                                  /**< Bit mask for CMU_HFRCOENS */
    430. 

  430. #define _CMU_STATUS_HFRCOENS_DEFAULT               0x00000001UL                           /**< Mode DEFAULT for CMU_STATUS */
    431. 

  431. #define CMU_STATUS_HFRCOENS_DEFAULT                (_CMU_STATUS_HFRCOENS_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_STATUS */
    432. 

  432. #define CMU_STATUS_HFRCORDY                        (0x1UL << 1)                           /**< HFRCO Ready */
    433. 

  433. #define _CMU_STATUS_HFRCORDY_SHIFT                 1                                      /**< Shift value for CMU_HFRCORDY */
    434. 

  434. #define _CMU_STATUS_HFRCORDY_MASK                  0x2UL                                  /**< Bit mask for CMU_HFRCORDY */
    435. 

  435. #define _CMU_STATUS_HFRCORDY_DEFAULT               0x00000001UL                           /**< Mode DEFAULT for CMU_STATUS */
    436. 

  436. #define CMU_STATUS_HFRCORDY_DEFAULT                (_CMU_STATUS_HFRCORDY_DEFAULT << 1)    /**< Shifted mode DEFAULT for CMU_STATUS */
    437. 

  437. #define CMU_STATUS_HFXOENS                         (0x1UL << 2)                           /**< HFXO Enable Status */
    438. 

  438. #define _CMU_STATUS_HFXOENS_SHIFT                  2                                      /**< Shift value for CMU_HFXOENS */
    439. 

  439. #define _CMU_STATUS_HFXOENS_MASK                   0x4UL                                  /**< Bit mask for CMU_HFXOENS */
    440. 

  440. #define _CMU_STATUS_HFXOENS_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    441. 

  441. #define CMU_STATUS_HFXOENS_DEFAULT                 (_CMU_STATUS_HFXOENS_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_STATUS */
    442. 

  442. #define CMU_STATUS_HFXORDY                         (0x1UL << 3)                           /**< HFXO Ready */
    443. 

  443. #define _CMU_STATUS_HFXORDY_SHIFT                  3                                      /**< Shift value for CMU_HFXORDY */
    444. 

  444. #define _CMU_STATUS_HFXORDY_MASK                   0x8UL                                  /**< Bit mask for CMU_HFXORDY */
    445. 

  445. #define _CMU_STATUS_HFXORDY_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    446. 

  446. #define CMU_STATUS_HFXORDY_DEFAULT                 (_CMU_STATUS_HFXORDY_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_STATUS */
    447. 

  447. #define CMU_STATUS_AUXHFRCOENS                     (0x1UL << 4)                           /**< AUXHFRCO Enable Status */
    448. 

  448. #define _CMU_STATUS_AUXHFRCOENS_SHIFT              4                                      /**< Shift value for CMU_AUXHFRCOENS */
    449. 

  449. #define _CMU_STATUS_AUXHFRCOENS_MASK               0x10UL                                 /**< Bit mask for CMU_AUXHFRCOENS */
    450. 

  450. #define _CMU_STATUS_AUXHFRCOENS_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    451. 

  451. #define CMU_STATUS_AUXHFRCOENS_DEFAULT             (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
    452. 

  452. #define CMU_STATUS_AUXHFRCORDY                     (0x1UL << 5)                           /**< AUXHFRCO Ready */
    453. 

  453. #define _CMU_STATUS_AUXHFRCORDY_SHIFT              5                                      /**< Shift value for CMU_AUXHFRCORDY */
    454. 

  454. #define _CMU_STATUS_AUXHFRCORDY_MASK               0x20UL                                 /**< Bit mask for CMU_AUXHFRCORDY */
    455. 

  455. #define _CMU_STATUS_AUXHFRCORDY_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    456. 

  456. #define CMU_STATUS_AUXHFRCORDY_DEFAULT             (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
    457. 

  457. #define CMU_STATUS_LFRCOENS                        (0x1UL << 6)                           /**< LFRCO Enable Status */
    458. 

  458. #define _CMU_STATUS_LFRCOENS_SHIFT                 6                                      /**< Shift value for CMU_LFRCOENS */
    459. 

  459. #define _CMU_STATUS_LFRCOENS_MASK                  0x40UL                                 /**< Bit mask for CMU_LFRCOENS */
    460. 

  460. #define _CMU_STATUS_LFRCOENS_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    461. 

  461. #define CMU_STATUS_LFRCOENS_DEFAULT                (_CMU_STATUS_LFRCOENS_DEFAULT << 6)    /**< Shifted mode DEFAULT for CMU_STATUS */
    462. 

  462. #define CMU_STATUS_LFRCORDY                        (0x1UL << 7)                           /**< LFRCO Ready */
    463. 

  463. #define _CMU_STATUS_LFRCORDY_SHIFT                 7                                      /**< Shift value for CMU_LFRCORDY */
    464. 

  464. #define _CMU_STATUS_LFRCORDY_MASK                  0x80UL                                 /**< Bit mask for CMU_LFRCORDY */
    465. 

  465. #define _CMU_STATUS_LFRCORDY_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    466. 

  466. #define CMU_STATUS_LFRCORDY_DEFAULT                (_CMU_STATUS_LFRCORDY_DEFAULT << 7)    /**< Shifted mode DEFAULT for CMU_STATUS */
    467. 

  467. #define CMU_STATUS_LFXOENS                         (0x1UL << 8)                           /**< LFXO Enable Status */
    468. 

  468. #define _CMU_STATUS_LFXOENS_SHIFT                  8                                      /**< Shift value for CMU_LFXOENS */
    469. 

  469. #define _CMU_STATUS_LFXOENS_MASK                   0x100UL                                /**< Bit mask for CMU_LFXOENS */
    470. 

  470. #define _CMU_STATUS_LFXOENS_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    471. 

  471. #define CMU_STATUS_LFXOENS_DEFAULT                 (_CMU_STATUS_LFXOENS_DEFAULT << 8)     /**< Shifted mode DEFAULT for CMU_STATUS */
    472. 

  472. #define CMU_STATUS_LFXORDY                         (0x1UL << 9)                           /**< LFXO Ready */
    473. 

  473. #define _CMU_STATUS_LFXORDY_SHIFT                  9                                      /**< Shift value for CMU_LFXORDY */
    474. 

  474. #define _CMU_STATUS_LFXORDY_MASK                   0x200UL                                /**< Bit mask for CMU_LFXORDY */
    475. 

  475. #define _CMU_STATUS_LFXORDY_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    476. 

  476. #define CMU_STATUS_LFXORDY_DEFAULT                 (_CMU_STATUS_LFXORDY_DEFAULT << 9)     /**< Shifted mode DEFAULT for CMU_STATUS */
    477. 

  477. #define CMU_STATUS_HFRCOSEL                        (0x1UL << 10)                          /**< HFRCO Selected */
    478. 

  478. #define _CMU_STATUS_HFRCOSEL_SHIFT                 10                                     /**< Shift value for CMU_HFRCOSEL */
    479. 

  479. #define _CMU_STATUS_HFRCOSEL_MASK                  0x400UL                                /**< Bit mask for CMU_HFRCOSEL */
    480. 

  480. #define _CMU_STATUS_HFRCOSEL_DEFAULT               0x00000001UL                           /**< Mode DEFAULT for CMU_STATUS */
    481. 

  481. #define CMU_STATUS_HFRCOSEL_DEFAULT                (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)   /**< Shifted mode DEFAULT for CMU_STATUS */
    482. 

  482. #define CMU_STATUS_HFXOSEL                         (0x1UL << 11)                          /**< HFXO Selected */
    483. 

  483. #define _CMU_STATUS_HFXOSEL_SHIFT                  11                                     /**< Shift value for CMU_HFXOSEL */
    484. 

  484. #define _CMU_STATUS_HFXOSEL_MASK                   0x800UL                                /**< Bit mask for CMU_HFXOSEL */
    485. 

  485. #define _CMU_STATUS_HFXOSEL_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    486. 

  486. #define CMU_STATUS_HFXOSEL_DEFAULT                 (_CMU_STATUS_HFXOSEL_DEFAULT << 11)    /**< Shifted mode DEFAULT for CMU_STATUS */
    487. 

  487. #define CMU_STATUS_LFRCOSEL                        (0x1UL << 12)                          /**< LFRCO Selected */
    488. 

  488. #define _CMU_STATUS_LFRCOSEL_SHIFT                 12                                     /**< Shift value for CMU_LFRCOSEL */
    489. 

  489. #define _CMU_STATUS_LFRCOSEL_MASK                  0x1000UL                               /**< Bit mask for CMU_LFRCOSEL */
    490. 

  490. #define _CMU_STATUS_LFRCOSEL_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    491. 

  491. #define CMU_STATUS_LFRCOSEL_DEFAULT                (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)   /**< Shifted mode DEFAULT for CMU_STATUS */
    492. 

  492. #define CMU_STATUS_LFXOSEL                         (0x1UL << 13)                          /**< LFXO Selected */
    493. 

  493. #define _CMU_STATUS_LFXOSEL_SHIFT                  13                                     /**< Shift value for CMU_LFXOSEL */
    494. 

  494. #define _CMU_STATUS_LFXOSEL_MASK                   0x2000UL                               /**< Bit mask for CMU_LFXOSEL */
    495. 

  495. #define _CMU_STATUS_LFXOSEL_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    496. 

  496. #define CMU_STATUS_LFXOSEL_DEFAULT                 (_CMU_STATUS_LFXOSEL_DEFAULT << 13)    /**< Shifted mode DEFAULT for CMU_STATUS */
    497. 

  497. #define CMU_STATUS_CALBSY                          (0x1UL << 14)                          /**< Calibration Busy */
    498. 

  498. #define _CMU_STATUS_CALBSY_SHIFT                   14                                     /**< Shift value for CMU_CALBSY */
    499. 

  499. #define _CMU_STATUS_CALBSY_MASK                    0x4000UL                               /**< Bit mask for CMU_CALBSY */
    500. 

  500. #define _CMU_STATUS_CALBSY_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for CMU_STATUS */
    501. 

  501. #define CMU_STATUS_CALBSY_DEFAULT                  (_CMU_STATUS_CALBSY_DEFAULT << 14)     /**< Shifted mode DEFAULT for CMU_STATUS */
    502. 

  502. 

  503. /* Bit fields for CMU IF */
    504. 

  504. #define _CMU_IF_RESETVALUE                         0x00000001UL                       /**< Default value for CMU_IF */
    505. 

  505. #define _CMU_IF_MASK                               0x0000003FUL                       /**< Mask for CMU_IF */
    506. 

  506. #define CMU_IF_HFRCORDY                            (0x1UL << 0)                       /**< HFRCO Ready Interrupt Flag */
    507. 

  507. #define _CMU_IF_HFRCORDY_SHIFT                     0                                  /**< Shift value for CMU_HFRCORDY */
    508. 

  508. #define _CMU_IF_HFRCORDY_MASK                      0x1UL                              /**< Bit mask for CMU_HFRCORDY */
    509. 

  509. #define _CMU_IF_HFRCORDY_DEFAULT                   0x00000001UL                       /**< Mode DEFAULT for CMU_IF */
    510. 

  510. #define CMU_IF_HFRCORDY_DEFAULT                    (_CMU_IF_HFRCORDY_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_IF */
    511. 

  511. #define CMU_IF_HFXORDY                             (0x1UL << 1)                       /**< HFXO Ready Interrupt Flag */
    512. 

  512. #define _CMU_IF_HFXORDY_SHIFT                      1                                  /**< Shift value for CMU_HFXORDY */
    513. 

  513. #define _CMU_IF_HFXORDY_MASK                       0x2UL                              /**< Bit mask for CMU_HFXORDY */
    514. 

  514. #define _CMU_IF_HFXORDY_DEFAULT                    0x00000000UL                       /**< Mode DEFAULT for CMU_IF */
    515. 

  515. #define CMU_IF_HFXORDY_DEFAULT                     (_CMU_IF_HFXORDY_DEFAULT << 1)     /**< Shifted mode DEFAULT for CMU_IF */
    516. 

  516. #define CMU_IF_LFRCORDY                            (0x1UL << 2)                       /**< LFRCO Ready Interrupt Flag */
    517. 

  517. #define _CMU_IF_LFRCORDY_SHIFT                     2                                  /**< Shift value for CMU_LFRCORDY */
    518. 

  518. #define _CMU_IF_LFRCORDY_MASK                      0x4UL                              /**< Bit mask for CMU_LFRCORDY */
    519. 

  519. #define _CMU_IF_LFRCORDY_DEFAULT                   0x00000000UL                       /**< Mode DEFAULT for CMU_IF */
    520. 

  520. #define CMU_IF_LFRCORDY_DEFAULT                    (_CMU_IF_LFRCORDY_DEFAULT << 2)    /**< Shifted mode DEFAULT for CMU_IF */
    521. 

  521. #define CMU_IF_LFXORDY                             (0x1UL << 3)                       /**< LFXO Ready Interrupt Flag */
    522. 

  522. #define _CMU_IF_LFXORDY_SHIFT                      3                                  /**< Shift value for CMU_LFXORDY */
    523. 

  523. #define _CMU_IF_LFXORDY_MASK                       0x8UL                              /**< Bit mask for CMU_LFXORDY */
    524. 

  524. #define _CMU_IF_LFXORDY_DEFAULT                    0x00000000UL                       /**< Mode DEFAULT for CMU_IF */
    525. 

  525. #define CMU_IF_LFXORDY_DEFAULT                     (_CMU_IF_LFXORDY_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_IF */
    526. 

  526. #define CMU_IF_AUXHFRCORDY                         (0x1UL << 4)                       /**< AUXHFRCO Ready Interrupt Flag */
    527. 

  527. #define _CMU_IF_AUXHFRCORDY_SHIFT                  4                                  /**< Shift value for CMU_AUXHFRCORDY */
    528. 

  528. #define _CMU_IF_AUXHFRCORDY_MASK                   0x10UL                             /**< Bit mask for CMU_AUXHFRCORDY */
    529. 

  529. #define _CMU_IF_AUXHFRCORDY_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for CMU_IF */
    530. 

  530. #define CMU_IF_AUXHFRCORDY_DEFAULT                 (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
    531. 

  531. #define CMU_IF_CALRDY                              (0x1UL << 5)                       /**< Calibration Ready Interrupt Flag */
    532. 

  532. #define _CMU_IF_CALRDY_SHIFT                       5                                  /**< Shift value for CMU_CALRDY */
    533. 

  533. #define _CMU_IF_CALRDY_MASK                        0x20UL                             /**< Bit mask for CMU_CALRDY */
    534. 

  534. #define _CMU_IF_CALRDY_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for CMU_IF */
    535. 

  535. #define CMU_IF_CALRDY_DEFAULT                      (_CMU_IF_CALRDY_DEFAULT << 5)      /**< Shifted mode DEFAULT for CMU_IF */
    536. 

  536. 

  537. /* Bit fields for CMU IFS */
    538. 

  538. #define _CMU_IFS_RESETVALUE                        0x00000000UL                        /**< Default value for CMU_IFS */
    539. 

  539. #define _CMU_IFS_MASK                              0x0000003FUL                        /**< Mask for CMU_IFS */
    540. 

  540. #define CMU_IFS_HFRCORDY                           (0x1UL << 0)                        /**< HFRCO Ready Interrupt Flag Set */
    541. 

  541. #define _CMU_IFS_HFRCORDY_SHIFT                    0                                   /**< Shift value for CMU_HFRCORDY */
    542. 

  542. #define _CMU_IFS_HFRCORDY_MASK                     0x1UL                               /**< Bit mask for CMU_HFRCORDY */
    543. 

  543. #define _CMU_IFS_HFRCORDY_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CMU_IFS */
    544. 

  544. #define CMU_IFS_HFRCORDY_DEFAULT                   (_CMU_IFS_HFRCORDY_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_IFS */
    545. 

  545. #define CMU_IFS_HFXORDY                            (0x1UL << 1)                        /**< HFXO Ready Interrupt Flag Set */
    546. 

  546. #define _CMU_IFS_HFXORDY_SHIFT                     1                                   /**< Shift value for CMU_HFXORDY */
    547. 

  547. #define _CMU_IFS_HFXORDY_MASK                      0x2UL                               /**< Bit mask for CMU_HFXORDY */
    548. 

  548. #define _CMU_IFS_HFXORDY_DEFAULT                   0x00000000UL                        /**< Mode DEFAULT for CMU_IFS */
    549. 

  549. #define CMU_IFS_HFXORDY_DEFAULT                    (_CMU_IFS_HFXORDY_DEFAULT << 1)     /**< Shifted mode DEFAULT for CMU_IFS */
    550. 

  550. #define CMU_IFS_LFRCORDY                           (0x1UL << 2)                        /**< LFRCO Ready Interrupt Flag Set */
    551. 

  551. #define _CMU_IFS_LFRCORDY_SHIFT                    2                                   /**< Shift value for CMU_LFRCORDY */
    552. 

  552. #define _CMU_IFS_LFRCORDY_MASK                     0x4UL                               /**< Bit mask for CMU_LFRCORDY */
    553. 

  553. #define _CMU_IFS_LFRCORDY_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CMU_IFS */
    554. 

  554. #define CMU_IFS_LFRCORDY_DEFAULT                   (_CMU_IFS_LFRCORDY_DEFAULT << 2)    /**< Shifted mode DEFAULT for CMU_IFS */
    555. 

  555. #define CMU_IFS_LFXORDY                            (0x1UL << 3)                        /**< LFXO Ready Interrupt Flag Set */
    556. 

  556. #define _CMU_IFS_LFXORDY_SHIFT                     3                                   /**< Shift value for CMU_LFXORDY */
    557. 

  557. #define _CMU_IFS_LFXORDY_MASK                      0x8UL                               /**< Bit mask for CMU_LFXORDY */
    558. 

  558. #define _CMU_IFS_LFXORDY_DEFAULT                   0x00000000UL                        /**< Mode DEFAULT for CMU_IFS */
    559. 

  559. #define CMU_IFS_LFXORDY_DEFAULT                    (_CMU_IFS_LFXORDY_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_IFS */
    560. 

  560. #define CMU_IFS_AUXHFRCORDY                        (0x1UL << 4)                        /**< AUXHFRCO Ready Interrupt Flag Set */
    561. 

  561. #define _CMU_IFS_AUXHFRCORDY_SHIFT                 4                                   /**< Shift value for CMU_AUXHFRCORDY */
    562. 

  562. #define _CMU_IFS_AUXHFRCORDY_MASK                  0x10UL                              /**< Bit mask for CMU_AUXHFRCORDY */
    563. 

  563. #define _CMU_IFS_AUXHFRCORDY_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for CMU_IFS */
    564. 

  564. #define CMU_IFS_AUXHFRCORDY_DEFAULT                (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
    565. 

  565. #define CMU_IFS_CALRDY                             (0x1UL << 5)                        /**< Calibration Ready Interrupt Flag Set */
    566. 

  566. #define _CMU_IFS_CALRDY_SHIFT                      5                                   /**< Shift value for CMU_CALRDY */
    567. 

  567. #define _CMU_IFS_CALRDY_MASK                       0x20UL                              /**< Bit mask for CMU_CALRDY */
    568. 

  568. #define _CMU_IFS_CALRDY_DEFAULT                    0x00000000UL                        /**< Mode DEFAULT for CMU_IFS */
    569. 

  569. #define CMU_IFS_CALRDY_DEFAULT                     (_CMU_IFS_CALRDY_DEFAULT << 5)      /**< Shifted mode DEFAULT for CMU_IFS */
    570. 

  570. 

  571. /* Bit fields for CMU IFC */
    572. 

  572. #define _CMU_IFC_RESETVALUE                        0x00000000UL                        /**< Default value for CMU_IFC */
    573. 

  573. #define _CMU_IFC_MASK                              0x0000003FUL                        /**< Mask for CMU_IFC */
    574. 

  574. #define CMU_IFC_HFRCORDY                           (0x1UL << 0)                        /**< HFRCO Ready Interrupt Flag Clear */
    575. 

  575. #define _CMU_IFC_HFRCORDY_SHIFT                    0                                   /**< Shift value for CMU_HFRCORDY */
    576. 

  576. #define _CMU_IFC_HFRCORDY_MASK                     0x1UL                               /**< Bit mask for CMU_HFRCORDY */
    577. 

  577. #define _CMU_IFC_HFRCORDY_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CMU_IFC */
    578. 

  578. #define CMU_IFC_HFRCORDY_DEFAULT                   (_CMU_IFC_HFRCORDY_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_IFC */
    579. 

  579. #define CMU_IFC_HFXORDY                            (0x1UL << 1)                        /**< HFXO Ready Interrupt Flag Clear */
    580. 

  580. #define _CMU_IFC_HFXORDY_SHIFT                     1                                   /**< Shift value for CMU_HFXORDY */
    581. 

  581. #define _CMU_IFC_HFXORDY_MASK                      0x2UL                               /**< Bit mask for CMU_HFXORDY */
    582. 

  582. #define _CMU_IFC_HFXORDY_DEFAULT                   0x00000000UL                        /**< Mode DEFAULT for CMU_IFC */
    583. 

  583. #define CMU_IFC_HFXORDY_DEFAULT                    (_CMU_IFC_HFXORDY_DEFAULT << 1)     /**< Shifted mode DEFAULT for CMU_IFC */
    584. 

  584. #define CMU_IFC_LFRCORDY                           (0x1UL << 2)                        /**< LFRCO Ready Interrupt Flag Clear */
    585. 

  585. #define _CMU_IFC_LFRCORDY_SHIFT                    2                                   /**< Shift value for CMU_LFRCORDY */
    586. 

  586. #define _CMU_IFC_LFRCORDY_MASK                     0x4UL                               /**< Bit mask for CMU_LFRCORDY */
    587. 

  587. #define _CMU_IFC_LFRCORDY_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CMU_IFC */
    588. 

  588. #define CMU_IFC_LFRCORDY_DEFAULT                   (_CMU_IFC_LFRCORDY_DEFAULT << 2)    /**< Shifted mode DEFAULT for CMU_IFC */
    589. 

  589. #define CMU_IFC_LFXORDY                            (0x1UL << 3)                        /**< LFXO Ready Interrupt Flag Clear */
    590. 

  590. #define _CMU_IFC_LFXORDY_SHIFT                     3                                   /**< Shift value for CMU_LFXORDY */
    591. 

  591. #define _CMU_IFC_LFXORDY_MASK                      0x8UL                               /**< Bit mask for CMU_LFXORDY */
    592. 

  592. #define _CMU_IFC_LFXORDY_DEFAULT                   0x00000000UL                        /**< Mode DEFAULT for CMU_IFC */
    593. 

  593. #define CMU_IFC_LFXORDY_DEFAULT                    (_CMU_IFC_LFXORDY_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_IFC */
    594. 

  594. #define CMU_IFC_AUXHFRCORDY                        (0x1UL << 4)                        /**< AUXHFRCO Ready Interrupt Flag Clear */
    595. 

  595. #define _CMU_IFC_AUXHFRCORDY_SHIFT                 4                                   /**< Shift value for CMU_AUXHFRCORDY */
    596. 

  596. #define _CMU_IFC_AUXHFRCORDY_MASK                  0x10UL                              /**< Bit mask for CMU_AUXHFRCORDY */
    597. 

  597. #define _CMU_IFC_AUXHFRCORDY_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for CMU_IFC */
    598. 

  598. #define CMU_IFC_AUXHFRCORDY_DEFAULT                (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
    599. 

  599. #define CMU_IFC_CALRDY                             (0x1UL << 5)                        /**< Calibration Ready Interrupt Flag Clear */
    600. 

  600. #define _CMU_IFC_CALRDY_SHIFT                      5                                   /**< Shift value for CMU_CALRDY */
    601. 

  601. #define _CMU_IFC_CALRDY_MASK                       0x20UL                              /**< Bit mask for CMU_CALRDY */
    602. 

  602. #define _CMU_IFC_CALRDY_DEFAULT                    0x00000000UL                        /**< Mode DEFAULT for CMU_IFC */
    603. 

  603. #define CMU_IFC_CALRDY_DEFAULT                     (_CMU_IFC_CALRDY_DEFAULT << 5)      /**< Shifted mode DEFAULT for CMU_IFC */
    604. 

  604. 

  605. /* Bit fields for CMU IEN */
    606. 

  606. #define _CMU_IEN_RESETVALUE                        0x00000000UL                        /**< Default value for CMU_IEN */
    607. 

  607. #define _CMU_IEN_MASK                              0x0000003FUL                        /**< Mask for CMU_IEN */
    608. 

  608. #define CMU_IEN_HFRCORDY                           (0x1UL << 0)                        /**< HFRCO Ready Interrupt Enable */
    609. 

  609. #define _CMU_IEN_HFRCORDY_SHIFT                    0                                   /**< Shift value for CMU_HFRCORDY */
    610. 

  610. #define _CMU_IEN_HFRCORDY_MASK                     0x1UL                               /**< Bit mask for CMU_HFRCORDY */
    611. 

  611. #define _CMU_IEN_HFRCORDY_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CMU_IEN */
    612. 

  612. #define CMU_IEN_HFRCORDY_DEFAULT                   (_CMU_IEN_HFRCORDY_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_IEN */
    613. 

  613. #define CMU_IEN_HFXORDY                            (0x1UL << 1)                        /**< HFXO Ready Interrupt Enable */
    614. 

  614. #define _CMU_IEN_HFXORDY_SHIFT                     1                                   /**< Shift value for CMU_HFXORDY */
    615. 

  615. #define _CMU_IEN_HFXORDY_MASK                      0x2UL                               /**< Bit mask for CMU_HFXORDY */
    616. 

  616. #define _CMU_IEN_HFXORDY_DEFAULT                   0x00000000UL                        /**< Mode DEFAULT for CMU_IEN */
    617. 

  617. #define CMU_IEN_HFXORDY_DEFAULT                    (_CMU_IEN_HFXORDY_DEFAULT << 1)     /**< Shifted mode DEFAULT for CMU_IEN */
    618. 

  618. #define CMU_IEN_LFRCORDY                           (0x1UL << 2)                        /**< LFRCO Ready Interrupt Enable */
    619. 

  619. #define _CMU_IEN_LFRCORDY_SHIFT                    2                                   /**< Shift value for CMU_LFRCORDY */
    620. 

  620. #define _CMU_IEN_LFRCORDY_MASK                     0x4UL                               /**< Bit mask for CMU_LFRCORDY */
    621. 

  621. #define _CMU_IEN_LFRCORDY_DEFAULT                  0x00000000UL                        /**< Mode DEFAULT for CMU_IEN */
    622. 

  622. #define CMU_IEN_LFRCORDY_DEFAULT                   (_CMU_IEN_LFRCORDY_DEFAULT << 2)    /**< Shifted mode DEFAULT for CMU_IEN */
    623. 

  623. #define CMU_IEN_LFXORDY                            (0x1UL << 3)                        /**< LFXO Ready Interrupt Enable */
    624. 

  624. #define _CMU_IEN_LFXORDY_SHIFT                     3                                   /**< Shift value for CMU_LFXORDY */
    625. 

  625. #define _CMU_IEN_LFXORDY_MASK                      0x8UL                               /**< Bit mask for CMU_LFXORDY */
    626. 

  626. #define _CMU_IEN_LFXORDY_DEFAULT                   0x00000000UL                        /**< Mode DEFAULT for CMU_IEN */
    627. 

  627. #define CMU_IEN_LFXORDY_DEFAULT                    (_CMU_IEN_LFXORDY_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_IEN */
    628. 

  628. #define CMU_IEN_AUXHFRCORDY                        (0x1UL << 4)                        /**< AUXHFRCO Ready Interrupt Enable */
    629. 

  629. #define _CMU_IEN_AUXHFRCORDY_SHIFT                 4                                   /**< Shift value for CMU_AUXHFRCORDY */
    630. 

  630. #define _CMU_IEN_AUXHFRCORDY_MASK                  0x10UL                              /**< Bit mask for CMU_AUXHFRCORDY */
    631. 

  631. #define _CMU_IEN_AUXHFRCORDY_DEFAULT               0x00000000UL                        /**< Mode DEFAULT for CMU_IEN */
    632. 

  632. #define CMU_IEN_AUXHFRCORDY_DEFAULT                (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
    633. 

  633. #define CMU_IEN_CALRDY                             (0x1UL << 5)                        /**< Calibration Ready Interrupt Enable */
    634. 

  634. #define _CMU_IEN_CALRDY_SHIFT                      5                                   /**< Shift value for CMU_CALRDY */
    635. 

  635. #define _CMU_IEN_CALRDY_MASK                       0x20UL                              /**< Bit mask for CMU_CALRDY */
    636. 

  636. #define _CMU_IEN_CALRDY_DEFAULT                    0x00000000UL                        /**< Mode DEFAULT for CMU_IEN */
    637. 

  637. #define CMU_IEN_CALRDY_DEFAULT                     (_CMU_IEN_CALRDY_DEFAULT << 5)      /**< Shifted mode DEFAULT for CMU_IEN */
    638. 

  638. 

  639. /* Bit fields for CMU HFCORECLKEN0 */
    640. 

  640. #define _CMU_HFCORECLKEN0_RESETVALUE               0x00000000UL                         /**< Default value for CMU_HFCORECLKEN0 */
    641. 

  641. #define _CMU_HFCORECLKEN0_MASK                     0x0000000FUL                         /**< Mask for CMU_HFCORECLKEN0 */
    642. 

  642. #define CMU_HFCORECLKEN0_AES                       (0x1UL << 0)                         /**< Advanced Encryption Standard Accelerator Clock Enable */
    643. 

  643. #define _CMU_HFCORECLKEN0_AES_SHIFT                0                                    /**< Shift value for CMU_AES */
    644. 

  644. #define _CMU_HFCORECLKEN0_AES_MASK                 0x1UL                                /**< Bit mask for CMU_AES */
    645. 

  645. #define _CMU_HFCORECLKEN0_AES_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
    646. 

  646. #define CMU_HFCORECLKEN0_AES_DEFAULT               (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
    647. 

  647. #define CMU_HFCORECLKEN0_DMA                       (0x1UL << 1)                         /**< Direct Memory Access Controller Clock Enable */
    648. 

  648. #define _CMU_HFCORECLKEN0_DMA_SHIFT                1                                    /**< Shift value for CMU_DMA */
    649. 

  649. #define _CMU_HFCORECLKEN0_DMA_MASK                 0x2UL                                /**< Bit mask for CMU_DMA */
    650. 

  650. #define _CMU_HFCORECLKEN0_DMA_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
    651. 

  651. #define CMU_HFCORECLKEN0_DMA_DEFAULT               (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
    652. 

  652. #define CMU_HFCORECLKEN0_LE                        (0x1UL << 2)                         /**< Low Energy Peripheral Interface Clock Enable */
    653. 

  653. #define _CMU_HFCORECLKEN0_LE_SHIFT                 2                                    /**< Shift value for CMU_LE */
    654. 

  654. #define _CMU_HFCORECLKEN0_LE_MASK                  0x4UL                                /**< Bit mask for CMU_LE */
    655. 

  655. #define _CMU_HFCORECLKEN0_LE_DEFAULT               0x00000000UL                         /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
    656. 

  656. #define CMU_HFCORECLKEN0_LE_DEFAULT                (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)  /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
    657. 

  657. #define CMU_HFCORECLKEN0_EBI                       (0x1UL << 3)                         /**< External Bus Interface Clock Enable */
    658. 

  658. #define _CMU_HFCORECLKEN0_EBI_SHIFT                3                                    /**< Shift value for CMU_EBI */
    659. 

  659. #define _CMU_HFCORECLKEN0_EBI_MASK                 0x8UL                                /**< Bit mask for CMU_EBI */
    660. 

  660. #define _CMU_HFCORECLKEN0_EBI_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
    661. 

  661. #define CMU_HFCORECLKEN0_EBI_DEFAULT               (_CMU_HFCORECLKEN0_EBI_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
    662. 

  662. 

  663. /* Bit fields for CMU HFPERCLKEN0 */
    664. 

  664. #define _CMU_HFPERCLKEN0_RESETVALUE                0x00000000UL                           /**< Default value for CMU_HFPERCLKEN0 */
    665. 

  665. #define _CMU_HFPERCLKEN0_MASK                      0x0000FFFFUL                           /**< Mask for CMU_HFPERCLKEN0 */
    666. 

  666. #define CMU_HFPERCLKEN0_USART0                     (0x1UL << 0)                           /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
    667. 

  667. #define _CMU_HFPERCLKEN0_USART0_SHIFT              0                                      /**< Shift value for CMU_USART0 */
    668. 

  668. #define _CMU_HFPERCLKEN0_USART0_MASK               0x1UL                                  /**< Bit mask for CMU_USART0 */
    669. 

  669. #define _CMU_HFPERCLKEN0_USART0_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    670. 

  670. #define CMU_HFPERCLKEN0_USART0_DEFAULT             (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    671. 

  671. #define CMU_HFPERCLKEN0_USART1                     (0x1UL << 1)                           /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
    672. 

  672. #define _CMU_HFPERCLKEN0_USART1_SHIFT              1                                      /**< Shift value for CMU_USART1 */
    673. 

  673. #define _CMU_HFPERCLKEN0_USART1_MASK               0x2UL                                  /**< Bit mask for CMU_USART1 */
    674. 

  674. #define _CMU_HFPERCLKEN0_USART1_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    675. 

  675. #define CMU_HFPERCLKEN0_USART1_DEFAULT             (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    676. 

  676. #define CMU_HFPERCLKEN0_USART2                     (0x1UL << 2)                           /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
    677. 

  677. #define _CMU_HFPERCLKEN0_USART2_SHIFT              2                                      /**< Shift value for CMU_USART2 */
    678. 

  678. #define _CMU_HFPERCLKEN0_USART2_MASK               0x4UL                                  /**< Bit mask for CMU_USART2 */
    679. 

  679. #define _CMU_HFPERCLKEN0_USART2_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    680. 

  680. #define CMU_HFPERCLKEN0_USART2_DEFAULT             (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    681. 

  681. #define CMU_HFPERCLKEN0_UART0                      (0x1UL << 3)                           /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */
    682. 

  682. #define _CMU_HFPERCLKEN0_UART0_SHIFT               3                                      /**< Shift value for CMU_UART0 */
    683. 

  683. #define _CMU_HFPERCLKEN0_UART0_MASK                0x8UL                                  /**< Bit mask for CMU_UART0 */
    684. 

  684. #define _CMU_HFPERCLKEN0_UART0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    685. 

  685. #define CMU_HFPERCLKEN0_UART0_DEFAULT              (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    686. 

  686. #define CMU_HFPERCLKEN0_TIMER0                     (0x1UL << 4)                           /**< Timer 0 Clock Enable */
    687. 

  687. #define _CMU_HFPERCLKEN0_TIMER0_SHIFT              4                                      /**< Shift value for CMU_TIMER0 */
    688. 

  688. #define _CMU_HFPERCLKEN0_TIMER0_MASK               0x10UL                                 /**< Bit mask for CMU_TIMER0 */
    689. 

  689. #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    690. 

  690. #define CMU_HFPERCLKEN0_TIMER0_DEFAULT             (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    691. 

  691. #define CMU_HFPERCLKEN0_TIMER1                     (0x1UL << 5)                           /**< Timer 1 Clock Enable */
    692. 

  692. #define _CMU_HFPERCLKEN0_TIMER1_SHIFT              5                                      /**< Shift value for CMU_TIMER1 */
    693. 

  693. #define _CMU_HFPERCLKEN0_TIMER1_MASK               0x20UL                                 /**< Bit mask for CMU_TIMER1 */
    694. 

  694. #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    695. 

  695. #define CMU_HFPERCLKEN0_TIMER1_DEFAULT             (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    696. 

  696. #define CMU_HFPERCLKEN0_TIMER2                     (0x1UL << 6)                           /**< Timer 2 Clock Enable */
    697. 

  697. #define _CMU_HFPERCLKEN0_TIMER2_SHIFT              6                                      /**< Shift value for CMU_TIMER2 */
    698. 

  698. #define _CMU_HFPERCLKEN0_TIMER2_MASK               0x40UL                                 /**< Bit mask for CMU_TIMER2 */
    699. 

  699. #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    700. 

  700. #define CMU_HFPERCLKEN0_TIMER2_DEFAULT             (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    701. 

  701. #define CMU_HFPERCLKEN0_ACMP0                      (0x1UL << 7)                           /**< Analog Comparator 0 Clock Enable */
    702. 

  702. #define _CMU_HFPERCLKEN0_ACMP0_SHIFT               7                                      /**< Shift value for CMU_ACMP0 */
    703. 

  703. #define _CMU_HFPERCLKEN0_ACMP0_MASK                0x80UL                                 /**< Bit mask for CMU_ACMP0 */
    704. 

  704. #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    705. 

  705. #define CMU_HFPERCLKEN0_ACMP0_DEFAULT              (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    706. 

  706. #define CMU_HFPERCLKEN0_ACMP1                      (0x1UL << 8)                           /**< Analog Comparator 1 Clock Enable */
    707. 

  707. #define _CMU_HFPERCLKEN0_ACMP1_SHIFT               8                                      /**< Shift value for CMU_ACMP1 */
    708. 

  708. #define _CMU_HFPERCLKEN0_ACMP1_MASK                0x100UL                                /**< Bit mask for CMU_ACMP1 */
    709. 

  709. #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    710. 

  710. #define CMU_HFPERCLKEN0_ACMP1_DEFAULT              (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    711. 

  711. #define CMU_HFPERCLKEN0_PRS                        (0x1UL << 10)                          /**< Peripheral Reflex System Clock Enable */
    712. 

  712. #define _CMU_HFPERCLKEN0_PRS_SHIFT                 10                                     /**< Shift value for CMU_PRS */
    713. 

  713. #define _CMU_HFPERCLKEN0_PRS_MASK                  0x400UL                                /**< Bit mask for CMU_PRS */
    714. 

  714. #define _CMU_HFPERCLKEN0_PRS_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    715. 

  715. #define CMU_HFPERCLKEN0_PRS_DEFAULT                (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10)   /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    716. 

  716. #define CMU_HFPERCLKEN0_DAC0                       (0x1UL << 11)                          /**< Digital to Analog Converter 0 Clock Enable */
    717. 

  717. #define _CMU_HFPERCLKEN0_DAC0_SHIFT                11                                     /**< Shift value for CMU_DAC0 */
    718. 

  718. #define _CMU_HFPERCLKEN0_DAC0_MASK                 0x800UL                                /**< Bit mask for CMU_DAC0 */
    719. 

  719. #define _CMU_HFPERCLKEN0_DAC0_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    720. 

  720. #define CMU_HFPERCLKEN0_DAC0_DEFAULT               (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    721. 

  721. #define CMU_HFPERCLKEN0_GPIO                       (0x1UL << 12)                          /**< General purpose Input/Output Clock Enable */
    722. 

  722. #define _CMU_HFPERCLKEN0_GPIO_SHIFT                12                                     /**< Shift value for CMU_GPIO */
    723. 

  723. #define _CMU_HFPERCLKEN0_GPIO_MASK                 0x1000UL                               /**< Bit mask for CMU_GPIO */
    724. 

  724. #define _CMU_HFPERCLKEN0_GPIO_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    725. 

  725. #define CMU_HFPERCLKEN0_GPIO_DEFAULT               (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    726. 

  726. #define CMU_HFPERCLKEN0_VCMP                       (0x1UL << 13)                          /**< Voltage Comparator Clock Enable */
    727. 

  727. #define _CMU_HFPERCLKEN0_VCMP_SHIFT                13                                     /**< Shift value for CMU_VCMP */
    728. 

  728. #define _CMU_HFPERCLKEN0_VCMP_MASK                 0x2000UL                               /**< Bit mask for CMU_VCMP */
    729. 

  729. #define _CMU_HFPERCLKEN0_VCMP_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    730. 

  730. #define CMU_HFPERCLKEN0_VCMP_DEFAULT               (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    731. 

  731. #define CMU_HFPERCLKEN0_ADC0                       (0x1UL << 14)                          /**< Analog to Digital Converter 0 Clock Enable */
    732. 

  732. #define _CMU_HFPERCLKEN0_ADC0_SHIFT                14                                     /**< Shift value for CMU_ADC0 */
    733. 

  733. #define _CMU_HFPERCLKEN0_ADC0_MASK                 0x4000UL                               /**< Bit mask for CMU_ADC0 */
    734. 

  734. #define _CMU_HFPERCLKEN0_ADC0_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    735. 

  735. #define CMU_HFPERCLKEN0_ADC0_DEFAULT               (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    736. 

  736. #define CMU_HFPERCLKEN0_I2C0                       (0x1UL << 15)                          /**< I2C 0 Clock Enable */
    737. 

  737. #define _CMU_HFPERCLKEN0_I2C0_SHIFT                15                                     /**< Shift value for CMU_I2C0 */
    738. 

  738. #define _CMU_HFPERCLKEN0_I2C0_MASK                 0x8000UL                               /**< Bit mask for CMU_I2C0 */
    739. 

  739. #define _CMU_HFPERCLKEN0_I2C0_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
    740. 

  740. #define CMU_HFPERCLKEN0_I2C0_DEFAULT               (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15)  /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
    741. 

  741. 

  742. /* Bit fields for CMU SYNCBUSY */
    743. 

  743. #define _CMU_SYNCBUSY_RESETVALUE                   0x00000000UL                           /**< Default value for CMU_SYNCBUSY */
    744. 

  744. #define _CMU_SYNCBUSY_MASK                         0x00000055UL                           /**< Mask for CMU_SYNCBUSY */
    745. 

  745. #define CMU_SYNCBUSY_LFACLKEN0                     (0x1UL << 0)                           /**< Low Frequency A Clock Enable 0 Busy */
    746. 

  746. #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT              0                                      /**< Shift value for CMU_LFACLKEN0 */
    747. 

  747. #define _CMU_SYNCBUSY_LFACLKEN0_MASK               0x1UL                                  /**< Bit mask for CMU_LFACLKEN0 */
    748. 

  748. #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
    749. 

  749. #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT             (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
    750. 

  750. #define CMU_SYNCBUSY_LFAPRESC0                     (0x1UL << 2)                           /**< Low Frequency A Prescaler 0 Busy */
    751. 

  751. #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT              2                                      /**< Shift value for CMU_LFAPRESC0 */
    752. 

  752. #define _CMU_SYNCBUSY_LFAPRESC0_MASK               0x4UL                                  /**< Bit mask for CMU_LFAPRESC0 */
    753. 

  753. #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
    754. 

  754. #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT             (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
    755. 

  755. #define CMU_SYNCBUSY_LFBCLKEN0                     (0x1UL << 4)                           /**< Low Frequency B Clock Enable 0 Busy */
    756. 

  756. #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT              4                                      /**< Shift value for CMU_LFBCLKEN0 */
    757. 

  757. #define _CMU_SYNCBUSY_LFBCLKEN0_MASK               0x10UL                                 /**< Bit mask for CMU_LFBCLKEN0 */
    758. 

  758. #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
    759. 

  759. #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
    760. 

  760. #define CMU_SYNCBUSY_LFBPRESC0                     (0x1UL << 6)                           /**< Low Frequency B Prescaler 0 Busy */
    761. 

  761. #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT              6                                      /**< Shift value for CMU_LFBPRESC0 */
    762. 

  762. #define _CMU_SYNCBUSY_LFBPRESC0_MASK               0x40UL                                 /**< Bit mask for CMU_LFBPRESC0 */
    763. 

  763. #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_SYNCBUSY */
    764. 

  764. #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT             (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
    765. 

  765. 

  766. /* Bit fields for CMU FREEZE */
    767. 

  767. #define _CMU_FREEZE_RESETVALUE                     0x00000000UL                         /**< Default value for CMU_FREEZE */
    768. 

  768. #define _CMU_FREEZE_MASK                           0x00000001UL                         /**< Mask for CMU_FREEZE */
    769. 

  769. #define CMU_FREEZE_REGFREEZE                       (0x1UL << 0)                         /**< Register Update Freeze */
    770. 

  770. #define _CMU_FREEZE_REGFREEZE_SHIFT                0                                    /**< Shift value for CMU_REGFREEZE */
    771. 

  771. #define _CMU_FREEZE_REGFREEZE_MASK                 0x1UL                                /**< Bit mask for CMU_REGFREEZE */
    772. 

  772. #define _CMU_FREEZE_REGFREEZE_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for CMU_FREEZE */
    773. 

  773. #define _CMU_FREEZE_REGFREEZE_UPDATE               0x00000000UL                         /**< Mode UPDATE for CMU_FREEZE */
    774. 

  774. #define _CMU_FREEZE_REGFREEZE_FREEZE               0x00000001UL                         /**< Mode FREEZE for CMU_FREEZE */
    775. 

  775. #define CMU_FREEZE_REGFREEZE_DEFAULT               (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
    776. 

  776. #define CMU_FREEZE_REGFREEZE_UPDATE                (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for CMU_FREEZE */
    777. 

  777. #define CMU_FREEZE_REGFREEZE_FREEZE                (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for CMU_FREEZE */
    778. 

  778. 

  779. /* Bit fields for CMU LFACLKEN0 */
    780. 

  780. #define _CMU_LFACLKEN0_RESETVALUE                  0x00000000UL                           /**< Default value for CMU_LFACLKEN0 */
    781. 

  781. #define _CMU_LFACLKEN0_MASK                        0x00000007UL                           /**< Mask for CMU_LFACLKEN0 */
    782. 

  782. #define CMU_LFACLKEN0_RTC                          (0x1UL << 0)                           /**< Real-Time Counter Clock Enable */
    783. 

  783. #define _CMU_LFACLKEN0_RTC_SHIFT                   0                                      /**< Shift value for CMU_RTC */
    784. 

  784. #define _CMU_LFACLKEN0_RTC_MASK                    0x1UL                                  /**< Bit mask for CMU_RTC */
    785. 

  785. #define _CMU_LFACLKEN0_RTC_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
    786. 

  786. #define CMU_LFACLKEN0_RTC_DEFAULT                  (_CMU_LFACLKEN0_RTC_DEFAULT << 0)      /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
    787. 

  787. #define CMU_LFACLKEN0_LETIMER0                     (0x1UL << 1)                           /**< Low Energy Timer 0 Clock Enable */
    788. 

  788. #define _CMU_LFACLKEN0_LETIMER0_SHIFT              1                                      /**< Shift value for CMU_LETIMER0 */
    789. 

  789. #define _CMU_LFACLKEN0_LETIMER0_MASK               0x2UL                                  /**< Bit mask for CMU_LETIMER0 */
    790. 

  790. #define _CMU_LFACLKEN0_LETIMER0_DEFAULT            0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
    791. 

  791. #define CMU_LFACLKEN0_LETIMER0_DEFAULT             (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
    792. 

  792. #define CMU_LFACLKEN0_LCD                          (0x1UL << 2)                           /**< Liquid Crystal Display Controller Clock Enable */
    793. 

  793. #define _CMU_LFACLKEN0_LCD_SHIFT                   2                                      /**< Shift value for CMU_LCD */
    794. 

  794. #define _CMU_LFACLKEN0_LCD_MASK                    0x4UL                                  /**< Bit mask for CMU_LCD */
    795. 

  795. #define _CMU_LFACLKEN0_LCD_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
    796. 

  796. #define CMU_LFACLKEN0_LCD_DEFAULT                  (_CMU_LFACLKEN0_LCD_DEFAULT << 2)      /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
    797. 

  797. 

  798. /* Bit fields for CMU LFBCLKEN0 */
    799. 

  799. #define _CMU_LFBCLKEN0_RESETVALUE                  0x00000000UL                          /**< Default value for CMU_LFBCLKEN0 */
    800. 

  800. #define _CMU_LFBCLKEN0_MASK                        0x00000003UL                          /**< Mask for CMU_LFBCLKEN0 */
    801. 

  801. #define CMU_LFBCLKEN0_LEUART0                      (0x1UL << 0)                          /**< Low Energy UART 0 Clock Enable */
    802. 

  802. #define _CMU_LFBCLKEN0_LEUART0_SHIFT               0                                     /**< Shift value for CMU_LEUART0 */
    803. 

  803. #define _CMU_LFBCLKEN0_LEUART0_MASK                0x1UL                                 /**< Bit mask for CMU_LEUART0 */
    804. 

  804. #define _CMU_LFBCLKEN0_LEUART0_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
    805. 

  805. #define CMU_LFBCLKEN0_LEUART0_DEFAULT              (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
    806. 

  806. #define CMU_LFBCLKEN0_LEUART1                      (0x1UL << 1)                          /**< Low Energy UART 1 Clock Enable */
    807. 

  807. #define _CMU_LFBCLKEN0_LEUART1_SHIFT               1                                     /**< Shift value for CMU_LEUART1 */
    808. 

  808. #define _CMU_LFBCLKEN0_LEUART1_MASK                0x2UL                                 /**< Bit mask for CMU_LEUART1 */
    809. 

  809. #define _CMU_LFBCLKEN0_LEUART1_DEFAULT             0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
    810. 

  810. #define CMU_LFBCLKEN0_LEUART1_DEFAULT              (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
    811. 

  811. 

  812. /* Bit fields for CMU LFAPRESC0 */
    813. 

  813. #define _CMU_LFAPRESC0_RESETVALUE                  0x00000000UL                            /**< Default value for CMU_LFAPRESC0 */
    814. 

  814. #define _CMU_LFAPRESC0_MASK                        0x000003FFUL                            /**< Mask for CMU_LFAPRESC0 */
    815. 

  815. #define _CMU_LFAPRESC0_RTC_SHIFT                   0                                       /**< Shift value for CMU_RTC */
    816. 

  816. #define _CMU_LFAPRESC0_RTC_MASK                    0xFUL                                   /**< Bit mask for CMU_RTC */
    817. 

  817. #define _CMU_LFAPRESC0_RTC_DIV1                    0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
    818. 

  818. #define _CMU_LFAPRESC0_RTC_DIV2                    0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
    819. 

  819. #define _CMU_LFAPRESC0_RTC_DIV4                    0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
    820. 

  820. #define _CMU_LFAPRESC0_RTC_DIV8                    0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
    821. 

  821. #define _CMU_LFAPRESC0_RTC_DIV16                   0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
    822. 

  822. #define _CMU_LFAPRESC0_RTC_DIV32                   0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
    823. 

  823. #define _CMU_LFAPRESC0_RTC_DIV64                   0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
    824. 

  824. #define _CMU_LFAPRESC0_RTC_DIV128                  0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
    825. 

  825. #define _CMU_LFAPRESC0_RTC_DIV256                  0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
    826. 

  826. #define _CMU_LFAPRESC0_RTC_DIV512                  0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
    827. 

  827. #define _CMU_LFAPRESC0_RTC_DIV1024                 0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
    828. 

  828. #define _CMU_LFAPRESC0_RTC_DIV2048                 0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
    829. 

  829. #define _CMU_LFAPRESC0_RTC_DIV4096                 0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
    830. 

  830. #define _CMU_LFAPRESC0_RTC_DIV8192                 0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
    831. 

  831. #define _CMU_LFAPRESC0_RTC_DIV16384                0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
    832. 

  832. #define _CMU_LFAPRESC0_RTC_DIV32768                0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
    833. 

  833. #define CMU_LFAPRESC0_RTC_DIV1                     (_CMU_LFAPRESC0_RTC_DIV1 << 0)          /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
    834. 

  834. #define CMU_LFAPRESC0_RTC_DIV2                     (_CMU_LFAPRESC0_RTC_DIV2 << 0)          /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
    835. 

  835. #define CMU_LFAPRESC0_RTC_DIV4                     (_CMU_LFAPRESC0_RTC_DIV4 << 0)          /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
    836. 

  836. #define CMU_LFAPRESC0_RTC_DIV8                     (_CMU_LFAPRESC0_RTC_DIV8 << 0)          /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
    837. 

  837. #define CMU_LFAPRESC0_RTC_DIV16                    (_CMU_LFAPRESC0_RTC_DIV16 << 0)         /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
    838. 

  838. #define CMU_LFAPRESC0_RTC_DIV32                    (_CMU_LFAPRESC0_RTC_DIV32 << 0)         /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
    839. 

  839. #define CMU_LFAPRESC0_RTC_DIV64                    (_CMU_LFAPRESC0_RTC_DIV64 << 0)         /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
    840. 

  840. #define CMU_LFAPRESC0_RTC_DIV128                   (_CMU_LFAPRESC0_RTC_DIV128 << 0)        /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
    841. 

  841. #define CMU_LFAPRESC0_RTC_DIV256                   (_CMU_LFAPRESC0_RTC_DIV256 << 0)        /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
    842. 

  842. #define CMU_LFAPRESC0_RTC_DIV512                   (_CMU_LFAPRESC0_RTC_DIV512 << 0)        /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
    843. 

  843. #define CMU_LFAPRESC0_RTC_DIV1024                  (_CMU_LFAPRESC0_RTC_DIV1024 << 0)       /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
    844. 

  844. #define CMU_LFAPRESC0_RTC_DIV2048                  (_CMU_LFAPRESC0_RTC_DIV2048 << 0)       /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
    845. 

  845. #define CMU_LFAPRESC0_RTC_DIV4096                  (_CMU_LFAPRESC0_RTC_DIV4096 << 0)       /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
    846. 

  846. #define CMU_LFAPRESC0_RTC_DIV8192                  (_CMU_LFAPRESC0_RTC_DIV8192 << 0)       /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
    847. 

  847. #define CMU_LFAPRESC0_RTC_DIV16384                 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)      /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
    848. 

  848. #define CMU_LFAPRESC0_RTC_DIV32768                 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)      /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
    849. 

  849. #define _CMU_LFAPRESC0_LETIMER0_SHIFT              4                                       /**< Shift value for CMU_LETIMER0 */
    850. 

  850. #define _CMU_LFAPRESC0_LETIMER0_MASK               0xF0UL                                  /**< Bit mask for CMU_LETIMER0 */
    851. 

  851. #define _CMU_LFAPRESC0_LETIMER0_DIV1               0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
    852. 

  852. #define _CMU_LFAPRESC0_LETIMER0_DIV2               0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
    853. 

  853. #define _CMU_LFAPRESC0_LETIMER0_DIV4               0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
    854. 

  854. #define _CMU_LFAPRESC0_LETIMER0_DIV8               0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
    855. 

  855. #define _CMU_LFAPRESC0_LETIMER0_DIV16              0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
    856. 

  856. #define _CMU_LFAPRESC0_LETIMER0_DIV32              0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
    857. 

  857. #define _CMU_LFAPRESC0_LETIMER0_DIV64              0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
    858. 

  858. #define _CMU_LFAPRESC0_LETIMER0_DIV128             0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
    859. 

  859. #define _CMU_LFAPRESC0_LETIMER0_DIV256             0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
    860. 

  860. #define _CMU_LFAPRESC0_LETIMER0_DIV512             0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
    861. 

  861. #define _CMU_LFAPRESC0_LETIMER0_DIV1024            0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
    862. 

  862. #define _CMU_LFAPRESC0_LETIMER0_DIV2048            0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
    863. 

  863. #define _CMU_LFAPRESC0_LETIMER0_DIV4096            0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
    864. 

  864. #define _CMU_LFAPRESC0_LETIMER0_DIV8192            0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
    865. 

  865. #define _CMU_LFAPRESC0_LETIMER0_DIV16384           0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
    866. 

  866. #define _CMU_LFAPRESC0_LETIMER0_DIV32768           0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
    867. 

  867. #define CMU_LFAPRESC0_LETIMER0_DIV1                (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)     /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
    868. 

  868. #define CMU_LFAPRESC0_LETIMER0_DIV2                (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)     /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
    869. 

  869. #define CMU_LFAPRESC0_LETIMER0_DIV4                (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)     /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
    870. 

  870. #define CMU_LFAPRESC0_LETIMER0_DIV8                (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)     /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
    871. 

  871. #define CMU_LFAPRESC0_LETIMER0_DIV16               (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)    /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
    872. 

  872. #define CMU_LFAPRESC0_LETIMER0_DIV32               (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)    /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
    873. 

  873. #define CMU_LFAPRESC0_LETIMER0_DIV64               (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)    /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
    874. 

  874. #define CMU_LFAPRESC0_LETIMER0_DIV128              (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)   /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
    875. 

  875. #define CMU_LFAPRESC0_LETIMER0_DIV256              (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)   /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
    876. 

  876. #define CMU_LFAPRESC0_LETIMER0_DIV512              (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)   /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
    877. 

  877. #define CMU_LFAPRESC0_LETIMER0_DIV1024             (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)  /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
    878. 

  878. #define CMU_LFAPRESC0_LETIMER0_DIV2048             (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)  /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
    879. 

  879. #define CMU_LFAPRESC0_LETIMER0_DIV4096             (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)  /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
    880. 

  880. #define CMU_LFAPRESC0_LETIMER0_DIV8192             (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)  /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
    881. 

  881. #define CMU_LFAPRESC0_LETIMER0_DIV16384            (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
    882. 

  882. #define CMU_LFAPRESC0_LETIMER0_DIV32768            (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
    883. 

  883. #define _CMU_LFAPRESC0_LCD_SHIFT                   8                                       /**< Shift value for CMU_LCD */
    884. 

  884. #define _CMU_LFAPRESC0_LCD_MASK                    0x300UL                                 /**< Bit mask for CMU_LCD */
    885. 

  885. #define _CMU_LFAPRESC0_LCD_DIV16                   0x00000000UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
    886. 

  886. #define _CMU_LFAPRESC0_LCD_DIV32                   0x00000001UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
    887. 

  887. #define _CMU_LFAPRESC0_LCD_DIV64                   0x00000002UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
    888. 

  888. #define _CMU_LFAPRESC0_LCD_DIV128                  0x00000003UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
    889. 

  889. #define CMU_LFAPRESC0_LCD_DIV16                    (_CMU_LFAPRESC0_LCD_DIV16 << 8)         /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
    890. 

  890. #define CMU_LFAPRESC0_LCD_DIV32                    (_CMU_LFAPRESC0_LCD_DIV32 << 8)         /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
    891. 

  891. #define CMU_LFAPRESC0_LCD_DIV64                    (_CMU_LFAPRESC0_LCD_DIV64 << 8)         /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
    892. 

  892. #define CMU_LFAPRESC0_LCD_DIV128                   (_CMU_LFAPRESC0_LCD_DIV128 << 8)        /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
    893. 

  893. 

  894. /* Bit fields for CMU LFBPRESC0 */
    895. 

  895. #define _CMU_LFBPRESC0_RESETVALUE                  0x00000000UL                       /**< Default value for CMU_LFBPRESC0 */
    896. 

  896. #define _CMU_LFBPRESC0_MASK                        0x00000033UL                       /**< Mask for CMU_LFBPRESC0 */
    897. 

  897. #define _CMU_LFBPRESC0_LEUART0_SHIFT               0                                  /**< Shift value for CMU_LEUART0 */
    898. 

  898. #define _CMU_LFBPRESC0_LEUART0_MASK                0x3UL                              /**< Bit mask for CMU_LEUART0 */
    899. 

  899. #define _CMU_LFBPRESC0_LEUART0_DIV1                0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
    900. 

  900. #define _CMU_LFBPRESC0_LEUART0_DIV2                0x00000001UL                       /**< Mode DIV2 for CMU_LFBPRESC0 */
    901. 

  901. #define _CMU_LFBPRESC0_LEUART0_DIV4                0x00000002UL                       /**< Mode DIV4 for CMU_LFBPRESC0 */
    902. 

  902. #define _CMU_LFBPRESC0_LEUART0_DIV8                0x00000003UL                       /**< Mode DIV8 for CMU_LFBPRESC0 */
    903. 

  903. #define CMU_LFBPRESC0_LEUART0_DIV1                 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
    904. 

  904. #define CMU_LFBPRESC0_LEUART0_DIV2                 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
    905. 

  905. #define CMU_LFBPRESC0_LEUART0_DIV4                 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
    906. 

  906. #define CMU_LFBPRESC0_LEUART0_DIV8                 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
    907. 

  907. #define _CMU_LFBPRESC0_LEUART1_SHIFT               4                                  /**< Shift value for CMU_LEUART1 */
    908. 

  908. #define _CMU_LFBPRESC0_LEUART1_MASK                0x30UL                             /**< Bit mask for CMU_LEUART1 */
    909. 

  909. #define _CMU_LFBPRESC0_LEUART1_DIV1                0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
    910. 

  910. #define _CMU_LFBPRESC0_LEUART1_DIV2                0x00000001UL                       /**< Mode DIV2 for CMU_LFBPRESC0 */
    911. 

  911. #define _CMU_LFBPRESC0_LEUART1_DIV4                0x00000002UL                       /**< Mode DIV4 for CMU_LFBPRESC0 */
    912. 

  912. #define _CMU_LFBPRESC0_LEUART1_DIV8                0x00000003UL                       /**< Mode DIV8 for CMU_LFBPRESC0 */
    913. 

  913. #define CMU_LFBPRESC0_LEUART1_DIV1                 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
    914. 

  914. #define CMU_LFBPRESC0_LEUART1_DIV2                 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
    915. 

  915. #define CMU_LFBPRESC0_LEUART1_DIV4                 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
    916. 

  916. #define CMU_LFBPRESC0_LEUART1_DIV8                 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
    917. 

  917. 

  918. /* Bit fields for CMU PCNTCTRL */
    919. 

  919. #define _CMU_PCNTCTRL_RESETVALUE                   0x00000000UL                             /**< Default value for CMU_PCNTCTRL */
    920. 

  920. #define _CMU_PCNTCTRL_MASK                         0x0000003FUL                             /**< Mask for CMU_PCNTCTRL */
    921. 

  921. #define CMU_PCNTCTRL_PCNT0CLKEN                    (0x1UL << 0)                             /**< PCNT0 Clock Enable */
    922. 

  922. #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT             0                                        /**< Shift value for CMU_PCNT0CLKEN */
    923. 

  923. #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK              0x1UL                                    /**< Bit mask for CMU_PCNT0CLKEN */
    924. 

  924. #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
    925. 

  925. #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
    926. 

  926. #define CMU_PCNTCTRL_PCNT0CLKSEL                   (0x1UL << 1)                             /**< PCNT0 Clock Select */
    927. 

  927. #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT            1                                        /**< Shift value for CMU_PCNT0CLKSEL */
    928. 

  928. #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK             0x2UL                                    /**< Bit mask for CMU_PCNT0CLKSEL */
    929. 

  929. #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
    930. 

  930. #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK           0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
    931. 

  931. #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0          0x00000001UL                             /**< Mode PCNT0S0 for CMU_PCNTCTRL */
    932. 

  932. #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
    933. 

  933. #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
    934. 

  934. #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
    935. 

  935. #define CMU_PCNTCTRL_PCNT1CLKEN                    (0x1UL << 2)                             /**< PCNT1 Clock Enable */
    936. 

  936. #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT             2                                        /**< Shift value for CMU_PCNT1CLKEN */
    937. 

  937. #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK              0x4UL                                    /**< Bit mask for CMU_PCNT1CLKEN */
    938. 

  938. #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
    939. 

  939. #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT            (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
    940. 

  940. #define CMU_PCNTCTRL_PCNT1CLKSEL                   (0x1UL << 3)                             /**< PCNT1 Clock Select */
    941. 

  941. #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT            3                                        /**< Shift value for CMU_PCNT1CLKSEL */
    942. 

  942. #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK             0x8UL                                    /**< Bit mask for CMU_PCNT1CLKSEL */
    943. 

  943. #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
    944. 

  944. #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK           0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
    945. 

  945. #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0          0x00000001UL                             /**< Mode PCNT1S0 for CMU_PCNTCTRL */
    946. 

  946. #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT           (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
    947. 

  947. #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK            (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
    948. 

  948. #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0           (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
    949. 

  949. #define CMU_PCNTCTRL_PCNT2CLKEN                    (0x1UL << 4)                             /**< PCNT2 Clock Enable */
    950. 

  950. #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT             4                                        /**< Shift value for CMU_PCNT2CLKEN */
    951. 

  951. #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK              0x10UL                                   /**< Bit mask for CMU_PCNT2CLKEN */
    952. 

  952. #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
    953. 

  953. #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT            (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
    954. 

  954. #define CMU_PCNTCTRL_PCNT2CLKSEL                   (0x1UL << 5)                             /**< PCNT2 Clock Select */
    955. 

  955. #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT            5                                        /**< Shift value for CMU_PCNT2CLKSEL */
    956. 

  956. #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK             0x20UL                                   /**< Bit mask for CMU_PCNT2CLKSEL */
    957. 

  957. #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT          0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
    958. 

  958. #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK           0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
    959. 

  959. #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0          0x00000001UL                             /**< Mode PCNT2S0 for CMU_PCNTCTRL */
    960. 

  960. #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT           (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
    961. 

  961. #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK            (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
    962. 

  962. #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0           (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
    963. 

  963. 

  964. /* Bit fields for CMU LCDCTRL */
    965. 

  965. #define _CMU_LCDCTRL_RESETVALUE                    0x00000020UL                         /**< Default value for CMU_LCDCTRL */
    966. 

  966. #define _CMU_LCDCTRL_MASK                          0x0000007FUL                         /**< Mask for CMU_LCDCTRL */
    967. 

  967. #define _CMU_LCDCTRL_FDIV_SHIFT                    0                                    /**< Shift value for CMU_FDIV */
    968. 

  968. #define _CMU_LCDCTRL_FDIV_MASK                     0x7UL                                /**< Bit mask for CMU_FDIV */
    969. 

  969. #define _CMU_LCDCTRL_FDIV_DEFAULT                  0x00000000UL                         /**< Mode DEFAULT for CMU_LCDCTRL */
    970. 

  970. #define CMU_LCDCTRL_FDIV_DEFAULT                   (_CMU_LCDCTRL_FDIV_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_LCDCTRL */
    971. 

  971. #define CMU_LCDCTRL_VBOOSTEN                       (0x1UL << 3)                         /**< Voltage Boost Enable */
    972. 

  972. #define _CMU_LCDCTRL_VBOOSTEN_SHIFT                3                                    /**< Shift value for CMU_VBOOSTEN */
    973. 

  973. #define _CMU_LCDCTRL_VBOOSTEN_MASK                 0x8UL                                /**< Bit mask for CMU_VBOOSTEN */
    974. 

  974. #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for CMU_LCDCTRL */
    975. 

  975. #define CMU_LCDCTRL_VBOOSTEN_DEFAULT               (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
    976. 

  976. #define _CMU_LCDCTRL_VBFDIV_SHIFT                  4                                    /**< Shift value for CMU_VBFDIV */
    977. 

  977. #define _CMU_LCDCTRL_VBFDIV_MASK                   0x70UL                               /**< Bit mask for CMU_VBFDIV */
    978. 

  978. #define _CMU_LCDCTRL_VBFDIV_DIV1                   0x00000000UL                         /**< Mode DIV1 for CMU_LCDCTRL */
    979. 

  979. #define _CMU_LCDCTRL_VBFDIV_DIV2                   0x00000001UL                         /**< Mode DIV2 for CMU_LCDCTRL */
    980. 

  980. #define _CMU_LCDCTRL_VBFDIV_DEFAULT                0x00000002UL                         /**< Mode DEFAULT for CMU_LCDCTRL */
    981. 

  981. #define _CMU_LCDCTRL_VBFDIV_DIV4                   0x00000002UL                         /**< Mode DIV4 for CMU_LCDCTRL */
    982. 

  982. #define _CMU_LCDCTRL_VBFDIV_DIV8                   0x00000003UL                         /**< Mode DIV8 for CMU_LCDCTRL */
    983. 

  983. #define _CMU_LCDCTRL_VBFDIV_DIV16                  0x00000004UL                         /**< Mode DIV16 for CMU_LCDCTRL */
    984. 

  984. #define _CMU_LCDCTRL_VBFDIV_DIV32                  0x00000005UL                         /**< Mode DIV32 for CMU_LCDCTRL */
    985. 

  985. #define _CMU_LCDCTRL_VBFDIV_DIV64                  0x00000006UL                         /**< Mode DIV64 for CMU_LCDCTRL */
    986. 

  986. #define _CMU_LCDCTRL_VBFDIV_DIV128                 0x00000007UL                         /**< Mode DIV128 for CMU_LCDCTRL */
    987. 

  987. #define CMU_LCDCTRL_VBFDIV_DIV1                    (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)      /**< Shifted mode DIV1 for CMU_LCDCTRL */
    988. 

  988. #define CMU_LCDCTRL_VBFDIV_DIV2                    (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)      /**< Shifted mode DIV2 for CMU_LCDCTRL */
    989. 

  989. #define CMU_LCDCTRL_VBFDIV_DEFAULT                 (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)   /**< Shifted mode DEFAULT for CMU_LCDCTRL */
    990. 

  990. #define CMU_LCDCTRL_VBFDIV_DIV4                    (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)      /**< Shifted mode DIV4 for CMU_LCDCTRL */
    991. 

  991. #define CMU_LCDCTRL_VBFDIV_DIV8                    (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)      /**< Shifted mode DIV8 for CMU_LCDCTRL */
    992. 

  992. #define CMU_LCDCTRL_VBFDIV_DIV16                   (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)     /**< Shifted mode DIV16 for CMU_LCDCTRL */
    993. 

  993. #define CMU_LCDCTRL_VBFDIV_DIV32                   (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)     /**< Shifted mode DIV32 for CMU_LCDCTRL */
    994. 

  994. #define CMU_LCDCTRL_VBFDIV_DIV64                   (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)     /**< Shifted mode DIV64 for CMU_LCDCTRL */
    995. 

  995. #define CMU_LCDCTRL_VBFDIV_DIV128                  (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)    /**< Shifted mode DIV128 for CMU_LCDCTRL */
    996. 

  996. 

  997. /* Bit fields for CMU ROUTE */
    998. 

  998. #define _CMU_ROUTE_RESETVALUE                      0x00000000UL                         /**< Default value for CMU_ROUTE */
    999. 

  999. #define _CMU_ROUTE_MASK                            0x00000007UL                         /**< Mask for CMU_ROUTE */
    1000. 

  1000. #define CMU_ROUTE_CLKOUT0PEN                       (0x1UL << 0)                         /**< CLKOUT0 Pin Enable */
    1001. 

  1001. #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                0                                    /**< Shift value for CMU_CLKOUT0PEN */
    1002. 

  1002. #define _CMU_ROUTE_CLKOUT0PEN_MASK                 0x1UL                                /**< Bit mask for CMU_CLKOUT0PEN */
    1003. 

  1003. #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for CMU_ROUTE */
    1004. 

  1004. #define CMU_ROUTE_CLKOUT0PEN_DEFAULT               (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
    1005. 

  1005. #define CMU_ROUTE_CLKOUT1PEN                       (0x1UL << 1)                         /**< CLKOUT1 Pin Enable */
    1006. 

  1006. #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                1                                    /**< Shift value for CMU_CLKOUT1PEN */
    1007. 

  1007. #define _CMU_ROUTE_CLKOUT1PEN_MASK                 0x2UL                                /**< Bit mask for CMU_CLKOUT1PEN */
    1008. 

  1008. #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for CMU_ROUTE */
    1009. 

  1009. #define CMU_ROUTE_CLKOUT1PEN_DEFAULT               (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
    1010. 

  1010. #define CMU_ROUTE_LOCATION                         (0x1UL << 2)                         /**< I/O Location */
    1011. 

  1011. #define _CMU_ROUTE_LOCATION_SHIFT                  2                                    /**< Shift value for CMU_LOCATION */
    1012. 

  1012. #define _CMU_ROUTE_LOCATION_MASK                   0x4UL                                /**< Bit mask for CMU_LOCATION */
    1013. 

  1013. #define _CMU_ROUTE_LOCATION_DEFAULT                0x00000000UL                         /**< Mode DEFAULT for CMU_ROUTE */
    1014. 

  1014. #define _CMU_ROUTE_LOCATION_LOC0                   0x00000000UL                         /**< Mode LOC0 for CMU_ROUTE */
    1015. 

  1015. #define _CMU_ROUTE_LOCATION_LOC1                   0x00000001UL                         /**< Mode LOC1 for CMU_ROUTE */
    1016. 

  1016. #define CMU_ROUTE_LOCATION_DEFAULT                 (_CMU_ROUTE_LOCATION_DEFAULT << 2)   /**< Shifted mode DEFAULT for CMU_ROUTE */
    1017. 

  1017. #define CMU_ROUTE_LOCATION_LOC0                    (_CMU_ROUTE_LOCATION_LOC0 << 2)      /**< Shifted mode LOC0 for CMU_ROUTE */
    1018. 

  1018. #define CMU_ROUTE_LOCATION_LOC1                    (_CMU_ROUTE_LOCATION_LOC1 << 2)      /**< Shifted mode LOC1 for CMU_ROUTE */
    1019. 

  1019. 

  1020. /* Bit fields for CMU LOCK */
    1021. 

  1021. #define _CMU_LOCK_RESETVALUE                       0x00000000UL                      /**< Default value for CMU_LOCK */
    1022. 

  1022. #define _CMU_LOCK_MASK                             0x0000FFFFUL                      /**< Mask for CMU_LOCK */
    1023. 

  1023. #define _CMU_LOCK_LOCKKEY_SHIFT                    0                                 /**< Shift value for CMU_LOCKKEY */
    1024. 

  1024. #define _CMU_LOCK_LOCKKEY_MASK                     0xFFFFUL                          /**< Bit mask for CMU_LOCKKEY */
    1025. 

  1025. #define _CMU_LOCK_LOCKKEY_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for CMU_LOCK */
    1026. 

  1026. #define _CMU_LOCK_LOCKKEY_LOCK                     0x00000000UL                      /**< Mode LOCK for CMU_LOCK */
    1027. 

  1027. #define _CMU_LOCK_LOCKKEY_UNLOCKED                 0x00000000UL                      /**< Mode UNLOCKED for CMU_LOCK */
    1028. 

  1028. #define _CMU_LOCK_LOCKKEY_LOCKED                   0x00000001UL                      /**< Mode LOCKED for CMU_LOCK */
    1029. 

  1029. #define _CMU_LOCK_LOCKKEY_UNLOCK                   0x0000580EUL                      /**< Mode UNLOCK for CMU_LOCK */
    1030. 

  1030. #define CMU_LOCK_LOCKKEY_DEFAULT                   (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LOCK */
    1031. 

  1031. #define CMU_LOCK_LOCKKEY_LOCK                      (_CMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for CMU_LOCK */
    1032. 

  1032. #define CMU_LOCK_LOCKKEY_UNLOCKED                  (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
    1033. 

  1033. #define CMU_LOCK_LOCKKEY_LOCKED                    (_CMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for CMU_LOCK */
    1034. 

  1034. #define CMU_LOCK_LOCKKEY_UNLOCK                    (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
    1035. 

  1035. 

  1036. /** @} End of group EFM32G_CMU */
    1037. 

  1037. 

  1038.