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efm32g_devinfo.h

efm32g_devinfo.h 11 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file
    3. 

  3.  * @brief efm32g_devinfo Register and Bit Field definitions
    4. 

  4.  * @author Energy Micro AS
    5. 

  5.  * @version 3.0.0
    6. 

  6.  ******************************************************************************
    7. 

  7.  * @section License
    8. 

  8.  * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
    9. 

  9.  ******************************************************************************
    10. 

  10.  *
    11. 

  11.  * Permission is granted to anyone to use this software for any purpose,
    12. 

  12.  * including commercial applications, and to alter it and redistribute it
    13. 

  13.  * freely, subject to the following restrictions:
    14. 

  14.  *
    15. 

  15.  * 1. The origin of this software must not be misrepresented; you must not
    16. 

  16.  *    claim that you wrote the original software.
    17. 

  17.  * 2. Altered source versions must be plainly marked as such, and must not be
    18. 

  18.  *    misrepresented as being the original software.
    19. 

  19.  * 3. This notice may not be removed or altered from any source distribution.
    20. 

  20.  *
    21. 

  21.  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
    22. 

  22.  * obligation to support this Software. Energy Micro AS is providing the
    23. 

  23.  * Software "AS IS", with no express or implied warranties of any kind,
    24. 

  24.  * including, but not limited to, any implied warranties of merchantability
    25. 

  25.  * or fitness for any particular purpose or warranties against infringement
    26. 

  26.  * of any proprietary rights of a third party.
    27. 

  27.  *
    28. 

  28.  * Energy Micro AS will not be liable for any consequential, incidental, or
    29. 

  29.  * special damages, or any other relief, or for any claim by any third party,
    30. 

  30.  * arising from your use of this Software.
    31. 

  31.  *
    32. 

  32.  *****************************************************************************/
    33. 

  33. /**************************************************************************//**
    34. 

  34.  * @defgroup EFM32G_DEVINFO
    35. 

  35.  * @{
    36. 

  36.  *****************************************************************************/
    37. 

  37. typedef struct
    38. 

  38. {
    39. 

  39.   __I uint32_t CAL;          /**< Calibration temperature and checksum */
    40. 

  40.   __I uint32_t ADC0CAL0;     /**< ADC0 Calibration register 0 */
    41. 

  41.   __I uint32_t ADC0CAL1;     /**< ADC0 Calibration register 1 */
    42. 

  42.   __I uint32_t ADC0CAL2;     /**< ADC0 Calibration register 2 */
    43. 

  43.   uint32_t     RESERVED0[2]; /**< Reserved */
    44. 

  44.   __I uint32_t DAC0CAL0;     /**< DAC calibrartion register 0 */
    45. 

  45.   __I uint32_t DAC0CAL1;     /**< DAC calibrartion register 1 */
    46. 

  46.   __I uint32_t DAC0CAL2;     /**< DAC calibrartion register 2 */
    47. 

  47.   uint32_t     RESERVED1[2]; /**< Reserved */
    48. 

  48.   __I uint32_t HFRCOCAL0;    /**< HFRCO calibration register 0 */
    49. 

  49.   __I uint32_t HFRCOCAL1;    /**< HFRCO calibration register 1 */
    50. 

  50.   uint32_t     RESERVED2[3]; /**< Reserved */
    51. 

  51.   __I uint32_t UNIQUEL;      /**< Low 32 bits of device unique number */
    52. 

  52.   __I uint32_t UNIQUEH;      /**< High 32 bits of device unique number */
    53. 

  53.   __I uint32_t MSIZE;        /**< Flash and SRAM Memory size in KiloBytes */
    54. 

  54.   __I uint32_t PART;         /**< Part description */
    55. 

  55. } DEVINFO_TypeDef;           /** @} */
    56. 

  56. 

  57. /**************************************************************************//**
    58. 

  58.  * @defgroup EFM32G_DEVINFO_BitFields
    59. 

  59.  * @{
    60. 

  60.  *****************************************************************************/
    61. 

  61. /* Bit fields for EFM32G_DEVINFO */
    62. 

  62. #define _DEVINFO_CAL_CRC_MASK                      0x0000FFFFUL /**< Integrity CRC checksum mask */
    63. 

  63. #define _DEVINFO_CAL_CRC_SHIFT                     0            /**< Integrity CRC checksum shift */
    64. 

  64. #define _DEVINFO_CAL_TEMP_MASK                     0x00FF0000UL /**< Calibration temperature, DegC, mask */
    65. 

  65. #define _DEVINFO_CAL_TEMP_SHIFT                    16           /**< Calibration temperature shift */
    66. 

  66. #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK           0x00007F00UL /**< Gain for 1V25 reference, mask */
    67. 

  67. #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT          8            /**< Gain for 1V25 reference, shift */
    68. 

  68. #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK         0x0000007FUL /**< Offset for 1V25 reference, mask */
    69. 

  69. #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT        0            /**< Offset for 1V25 reference, shift */
    70. 

  70. #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK            0x7F000000UL /**< Gain for 2V5 reference, mask */
    71. 

  71. #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT           24           /**< Gain for 2V5 reference, shift */
    72. 

  72. #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK          0x007F0000UL /**< Offset for 2V5 reference, mask */
    73. 

  73. #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT         16           /**< Offset for 2V5 reference, shift */
    74. 

  74. #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK            0x00007F00UL /**< Gain for VDD reference, mask */
    75. 

  75. #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT           8            /**< Gain for VDD reference, shift */
    76. 

  76. #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK          0x0000007FUL /**< Offset for VDD reference, mask */
    77. 

  77. #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT         0            /**< Offset for VDD reference, shift */
    78. 

  78. #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK         0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
    79. 

  79. #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT        24           /**< Gain for 5VDIFF reference, mask */
    80. 

  80. #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK       0x007F0000UL /**< Offset for 5VDIFF reference, mask */
    81. 

  81. #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT      16           /**< Offset for 5VDIFF reference, shift */
    82. 

  82. #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK     0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
    83. 

  83. #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT    0            /**< Offset for 2XVDDVSS reference, shift */
    84. 

  84. #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK            0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
    85. 

  85. #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT           20           /**< Temperature reading at 1V25 reference, DegC */
    86. 

  86. #define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK           0x007F0000UL /**< Gain for 1V25 reference, mask */
    87. 

  87. #define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT          16           /**< Gain for 1V25 reference, shift */
    88. 

  88. #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK     0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
    89. 

  89. #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT    8            /**< Channel 1 offset for 1V25 reference, shift */
    90. 

  90. #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK     0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
    91. 

  91. #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT    0            /**< Channel 0 offset for 1V25 reference, shift */
    92. 

  92. #define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK            0x007F0000UL /**< Gain for 2V5 reference, mask */
    93. 

  93. #define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT           16           /**< Gain for 2V5 reference, shift */
    94. 

  94. #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK      0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
    95. 

  95. #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT     8            /**< Channel 1 offset for 2V5 reference, shift */
    96. 

  96. #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK      0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
    97. 

  97. #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT     0            /**< Channel 0 offset for 2V5 reference, shift */
    98. 

  98. #define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK            0x007F0000UL /**< Gain for VDD reference, mask */
    99. 

  99. #define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT           16           /**< Gain for VDD reference, shift */
    100. 

  100. #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK      0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
    101. 

  101. #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT     8            /**< Channel 1 offset for VDD reference, shift */
    102. 

  102. #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK      0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
    103. 

  103. #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT     0            /**< Channel 0 offset for VDD reference, shift*/
    104. 

  104. #define _DEVINFO_HFRCOCAL0_BAND1_MASK              0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
    105. 

  105. #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT             0            /**< 1MHz tuning value for HFRCO, shift */
    106. 

  106. #define _DEVINFO_HFRCOCAL0_BAND7_MASK              0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
    107. 

  107. #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT             8            /**< 7MHz tuning value for HFRCO, shift */
    108. 

  108. #define _DEVINFO_HFRCOCAL0_BAND11_MASK             0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
    109. 

  109. #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT            16           /**< 11MHz tuning value for HFRCO, shift */
    110. 

  110. #define _DEVINFO_HFRCOCAL0_BAND14_MASK             0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
    111. 

  111. #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT            24           /**< 14MHz tuning value for HFRCO, shift */
    112. 

  112. #define _DEVINFO_HFRCOCAL1_BAND21_MASK             0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
    113. 

  113. #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT            0            /**< 21MHz tuning value for HFRCO, shift */
    114. 

  114. #define _DEVINFO_HFRCOCAL1_BAND28_MASK             0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
    115. 

  115. #define _DEVINFO_HFRCOCAL1_BAND28_SHIFT            8            /**< 28MHz tuning value for HFRCO, mask */
    116. 

  116. #define _DEVINFO_UNIQUEL_MASK                      0xFFFFFFFFUL /**< Lower part of  64-bit device unique number */
    117. 

  117. #define _DEVINFO_UNIQUEL_SHIFT                     0            /**< Unique Low 32-bit shift */
    118. 

  118. #define _DEVINFO_UNIQUEH_MASK                      0xFFFFFFFFUL /**< High part of  64-bit device unique number */
    119. 

  119. #define _DEVINFO_UNIQUEH_SHIFT                     0            /**< Unique High 32-bit shift */
    120. 

  120. #define _DEVINFO_MSIZE_SRAM_MASK                   0xFFFF0000UL /**< Flash size in kilobytes */
    121. 

  121. #define _DEVINFO_MSIZE_SRAM_SHIFT                  16           /**< Bit position for flash size */
    122. 

  122. #define _DEVINFO_MSIZE_FLASH_MASK                  0x0000FFFFUL /**< SRAM size in kilobytes */
    123. 

  123. #define _DEVINFO_MSIZE_FLASH_SHIFT                 0            /**< Bit position for SRAM size */
    124. 

  124. #define _DEVINFO_PART_PROD_REV_MASK                0xFF000000UL /**< Production revision */
    125. 

  125. #define _DEVINFO_PART_PROD_REV_SHIFT               24           /**< Bit position for production revision */
    126. 

  126. #define _DEVINFO_PART_DEVICE_FAMILY_MASK           0x00FF0000UL /**< Device Family, 0x47 for Gecko */
    127. 

  127. #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT          16           /**< Bit position for device family */
    128. 

  128. #define _DEVINFO_PART_DEVICE_FAMILY_G              71           /**< Gecko Device Family */
    129. 

  129. #define _DEVINFO_PART_DEVICE_FAMILY_GG             72           /**< Giant Gecko Device Family */
    130. 

  130. #define _DEVINFO_PART_DEVICE_FAMILY_TG             73           /**< Tiny Gecko Device Family */
    131. 

  131. #define _DEVINFO_PART_DEVICE_FAMILY_LG             74           /**< Leopard Gecko Device Family */
    132. 

  132. #define _DEVINFO_PART_DEVICE_FAMILY_ZG             75           /**< Zero Gecko Device Family */
    133. 

  133. #define _DEVINFO_PART_DEVICE_NUMBER_MASK           0x0000FFFFUL /**< Device number */
    134. 

  134. #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT          0            /**< Bit position for device number */
    135. 

  135. 

  136. /** @} End of group EFM32G_DEVINFO */
    137. 

  137. 

  138.