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efm32gg_prs.h

efm32gg_prs.h 52 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file
    3. 

  3.  * @brief efm32gg_prs Register and Bit Field definitions
    4. 

  4.  * @author Energy Micro AS
    5. 

  5.  * @version 3.0.0
    6. 

  6.  ******************************************************************************
    7. 

  7.  * @section License
    8. 

  8.  * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
    9. 

  9.  ******************************************************************************
    10. 

  10.  *
    11. 

  11.  * Permission is granted to anyone to use this software for any purpose,
    12. 

  12.  * including commercial applications, and to alter it and redistribute it
    13. 

  13.  * freely, subject to the following restrictions:
    14. 

  14.  *
    15. 

  15.  * 1. The origin of this software must not be misrepresented; you must not
    16. 

  16.  *    claim that you wrote the original software.
    17. 

  17.  * 2. Altered source versions must be plainly marked as such, and must not be
    18. 

  18.  *    misrepresented as being the original software.
    19. 

  19.  * 3. This notice may not be removed or altered from any source distribution.
    20. 

  20.  *
    21. 

  21.  * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
    22. 

  22.  * obligation to support this Software. Energy Micro AS is providing the
    23. 

  23.  * Software "AS IS", with no express or implied warranties of any kind,
    24. 

  24.  * including, but not limited to, any implied warranties of merchantability
    25. 

  25.  * or fitness for any particular purpose or warranties against infringement
    26. 

  26.  * of any proprietary rights of a third party.
    27. 

  27.  *
    28. 

  28.  * Energy Micro AS will not be liable for any consequential, incidental, or
    29. 

  29.  * special damages, or any other relief, or for any claim by any third party,
    30. 

  30.  * arising from your use of this Software.
    31. 

  31.  *
    32. 

  32.  *****************************************************************************/
    33. 

  33. /**************************************************************************//**
    34. 

  34.  * @defgroup EFM32GG_PRS
    35. 

  35.  * @{
    36. 

  36.  * @brief EFM32GG_PRS Register Declaration
    37. 

  37.  *****************************************************************************/
    38. 

  38. typedef struct
    39. 

  39. {
    40. 

  40.   __IO uint32_t  SWPULSE;      /**< Software Pulse Register  */
    41. 

  41.   __IO uint32_t  SWLEVEL;      /**< Software Level Register  */
    42. 

  42.   __IO uint32_t  ROUTE;        /**< I/O Routing Register  */
    43. 

  43. 

  44.   uint32_t       RESERVED0[1]; /**< Reserved registers */
    45. 

  45. 

  46.   PRS_CH_TypeDef CH[12];       /**< Channel registers */
    47. 

  47. } PRS_TypeDef;                 /** @} */
    48. 

  48. 

  49. /**************************************************************************//**
    50. 

  50.  * @defgroup EFM32GG_PRS_BitFields
    51. 

  51.  * @{
    52. 

  52.  *****************************************************************************/
    53. 

  53. 

  54. /* Bit fields for PRS SWPULSE */
    55. 

  55. #define _PRS_SWPULSE_RESETVALUE                 0x00000000UL                           /**< Default value for PRS_SWPULSE */
    56. 

  56. #define _PRS_SWPULSE_MASK                       0x00000FFFUL                           /**< Mask for PRS_SWPULSE */
    57. 

  57. #define PRS_SWPULSE_CH0PULSE                    (0x1UL << 0)                           /**< Channel 0 Pulse Generation */
    58. 

  58. #define _PRS_SWPULSE_CH0PULSE_SHIFT             0                                      /**< Shift value for PRS_CH0PULSE */
    59. 

  59. #define _PRS_SWPULSE_CH0PULSE_MASK              0x1UL                                  /**< Bit mask for PRS_CH0PULSE */
    60. 

  60. #define _PRS_SWPULSE_CH0PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    61. 

  61. #define PRS_SWPULSE_CH0PULSE_DEFAULT            (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    62. 

  62. #define PRS_SWPULSE_CH1PULSE                    (0x1UL << 1)                           /**< Channel 1 Pulse Generation */
    63. 

  63. #define _PRS_SWPULSE_CH1PULSE_SHIFT             1                                      /**< Shift value for PRS_CH1PULSE */
    64. 

  64. #define _PRS_SWPULSE_CH1PULSE_MASK              0x2UL                                  /**< Bit mask for PRS_CH1PULSE */
    65. 

  65. #define _PRS_SWPULSE_CH1PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    66. 

  66. #define PRS_SWPULSE_CH1PULSE_DEFAULT            (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    67. 

  67. #define PRS_SWPULSE_CH2PULSE                    (0x1UL << 2)                           /**< Channel 2 Pulse Generation */
    68. 

  68. #define _PRS_SWPULSE_CH2PULSE_SHIFT             2                                      /**< Shift value for PRS_CH2PULSE */
    69. 

  69. #define _PRS_SWPULSE_CH2PULSE_MASK              0x4UL                                  /**< Bit mask for PRS_CH2PULSE */
    70. 

  70. #define _PRS_SWPULSE_CH2PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    71. 

  71. #define PRS_SWPULSE_CH2PULSE_DEFAULT            (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    72. 

  72. #define PRS_SWPULSE_CH3PULSE                    (0x1UL << 3)                           /**< Channel 3 Pulse Generation */
    73. 

  73. #define _PRS_SWPULSE_CH3PULSE_SHIFT             3                                      /**< Shift value for PRS_CH3PULSE */
    74. 

  74. #define _PRS_SWPULSE_CH3PULSE_MASK              0x8UL                                  /**< Bit mask for PRS_CH3PULSE */
    75. 

  75. #define _PRS_SWPULSE_CH3PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    76. 

  76. #define PRS_SWPULSE_CH3PULSE_DEFAULT            (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    77. 

  77. #define PRS_SWPULSE_CH4PULSE                    (0x1UL << 4)                           /**< Channel 4 Pulse Generation */
    78. 

  78. #define _PRS_SWPULSE_CH4PULSE_SHIFT             4                                      /**< Shift value for PRS_CH4PULSE */
    79. 

  79. #define _PRS_SWPULSE_CH4PULSE_MASK              0x10UL                                 /**< Bit mask for PRS_CH4PULSE */
    80. 

  80. #define _PRS_SWPULSE_CH4PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    81. 

  81. #define PRS_SWPULSE_CH4PULSE_DEFAULT            (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    82. 

  82. #define PRS_SWPULSE_CH5PULSE                    (0x1UL << 5)                           /**< Channel 5 Pulse Generation */
    83. 

  83. #define _PRS_SWPULSE_CH5PULSE_SHIFT             5                                      /**< Shift value for PRS_CH5PULSE */
    84. 

  84. #define _PRS_SWPULSE_CH5PULSE_MASK              0x20UL                                 /**< Bit mask for PRS_CH5PULSE */
    85. 

  85. #define _PRS_SWPULSE_CH5PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    86. 

  86. #define PRS_SWPULSE_CH5PULSE_DEFAULT            (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    87. 

  87. #define PRS_SWPULSE_CH6PULSE                    (0x1UL << 6)                           /**< Channel 6 Pulse Generation */
    88. 

  88. #define _PRS_SWPULSE_CH6PULSE_SHIFT             6                                      /**< Shift value for PRS_CH6PULSE */
    89. 

  89. #define _PRS_SWPULSE_CH6PULSE_MASK              0x40UL                                 /**< Bit mask for PRS_CH6PULSE */
    90. 

  90. #define _PRS_SWPULSE_CH6PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    91. 

  91. #define PRS_SWPULSE_CH6PULSE_DEFAULT            (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    92. 

  92. #define PRS_SWPULSE_CH7PULSE                    (0x1UL << 7)                           /**< Channel 7 Pulse Generation */
    93. 

  93. #define _PRS_SWPULSE_CH7PULSE_SHIFT             7                                      /**< Shift value for PRS_CH7PULSE */
    94. 

  94. #define _PRS_SWPULSE_CH7PULSE_MASK              0x80UL                                 /**< Bit mask for PRS_CH7PULSE */
    95. 

  95. #define _PRS_SWPULSE_CH7PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    96. 

  96. #define PRS_SWPULSE_CH7PULSE_DEFAULT            (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    97. 

  97. #define PRS_SWPULSE_CH8PULSE                    (0x1UL << 8)                           /**< Channel 8 Pulse Generation */
    98. 

  98. #define _PRS_SWPULSE_CH8PULSE_SHIFT             8                                      /**< Shift value for PRS_CH8PULSE */
    99. 

  99. #define _PRS_SWPULSE_CH8PULSE_MASK              0x100UL                                /**< Bit mask for PRS_CH8PULSE */
    100. 

  100. #define _PRS_SWPULSE_CH8PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    101. 

  101. #define PRS_SWPULSE_CH8PULSE_DEFAULT            (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    102. 

  102. #define PRS_SWPULSE_CH9PULSE                    (0x1UL << 9)                           /**< Channel 9 Pulse Generation */
    103. 

  103. #define _PRS_SWPULSE_CH9PULSE_SHIFT             9                                      /**< Shift value for PRS_CH9PULSE */
    104. 

  104. #define _PRS_SWPULSE_CH9PULSE_MASK              0x200UL                                /**< Bit mask for PRS_CH9PULSE */
    105. 

  105. #define _PRS_SWPULSE_CH9PULSE_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    106. 

  106. #define PRS_SWPULSE_CH9PULSE_DEFAULT            (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
    107. 

  107. #define PRS_SWPULSE_CH10PULSE                   (0x1UL << 10)                          /**< Channel 10 Pulse Generation */
    108. 

  108. #define _PRS_SWPULSE_CH10PULSE_SHIFT            10                                     /**< Shift value for PRS_CH10PULSE */
    109. 

  109. #define _PRS_SWPULSE_CH10PULSE_MASK             0x400UL                                /**< Bit mask for PRS_CH10PULSE */
    110. 

  110. #define _PRS_SWPULSE_CH10PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    111. 

  111. #define PRS_SWPULSE_CH10PULSE_DEFAULT           (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
    112. 

  112. #define PRS_SWPULSE_CH11PULSE                   (0x1UL << 11)                          /**< Channel 11 Pulse Generation */
    113. 

  113. #define _PRS_SWPULSE_CH11PULSE_SHIFT            11                                     /**< Shift value for PRS_CH11PULSE */
    114. 

  114. #define _PRS_SWPULSE_CH11PULSE_MASK             0x800UL                                /**< Bit mask for PRS_CH11PULSE */
    115. 

  115. #define _PRS_SWPULSE_CH11PULSE_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
    116. 

  116. #define PRS_SWPULSE_CH11PULSE_DEFAULT           (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
    117. 

  117. 

  118. /* Bit fields for PRS SWLEVEL */
    119. 

  119. #define _PRS_SWLEVEL_RESETVALUE                 0x00000000UL                           /**< Default value for PRS_SWLEVEL */
    120. 

  120. #define _PRS_SWLEVEL_MASK                       0x00000FFFUL                           /**< Mask for PRS_SWLEVEL */
    121. 

  121. #define PRS_SWLEVEL_CH0LEVEL                    (0x1UL << 0)                           /**< Channel 0 Software Level */
    122. 

  122. #define _PRS_SWLEVEL_CH0LEVEL_SHIFT             0                                      /**< Shift value for PRS_CH0LEVEL */
    123. 

  123. #define _PRS_SWLEVEL_CH0LEVEL_MASK              0x1UL                                  /**< Bit mask for PRS_CH0LEVEL */
    124. 

  124. #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    125. 

  125. #define PRS_SWLEVEL_CH0LEVEL_DEFAULT            (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    126. 

  126. #define PRS_SWLEVEL_CH1LEVEL                    (0x1UL << 1)                           /**< Channel 1 Software Level */
    127. 

  127. #define _PRS_SWLEVEL_CH1LEVEL_SHIFT             1                                      /**< Shift value for PRS_CH1LEVEL */
    128. 

  128. #define _PRS_SWLEVEL_CH1LEVEL_MASK              0x2UL                                  /**< Bit mask for PRS_CH1LEVEL */
    129. 

  129. #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    130. 

  130. #define PRS_SWLEVEL_CH1LEVEL_DEFAULT            (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    131. 

  131. #define PRS_SWLEVEL_CH2LEVEL                    (0x1UL << 2)                           /**< Channel 2 Software Level */
    132. 

  132. #define _PRS_SWLEVEL_CH2LEVEL_SHIFT             2                                      /**< Shift value for PRS_CH2LEVEL */
    133. 

  133. #define _PRS_SWLEVEL_CH2LEVEL_MASK              0x4UL                                  /**< Bit mask for PRS_CH2LEVEL */
    134. 

  134. #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    135. 

  135. #define PRS_SWLEVEL_CH2LEVEL_DEFAULT            (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    136. 

  136. #define PRS_SWLEVEL_CH3LEVEL                    (0x1UL << 3)                           /**< Channel 3 Software Level */
    137. 

  137. #define _PRS_SWLEVEL_CH3LEVEL_SHIFT             3                                      /**< Shift value for PRS_CH3LEVEL */
    138. 

  138. #define _PRS_SWLEVEL_CH3LEVEL_MASK              0x8UL                                  /**< Bit mask for PRS_CH3LEVEL */
    139. 

  139. #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    140. 

  140. #define PRS_SWLEVEL_CH3LEVEL_DEFAULT            (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    141. 

  141. #define PRS_SWLEVEL_CH4LEVEL                    (0x1UL << 4)                           /**< Channel 4 Software Level */
    142. 

  142. #define _PRS_SWLEVEL_CH4LEVEL_SHIFT             4                                      /**< Shift value for PRS_CH4LEVEL */
    143. 

  143. #define _PRS_SWLEVEL_CH4LEVEL_MASK              0x10UL                                 /**< Bit mask for PRS_CH4LEVEL */
    144. 

  144. #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    145. 

  145. #define PRS_SWLEVEL_CH4LEVEL_DEFAULT            (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    146. 

  146. #define PRS_SWLEVEL_CH5LEVEL                    (0x1UL << 5)                           /**< Channel 5 Software Level */
    147. 

  147. #define _PRS_SWLEVEL_CH5LEVEL_SHIFT             5                                      /**< Shift value for PRS_CH5LEVEL */
    148. 

  148. #define _PRS_SWLEVEL_CH5LEVEL_MASK              0x20UL                                 /**< Bit mask for PRS_CH5LEVEL */
    149. 

  149. #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    150. 

  150. #define PRS_SWLEVEL_CH5LEVEL_DEFAULT            (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    151. 

  151. #define PRS_SWLEVEL_CH6LEVEL                    (0x1UL << 6)                           /**< Channel 6 Software Level */
    152. 

  152. #define _PRS_SWLEVEL_CH6LEVEL_SHIFT             6                                      /**< Shift value for PRS_CH6LEVEL */
    153. 

  153. #define _PRS_SWLEVEL_CH6LEVEL_MASK              0x40UL                                 /**< Bit mask for PRS_CH6LEVEL */
    154. 

  154. #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    155. 

  155. #define PRS_SWLEVEL_CH6LEVEL_DEFAULT            (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    156. 

  156. #define PRS_SWLEVEL_CH7LEVEL                    (0x1UL << 7)                           /**< Channel 7 Software Level */
    157. 

  157. #define _PRS_SWLEVEL_CH7LEVEL_SHIFT             7                                      /**< Shift value for PRS_CH7LEVEL */
    158. 

  158. #define _PRS_SWLEVEL_CH7LEVEL_MASK              0x80UL                                 /**< Bit mask for PRS_CH7LEVEL */
    159. 

  159. #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    160. 

  160. #define PRS_SWLEVEL_CH7LEVEL_DEFAULT            (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    161. 

  161. #define PRS_SWLEVEL_CH8LEVEL                    (0x1UL << 8)                           /**< Channel 8 Software Level */
    162. 

  162. #define _PRS_SWLEVEL_CH8LEVEL_SHIFT             8                                      /**< Shift value for PRS_CH8LEVEL */
    163. 

  163. #define _PRS_SWLEVEL_CH8LEVEL_MASK              0x100UL                                /**< Bit mask for PRS_CH8LEVEL */
    164. 

  164. #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    165. 

  165. #define PRS_SWLEVEL_CH8LEVEL_DEFAULT            (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    166. 

  166. #define PRS_SWLEVEL_CH9LEVEL                    (0x1UL << 9)                           /**< Channel 9 Software Level */
    167. 

  167. #define _PRS_SWLEVEL_CH9LEVEL_SHIFT             9                                      /**< Shift value for PRS_CH9LEVEL */
    168. 

  168. #define _PRS_SWLEVEL_CH9LEVEL_MASK              0x200UL                                /**< Bit mask for PRS_CH9LEVEL */
    169. 

  169. #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT           0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    170. 

  170. #define PRS_SWLEVEL_CH9LEVEL_DEFAULT            (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    171. 

  171. #define PRS_SWLEVEL_CH10LEVEL                   (0x1UL << 10)                          /**< Channel 10 Software Level */
    172. 

  172. #define _PRS_SWLEVEL_CH10LEVEL_SHIFT            10                                     /**< Shift value for PRS_CH10LEVEL */
    173. 

  173. #define _PRS_SWLEVEL_CH10LEVEL_MASK             0x400UL                                /**< Bit mask for PRS_CH10LEVEL */
    174. 

  174. #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    175. 

  175. #define PRS_SWLEVEL_CH10LEVEL_DEFAULT           (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    176. 

  176. #define PRS_SWLEVEL_CH11LEVEL                   (0x1UL << 11)                          /**< Channel 11 Software Level */
    177. 

  177. #define _PRS_SWLEVEL_CH11LEVEL_SHIFT            11                                     /**< Shift value for PRS_CH11LEVEL */
    178. 

  178. #define _PRS_SWLEVEL_CH11LEVEL_MASK             0x800UL                                /**< Bit mask for PRS_CH11LEVEL */
    179. 

  179. #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
    180. 

  180. #define PRS_SWLEVEL_CH11LEVEL_DEFAULT           (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
    181. 

  181. 

  182. /* Bit fields for PRS ROUTE */
    183. 

  183. #define _PRS_ROUTE_RESETVALUE                   0x00000000UL                     /**< Default value for PRS_ROUTE */
    184. 

  184. #define _PRS_ROUTE_MASK                         0x0000070FUL                     /**< Mask for PRS_ROUTE */
    185. 

  185. #define PRS_ROUTE_CH0PEN                        (0x1UL << 0)                     /**< CH0 Pin Enable */
    186. 

  186. #define _PRS_ROUTE_CH0PEN_SHIFT                 0                                /**< Shift value for PRS_CH0PEN */
    187. 

  187. #define _PRS_ROUTE_CH0PEN_MASK                  0x1UL                            /**< Bit mask for PRS_CH0PEN */
    188. 

  188. #define _PRS_ROUTE_CH0PEN_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PRS_ROUTE */
    189. 

  189. #define PRS_ROUTE_CH0PEN_DEFAULT                (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
    190. 

  190. #define PRS_ROUTE_CH1PEN                        (0x1UL << 1)                     /**< CH1 Pin Enable */
    191. 

  191. #define _PRS_ROUTE_CH1PEN_SHIFT                 1                                /**< Shift value for PRS_CH1PEN */
    192. 

  192. #define _PRS_ROUTE_CH1PEN_MASK                  0x2UL                            /**< Bit mask for PRS_CH1PEN */
    193. 

  193. #define _PRS_ROUTE_CH1PEN_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PRS_ROUTE */
    194. 

  194. #define PRS_ROUTE_CH1PEN_DEFAULT                (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
    195. 

  195. #define PRS_ROUTE_CH2PEN                        (0x1UL << 2)                     /**< CH2 Pin Enable */
    196. 

  196. #define _PRS_ROUTE_CH2PEN_SHIFT                 2                                /**< Shift value for PRS_CH2PEN */
    197. 

  197. #define _PRS_ROUTE_CH2PEN_MASK                  0x4UL                            /**< Bit mask for PRS_CH2PEN */
    198. 

  198. #define _PRS_ROUTE_CH2PEN_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PRS_ROUTE */
    199. 

  199. #define PRS_ROUTE_CH2PEN_DEFAULT                (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
    200. 

  200. #define PRS_ROUTE_CH3PEN                        (0x1UL << 3)                     /**< CH3 Pin Enable */
    201. 

  201. #define _PRS_ROUTE_CH3PEN_SHIFT                 3                                /**< Shift value for PRS_CH3PEN */
    202. 

  202. #define _PRS_ROUTE_CH3PEN_MASK                  0x8UL                            /**< Bit mask for PRS_CH3PEN */
    203. 

  203. #define _PRS_ROUTE_CH3PEN_DEFAULT               0x00000000UL                     /**< Mode DEFAULT for PRS_ROUTE */
    204. 

  204. #define PRS_ROUTE_CH3PEN_DEFAULT                (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
    205. 

  205. #define _PRS_ROUTE_LOCATION_SHIFT               8                                /**< Shift value for PRS_LOCATION */
    206. 

  206. #define _PRS_ROUTE_LOCATION_MASK                0x700UL                          /**< Bit mask for PRS_LOCATION */
    207. 

  207. #define _PRS_ROUTE_LOCATION_LOC0                0x00000000UL                     /**< Mode LOC0 for PRS_ROUTE */
    208. 

  208. #define _PRS_ROUTE_LOCATION_LOC1                0x00000001UL                     /**< Mode LOC1 for PRS_ROUTE */
    209. 

  209. #define PRS_ROUTE_LOCATION_LOC0                 (_PRS_ROUTE_LOCATION_LOC0 << 8)  /**< Shifted mode LOC0 for PRS_ROUTE */
    210. 

  210. #define PRS_ROUTE_LOCATION_LOC1                 (_PRS_ROUTE_LOCATION_LOC1 << 8)  /**< Shifted mode LOC1 for PRS_ROUTE */
    211. 

  211. 

  212. /* Bit fields for PRS CH_CTRL */
    213. 

  213. #define _PRS_CH_CTRL_RESETVALUE                 0x00000000UL                                /**< Default value for PRS_CH_CTRL */
    214. 

  214. #define _PRS_CH_CTRL_MASK                       0x133F0007UL                                /**< Mask for PRS_CH_CTRL */
    215. 

  215. #define _PRS_CH_CTRL_SIGSEL_SHIFT               0                                           /**< Shift value for PRS_SIGSEL */
    216. 

  216. #define _PRS_CH_CTRL_SIGSEL_MASK                0x7UL                                       /**< Bit mask for PRS_SIGSEL */
    217. 

  217. #define _PRS_CH_CTRL_SIGSEL_VCMPOUT             0x00000000UL                                /**< Mode VCMPOUT for PRS_CH_CTRL */
    218. 

  218. #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT            0x00000000UL                                /**< Mode ACMP0OUT for PRS_CH_CTRL */
    219. 

  219. #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT            0x00000000UL                                /**< Mode ACMP1OUT for PRS_CH_CTRL */
    220. 

  220. #define _PRS_CH_CTRL_SIGSEL_DAC0CH0             0x00000000UL                                /**< Mode DAC0CH0 for PRS_CH_CTRL */
    221. 

  221. #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE          0x00000000UL                                /**< Mode ADC0SINGLE for PRS_CH_CTRL */
    222. 

  222. #define _PRS_CH_CTRL_SIGSEL_USART0IRTX          0x00000000UL                                /**< Mode USART0IRTX for PRS_CH_CTRL */
    223. 

  223. #define _PRS_CH_CTRL_SIGSEL_TIMER0UF            0x00000000UL                                /**< Mode TIMER0UF for PRS_CH_CTRL */
    224. 

  224. #define _PRS_CH_CTRL_SIGSEL_TIMER1UF            0x00000000UL                                /**< Mode TIMER1UF for PRS_CH_CTRL */
    225. 

  225. #define _PRS_CH_CTRL_SIGSEL_TIMER2UF            0x00000000UL                                /**< Mode TIMER2UF for PRS_CH_CTRL */
    226. 

  226. #define _PRS_CH_CTRL_SIGSEL_TIMER3UF            0x00000000UL                                /**< Mode TIMER3UF for PRS_CH_CTRL */
    227. 

  227. #define _PRS_CH_CTRL_SIGSEL_USBSOF              0x00000000UL                                /**< Mode USBSOF for PRS_CH_CTRL */
    228. 

  228. #define _PRS_CH_CTRL_SIGSEL_RTCOF               0x00000000UL                                /**< Mode RTCOF for PRS_CH_CTRL */
    229. 

  229. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0            0x00000000UL                                /**< Mode GPIOPIN0 for PRS_CH_CTRL */
    230. 

  230. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8            0x00000000UL                                /**< Mode GPIOPIN8 for PRS_CH_CTRL */
    231. 

  231. #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0         0x00000000UL                                /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
    232. 

  232. #define _PRS_CH_CTRL_SIGSEL_BURTCOF             0x00000000UL                                /**< Mode BURTCOF for PRS_CH_CTRL */
    233. 

  233. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0     0x00000000UL                                /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
    234. 

  234. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8     0x00000000UL                                /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
    235. 

  235. #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0         0x00000000UL                                /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
    236. 

  236. #define _PRS_CH_CTRL_SIGSEL_DAC0CH1             0x00000001UL                                /**< Mode DAC0CH1 for PRS_CH_CTRL */
    237. 

  237. #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN            0x00000001UL                                /**< Mode ADC0SCAN for PRS_CH_CTRL */
    238. 

  238. #define _PRS_CH_CTRL_SIGSEL_USART0TXC           0x00000001UL                                /**< Mode USART0TXC for PRS_CH_CTRL */
    239. 

  239. #define _PRS_CH_CTRL_SIGSEL_USART1TXC           0x00000001UL                                /**< Mode USART1TXC for PRS_CH_CTRL */
    240. 

  240. #define _PRS_CH_CTRL_SIGSEL_USART2TXC           0x00000001UL                                /**< Mode USART2TXC for PRS_CH_CTRL */
    241. 

  241. #define _PRS_CH_CTRL_SIGSEL_TIMER0OF            0x00000001UL                                /**< Mode TIMER0OF for PRS_CH_CTRL */
    242. 

  242. #define _PRS_CH_CTRL_SIGSEL_TIMER1OF            0x00000001UL                                /**< Mode TIMER1OF for PRS_CH_CTRL */
    243. 

  243. #define _PRS_CH_CTRL_SIGSEL_TIMER2OF            0x00000001UL                                /**< Mode TIMER2OF for PRS_CH_CTRL */
    244. 

  244. #define _PRS_CH_CTRL_SIGSEL_TIMER3OF            0x00000001UL                                /**< Mode TIMER3OF for PRS_CH_CTRL */
    245. 

  245. #define _PRS_CH_CTRL_SIGSEL_USBSOFSR            0x00000001UL                                /**< Mode USBSOFSR for PRS_CH_CTRL */
    246. 

  246. #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0            0x00000001UL                                /**< Mode RTCCOMP0 for PRS_CH_CTRL */
    247. 

  247. #define _PRS_CH_CTRL_SIGSEL_UART0TXC            0x00000001UL                                /**< Mode UART0TXC for PRS_CH_CTRL */
    248. 

  248. #define _PRS_CH_CTRL_SIGSEL_UART1TXC            0x00000001UL                                /**< Mode UART1TXC for PRS_CH_CTRL */
    249. 

  249. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1            0x00000001UL                                /**< Mode GPIOPIN1 for PRS_CH_CTRL */
    250. 

  250. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9            0x00000001UL                                /**< Mode GPIOPIN9 for PRS_CH_CTRL */
    251. 

  251. #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1         0x00000001UL                                /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
    252. 

  252. #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0          0x00000001UL                                /**< Mode BURTCCOMP0 for PRS_CH_CTRL */
    253. 

  253. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1     0x00000001UL                                /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
    254. 

  254. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9     0x00000001UL                                /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
    255. 

  255. #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1         0x00000001UL                                /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
    256. 

  256. #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV       0x00000002UL                                /**< Mode USART0RXDATAV for PRS_CH_CTRL */
    257. 

  257. #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV       0x00000002UL                                /**< Mode USART1RXDATAV for PRS_CH_CTRL */
    258. 

  258. #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV       0x00000002UL                                /**< Mode USART2RXDATAV for PRS_CH_CTRL */
    259. 

  259. #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0           0x00000002UL                                /**< Mode TIMER0CC0 for PRS_CH_CTRL */
    260. 

  260. #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0           0x00000002UL                                /**< Mode TIMER1CC0 for PRS_CH_CTRL */
    261. 

  261. #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0           0x00000002UL                                /**< Mode TIMER2CC0 for PRS_CH_CTRL */
    262. 

  262. #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0           0x00000002UL                                /**< Mode TIMER3CC0 for PRS_CH_CTRL */
    263. 

  263. #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1            0x00000002UL                                /**< Mode RTCCOMP1 for PRS_CH_CTRL */
    264. 

  264. #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV        0x00000002UL                                /**< Mode UART0RXDATAV for PRS_CH_CTRL */
    265. 

  265. #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV        0x00000002UL                                /**< Mode UART1RXDATAV for PRS_CH_CTRL */
    266. 

  266. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2            0x00000002UL                                /**< Mode GPIOPIN2 for PRS_CH_CTRL */
    267. 

  267. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10           0x00000002UL                                /**< Mode GPIOPIN10 for PRS_CH_CTRL */
    268. 

  268. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2     0x00000002UL                                /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
    269. 

  269. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10    0x00000002UL                                /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
    270. 

  270. #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2         0x00000002UL                                /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
    271. 

  271. #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1           0x00000003UL                                /**< Mode TIMER0CC1 for PRS_CH_CTRL */
    272. 

  272. #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1           0x00000003UL                                /**< Mode TIMER1CC1 for PRS_CH_CTRL */
    273. 

  273. #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1           0x00000003UL                                /**< Mode TIMER2CC1 for PRS_CH_CTRL */
    274. 

  274. #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1           0x00000003UL                                /**< Mode TIMER3CC1 for PRS_CH_CTRL */
    275. 

  275. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3            0x00000003UL                                /**< Mode GPIOPIN3 for PRS_CH_CTRL */
    276. 

  276. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11           0x00000003UL                                /**< Mode GPIOPIN11 for PRS_CH_CTRL */
    277. 

  277. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3     0x00000003UL                                /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
    278. 

  278. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11    0x00000003UL                                /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
    279. 

  279. #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2           0x00000004UL                                /**< Mode TIMER0CC2 for PRS_CH_CTRL */
    280. 

  280. #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2           0x00000004UL                                /**< Mode TIMER1CC2 for PRS_CH_CTRL */
    281. 

  281. #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2           0x00000004UL                                /**< Mode TIMER2CC2 for PRS_CH_CTRL */
    282. 

  282. #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2           0x00000004UL                                /**< Mode TIMER3CC2 for PRS_CH_CTRL */
    283. 

  283. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4            0x00000004UL                                /**< Mode GPIOPIN4 for PRS_CH_CTRL */
    284. 

  284. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12           0x00000004UL                                /**< Mode GPIOPIN12 for PRS_CH_CTRL */
    285. 

  285. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4     0x00000004UL                                /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
    286. 

  286. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12    0x00000004UL                                /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
    287. 

  287. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5            0x00000005UL                                /**< Mode GPIOPIN5 for PRS_CH_CTRL */
    288. 

  288. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13           0x00000005UL                                /**< Mode GPIOPIN13 for PRS_CH_CTRL */
    289. 

  289. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5     0x00000005UL                                /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
    290. 

  290. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13    0x00000005UL                                /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
    291. 

  291. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6            0x00000006UL                                /**< Mode GPIOPIN6 for PRS_CH_CTRL */
    292. 

  292. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14           0x00000006UL                                /**< Mode GPIOPIN14 for PRS_CH_CTRL */
    293. 

  293. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6     0x00000006UL                                /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
    294. 

  294. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14    0x00000006UL                                /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
    295. 

  295. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7            0x00000007UL                                /**< Mode GPIOPIN7 for PRS_CH_CTRL */
    296. 

  296. #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15           0x00000007UL                                /**< Mode GPIOPIN15 for PRS_CH_CTRL */
    297. 

  297. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7     0x00000007UL                                /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
    298. 

  298. #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15    0x00000007UL                                /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
    299. 

  299. #define PRS_CH_CTRL_SIGSEL_VCMPOUT              (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)          /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
    300. 

  300. #define PRS_CH_CTRL_SIGSEL_ACMP0OUT             (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)         /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
    301. 

  301. #define PRS_CH_CTRL_SIGSEL_ACMP1OUT             (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)         /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
    302. 

  302. #define PRS_CH_CTRL_SIGSEL_DAC0CH0              (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0)          /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */
    303. 

  303. #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE           (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)       /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
    304. 

  304. #define PRS_CH_CTRL_SIGSEL_USART0IRTX           (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)       /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
    305. 

  305. #define PRS_CH_CTRL_SIGSEL_TIMER0UF             (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)         /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
    306. 

  306. #define PRS_CH_CTRL_SIGSEL_TIMER1UF             (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)         /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
    307. 

  307. #define PRS_CH_CTRL_SIGSEL_TIMER2UF             (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)         /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
    308. 

  308. #define PRS_CH_CTRL_SIGSEL_TIMER3UF             (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0)         /**< Shifted mode TIMER3UF for PRS_CH_CTRL */
    309. 

  309. #define PRS_CH_CTRL_SIGSEL_USBSOF               (_PRS_CH_CTRL_SIGSEL_USBSOF << 0)           /**< Shifted mode USBSOF for PRS_CH_CTRL */
    310. 

  310. #define PRS_CH_CTRL_SIGSEL_RTCOF                (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)            /**< Shifted mode RTCOF for PRS_CH_CTRL */
    311. 

  311. #define PRS_CH_CTRL_SIGSEL_GPIOPIN0             (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)         /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
    312. 

  312. #define PRS_CH_CTRL_SIGSEL_GPIOPIN8             (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)         /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
    313. 

  313. #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0          (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)      /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
    314. 

  314. #define PRS_CH_CTRL_SIGSEL_BURTCOF              (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0)          /**< Shifted mode BURTCOF for PRS_CH_CTRL */
    315. 

  315. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0)  /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
    316. 

  316. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0)  /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
    317. 

  317. #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0)      /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
    318. 

  318. #define PRS_CH_CTRL_SIGSEL_DAC0CH1              (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0)          /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */
    319. 

  319. #define PRS_CH_CTRL_SIGSEL_ADC0SCAN             (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)         /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
    320. 

  320. #define PRS_CH_CTRL_SIGSEL_USART0TXC            (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)        /**< Shifted mode USART0TXC for PRS_CH_CTRL */
    321. 

  321. #define PRS_CH_CTRL_SIGSEL_USART1TXC            (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)        /**< Shifted mode USART1TXC for PRS_CH_CTRL */
    322. 

  322. #define PRS_CH_CTRL_SIGSEL_USART2TXC            (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0)        /**< Shifted mode USART2TXC for PRS_CH_CTRL */
    323. 

  323. #define PRS_CH_CTRL_SIGSEL_TIMER0OF             (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)         /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
    324. 

  324. #define PRS_CH_CTRL_SIGSEL_TIMER1OF             (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)         /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
    325. 

  325. #define PRS_CH_CTRL_SIGSEL_TIMER2OF             (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)         /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
    326. 

  326. #define PRS_CH_CTRL_SIGSEL_TIMER3OF             (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0)         /**< Shifted mode TIMER3OF for PRS_CH_CTRL */
    327. 

  327. #define PRS_CH_CTRL_SIGSEL_USBSOFSR             (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0)         /**< Shifted mode USBSOFSR for PRS_CH_CTRL */
    328. 

  328. #define PRS_CH_CTRL_SIGSEL_RTCCOMP0             (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)         /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
    329. 

  329. #define PRS_CH_CTRL_SIGSEL_UART0TXC             (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0)         /**< Shifted mode UART0TXC for PRS_CH_CTRL */
    330. 

  330. #define PRS_CH_CTRL_SIGSEL_UART1TXC             (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0)         /**< Shifted mode UART1TXC for PRS_CH_CTRL */
    331. 

  331. #define PRS_CH_CTRL_SIGSEL_GPIOPIN1             (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)         /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
    332. 

  332. #define PRS_CH_CTRL_SIGSEL_GPIOPIN9             (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)         /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
    333. 

  333. #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1          (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)      /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
    334. 

  334. #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0           (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0)       /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */
    335. 

  335. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0)  /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
    336. 

  336. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0)  /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
    337. 

  337. #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0)      /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
    338. 

  338. #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)    /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
    339. 

  339. #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)    /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
    340. 

  340. #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0)    /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
    341. 

  341. #define PRS_CH_CTRL_SIGSEL_TIMER0CC0            (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)        /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
    342. 

  342. #define PRS_CH_CTRL_SIGSEL_TIMER1CC0            (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)        /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
    343. 

  343. #define PRS_CH_CTRL_SIGSEL_TIMER2CC0            (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)        /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
    344. 

  344. #define PRS_CH_CTRL_SIGSEL_TIMER3CC0            (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0)        /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */
    345. 

  345. #define PRS_CH_CTRL_SIGSEL_RTCCOMP1             (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)         /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
    346. 

  346. #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV         (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0)     /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */
    347. 

  347. #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV         (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0)     /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */
    348. 

  348. #define PRS_CH_CTRL_SIGSEL_GPIOPIN2             (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)         /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
    349. 

  349. #define PRS_CH_CTRL_SIGSEL_GPIOPIN10            (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)        /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
    350. 

  350. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0)  /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
    351. 

  351. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
    352. 

  352. #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0)      /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
    353. 

  353. #define PRS_CH_CTRL_SIGSEL_TIMER0CC1            (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)        /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
    354. 

  354. #define PRS_CH_CTRL_SIGSEL_TIMER1CC1            (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)        /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
    355. 

  355. #define PRS_CH_CTRL_SIGSEL_TIMER2CC1            (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)        /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
    356. 

  356. #define PRS_CH_CTRL_SIGSEL_TIMER3CC1            (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0)        /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */
    357. 

  357. #define PRS_CH_CTRL_SIGSEL_GPIOPIN3             (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)         /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
    358. 

  358. #define PRS_CH_CTRL_SIGSEL_GPIOPIN11            (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)        /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
    359. 

  359. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0)  /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
    360. 

  360. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
    361. 

  361. #define PRS_CH_CTRL_SIGSEL_TIMER0CC2            (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)        /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
    362. 

  362. #define PRS_CH_CTRL_SIGSEL_TIMER1CC2            (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)        /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
    363. 

  363. #define PRS_CH_CTRL_SIGSEL_TIMER2CC2            (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)        /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
    364. 

  364. #define PRS_CH_CTRL_SIGSEL_TIMER3CC2            (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0)        /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */
    365. 

  365. #define PRS_CH_CTRL_SIGSEL_GPIOPIN4             (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)         /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
    366. 

  366. #define PRS_CH_CTRL_SIGSEL_GPIOPIN12            (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)        /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
    367. 

  367. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0)  /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
    368. 

  368. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
    369. 

  369. #define PRS_CH_CTRL_SIGSEL_GPIOPIN5             (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)         /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
    370. 

  370. #define PRS_CH_CTRL_SIGSEL_GPIOPIN13            (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)        /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
    371. 

  371. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0)  /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
    372. 

  372. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
    373. 

  373. #define PRS_CH_CTRL_SIGSEL_GPIOPIN6             (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)         /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
    374. 

  374. #define PRS_CH_CTRL_SIGSEL_GPIOPIN14            (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)        /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
    375. 

  375. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0)  /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
    376. 

  376. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
    377. 

  377. #define PRS_CH_CTRL_SIGSEL_GPIOPIN7             (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)         /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
    378. 

  378. #define PRS_CH_CTRL_SIGSEL_GPIOPIN15            (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)        /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
    379. 

  379. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0)  /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
    380. 

  380. #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
    381. 

  381. #define _PRS_CH_CTRL_SOURCESEL_SHIFT            16                                          /**< Shift value for PRS_SOURCESEL */
    382. 

  382. #define _PRS_CH_CTRL_SOURCESEL_MASK             0x3F0000UL                                  /**< Bit mask for PRS_SOURCESEL */
    383. 

  383. #define _PRS_CH_CTRL_SOURCESEL_NONE             0x00000000UL                                /**< Mode NONE for PRS_CH_CTRL */
    384. 

  384. #define _PRS_CH_CTRL_SOURCESEL_VCMP             0x00000001UL                                /**< Mode VCMP for PRS_CH_CTRL */
    385. 

  385. #define _PRS_CH_CTRL_SOURCESEL_ACMP0            0x00000002UL                                /**< Mode ACMP0 for PRS_CH_CTRL */
    386. 

  386. #define _PRS_CH_CTRL_SOURCESEL_ACMP1            0x00000003UL                                /**< Mode ACMP1 for PRS_CH_CTRL */
    387. 

  387. #define _PRS_CH_CTRL_SOURCESEL_DAC0             0x00000006UL                                /**< Mode DAC0 for PRS_CH_CTRL */
    388. 

  388. #define _PRS_CH_CTRL_SOURCESEL_ADC0             0x00000008UL                                /**< Mode ADC0 for PRS_CH_CTRL */
    389. 

  389. #define _PRS_CH_CTRL_SOURCESEL_USART0           0x00000010UL                                /**< Mode USART0 for PRS_CH_CTRL */
    390. 

  390. #define _PRS_CH_CTRL_SOURCESEL_USART1           0x00000011UL                                /**< Mode USART1 for PRS_CH_CTRL */
    391. 

  391. #define _PRS_CH_CTRL_SOURCESEL_USART2           0x00000012UL                                /**< Mode USART2 for PRS_CH_CTRL */
    392. 

  392. #define _PRS_CH_CTRL_SOURCESEL_TIMER0           0x0000001CUL                                /**< Mode TIMER0 for PRS_CH_CTRL */
    393. 

  393. #define _PRS_CH_CTRL_SOURCESEL_TIMER1           0x0000001DUL                                /**< Mode TIMER1 for PRS_CH_CTRL */
    394. 

  394. #define _PRS_CH_CTRL_SOURCESEL_TIMER2           0x0000001EUL                                /**< Mode TIMER2 for PRS_CH_CTRL */
    395. 

  395. #define _PRS_CH_CTRL_SOURCESEL_TIMER3           0x0000001FUL                                /**< Mode TIMER3 for PRS_CH_CTRL */
    396. 

  396. #define _PRS_CH_CTRL_SOURCESEL_USB              0x00000024UL                                /**< Mode USB for PRS_CH_CTRL */
    397. 

  397. #define _PRS_CH_CTRL_SOURCESEL_RTC              0x00000028UL                                /**< Mode RTC for PRS_CH_CTRL */
    398. 

  398. #define _PRS_CH_CTRL_SOURCESEL_UART0            0x00000029UL                                /**< Mode UART0 for PRS_CH_CTRL */
    399. 

  399. #define _PRS_CH_CTRL_SOURCESEL_UART1            0x0000002AUL                                /**< Mode UART1 for PRS_CH_CTRL */
    400. 

  400. #define _PRS_CH_CTRL_SOURCESEL_GPIOL            0x00000030UL                                /**< Mode GPIOL for PRS_CH_CTRL */
    401. 

  401. #define _PRS_CH_CTRL_SOURCESEL_GPIOH            0x00000031UL                                /**< Mode GPIOH for PRS_CH_CTRL */
    402. 

  402. #define _PRS_CH_CTRL_SOURCESEL_LETIMER0         0x00000034UL                                /**< Mode LETIMER0 for PRS_CH_CTRL */
    403. 

  403. #define _PRS_CH_CTRL_SOURCESEL_BURTC            0x00000037UL                                /**< Mode BURTC for PRS_CH_CTRL */
    404. 

  404. #define _PRS_CH_CTRL_SOURCESEL_LESENSEL         0x00000039UL                                /**< Mode LESENSEL for PRS_CH_CTRL */
    405. 

  405. #define _PRS_CH_CTRL_SOURCESEL_LESENSEH         0x0000003AUL                                /**< Mode LESENSEH for PRS_CH_CTRL */
    406. 

  406. #define _PRS_CH_CTRL_SOURCESEL_LESENSED         0x0000003BUL                                /**< Mode LESENSED for PRS_CH_CTRL */
    407. 

  407. #define PRS_CH_CTRL_SOURCESEL_NONE              (_PRS_CH_CTRL_SOURCESEL_NONE << 16)         /**< Shifted mode NONE for PRS_CH_CTRL */
    408. 

  408. #define PRS_CH_CTRL_SOURCESEL_VCMP              (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)         /**< Shifted mode VCMP for PRS_CH_CTRL */
    409. 

  409. #define PRS_CH_CTRL_SOURCESEL_ACMP0             (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)        /**< Shifted mode ACMP0 for PRS_CH_CTRL */
    410. 

  410. #define PRS_CH_CTRL_SOURCESEL_ACMP1             (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)        /**< Shifted mode ACMP1 for PRS_CH_CTRL */
    411. 

  411. #define PRS_CH_CTRL_SOURCESEL_DAC0              (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16)         /**< Shifted mode DAC0 for PRS_CH_CTRL */
    412. 

  412. #define PRS_CH_CTRL_SOURCESEL_ADC0              (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)         /**< Shifted mode ADC0 for PRS_CH_CTRL */
    413. 

  413. #define PRS_CH_CTRL_SOURCESEL_USART0            (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)       /**< Shifted mode USART0 for PRS_CH_CTRL */
    414. 

  414. #define PRS_CH_CTRL_SOURCESEL_USART1            (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)       /**< Shifted mode USART1 for PRS_CH_CTRL */
    415. 

  415. #define PRS_CH_CTRL_SOURCESEL_USART2            (_PRS_CH_CTRL_SOURCESEL_USART2 << 16)       /**< Shifted mode USART2 for PRS_CH_CTRL */
    416. 

  416. #define PRS_CH_CTRL_SOURCESEL_TIMER0            (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)       /**< Shifted mode TIMER0 for PRS_CH_CTRL */
    417. 

  417. #define PRS_CH_CTRL_SOURCESEL_TIMER1            (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)       /**< Shifted mode TIMER1 for PRS_CH_CTRL */
    418. 

  418. #define PRS_CH_CTRL_SOURCESEL_TIMER2            (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)       /**< Shifted mode TIMER2 for PRS_CH_CTRL */
    419. 

  419. #define PRS_CH_CTRL_SOURCESEL_TIMER3            (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16)       /**< Shifted mode TIMER3 for PRS_CH_CTRL */
    420. 

  420. #define PRS_CH_CTRL_SOURCESEL_USB               (_PRS_CH_CTRL_SOURCESEL_USB << 16)          /**< Shifted mode USB for PRS_CH_CTRL */
    421. 

  421. #define PRS_CH_CTRL_SOURCESEL_RTC               (_PRS_CH_CTRL_SOURCESEL_RTC << 16)          /**< Shifted mode RTC for PRS_CH_CTRL */
    422. 

  422. #define PRS_CH_CTRL_SOURCESEL_UART0             (_PRS_CH_CTRL_SOURCESEL_UART0 << 16)        /**< Shifted mode UART0 for PRS_CH_CTRL */
    423. 

  423. #define PRS_CH_CTRL_SOURCESEL_UART1             (_PRS_CH_CTRL_SOURCESEL_UART1 << 16)        /**< Shifted mode UART1 for PRS_CH_CTRL */
    424. 

  424. #define PRS_CH_CTRL_SOURCESEL_GPIOL             (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)        /**< Shifted mode GPIOL for PRS_CH_CTRL */
    425. 

  425. #define PRS_CH_CTRL_SOURCESEL_GPIOH             (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)        /**< Shifted mode GPIOH for PRS_CH_CTRL */
    426. 

  426. #define PRS_CH_CTRL_SOURCESEL_LETIMER0          (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16)     /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
    427. 

  427. #define PRS_CH_CTRL_SOURCESEL_BURTC             (_PRS_CH_CTRL_SOURCESEL_BURTC << 16)        /**< Shifted mode BURTC for PRS_CH_CTRL */
    428. 

  428. #define PRS_CH_CTRL_SOURCESEL_LESENSEL          (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16)     /**< Shifted mode LESENSEL for PRS_CH_CTRL */
    429. 

  429. #define PRS_CH_CTRL_SOURCESEL_LESENSEH          (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16)     /**< Shifted mode LESENSEH for PRS_CH_CTRL */
    430. 

  430. #define PRS_CH_CTRL_SOURCESEL_LESENSED          (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16)     /**< Shifted mode LESENSED for PRS_CH_CTRL */
    431. 

  431. #define _PRS_CH_CTRL_EDSEL_SHIFT                24                                          /**< Shift value for PRS_EDSEL */
    432. 

  432. #define _PRS_CH_CTRL_EDSEL_MASK                 0x3000000UL                                 /**< Bit mask for PRS_EDSEL */
    433. 

  433. #define _PRS_CH_CTRL_EDSEL_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for PRS_CH_CTRL */
    434. 

  434. #define _PRS_CH_CTRL_EDSEL_OFF                  0x00000000UL                                /**< Mode OFF for PRS_CH_CTRL */
    435. 

  435. #define _PRS_CH_CTRL_EDSEL_POSEDGE              0x00000001UL                                /**< Mode POSEDGE for PRS_CH_CTRL */
    436. 

  436. #define _PRS_CH_CTRL_EDSEL_NEGEDGE              0x00000002UL                                /**< Mode NEGEDGE for PRS_CH_CTRL */
    437. 

  437. #define _PRS_CH_CTRL_EDSEL_BOTHEDGES            0x00000003UL                                /**< Mode BOTHEDGES for PRS_CH_CTRL */
    438. 

  438. #define PRS_CH_CTRL_EDSEL_DEFAULT               (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)          /**< Shifted mode DEFAULT for PRS_CH_CTRL */
    439. 

  439. #define PRS_CH_CTRL_EDSEL_OFF                   (_PRS_CH_CTRL_EDSEL_OFF << 24)              /**< Shifted mode OFF for PRS_CH_CTRL */
    440. 

  440. #define PRS_CH_CTRL_EDSEL_POSEDGE               (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)          /**< Shifted mode POSEDGE for PRS_CH_CTRL */
    441. 

  441. #define PRS_CH_CTRL_EDSEL_NEGEDGE               (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)          /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
    442. 

  442. #define PRS_CH_CTRL_EDSEL_BOTHEDGES             (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)        /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
    443. 

  443. #define PRS_CH_CTRL_ASYNC                       (0x1UL << 28)                               /**< Asynchronous reflex */
    444. 

  444. #define _PRS_CH_CTRL_ASYNC_SHIFT                28                                          /**< Shift value for PRS_ASYNC */
    445. 

  445. #define _PRS_CH_CTRL_ASYNC_MASK                 0x10000000UL                                /**< Bit mask for PRS_ASYNC */
    446. 

  446. #define _PRS_CH_CTRL_ASYNC_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for PRS_CH_CTRL */
    447. 

  447. #define PRS_CH_CTRL_ASYNC_DEFAULT               (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)          /**< Shifted mode DEFAULT for PRS_CH_CTRL */
    448. 

  448. 

  449. /** @} End of group EFM32GG_PRS */
    450. 

  450. 

  451.