CMSIS_System_View_Description.htm 65 KB

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  29. <h1 class="style1">Cortex Microcontroller Software Interface Standard<br>
  30. System View Description</h1>
  31. <p class="style1">This file describes the Cortex Microcontroller Software
  32. Interface Standard - System View Description (CMSIS - SVD) concept and syntax.</p>
  33. <p class="style1">Version: 1.02 - 27. July 2011</p>
  34. <p class="style1">Information in this file, the accompany manuals, and software is<br>
  35. Copyright © ARM Ltd.<br>All rights reserved.
  36. </p>
  37. <hr>
  38. <p><span style="FONT-WEIGHT: bold">Revision History</span></p>
  39. <ul>
  40. <li>Version 0.91: initial proposal.</li>
  41. <li>Version 0.92: revised proposal considering forum feedback (e.g. consider
  42. IP-XACT constructs and naming scheme)</li>
  43. <li>Version 1.0: new elements: peripheral version, vendor specific
  44. extension section, interrupt mapping information, global peripheral disable
  45. condition, naming of register arrays, enhanced naming schemes, etc.</li>
  46. <li>Version 1.0: SVD versioning and updated schema file</li>
  47. <li>Version 1.01: Error corrections in the example code. "include" has been removed. Restricted to one device per file.</li>
  48. <li>Version 1.02: Adding the use case of device header file generation.</li>
  49. </ul>
  50. <p>&nbsp;</p>
  51. <hr>
  52. <h2>Contents</h2>
  53. <ol>
  54. <li class="LI2"><a href="#1">About</a></li>
  55. <li class="LI2"><a href="#2">Motivation</a></li>
  56. <li class="LI2"><a href="#3">Requirements</a></li>
  57. <li class="LI2"><a href="#4">Format</a></li>
  58. <li class="LI2"><a href="#5">Example</a></li>
  59. <li class="LI2"><a href="#6">Questions &amp; Answers</a></li>
  60. </ol>
  61. <h2><a name="1"></a>About</h2>
  62. <p>
  63. The <strong>Cortex Microcontroller Software Interface Standard - System View
  64. Description</strong> (CMSIS - SVD) answers the challenges
  65. of accurate, detailed and timely device aware peripheral debugging support for Cortex
  66. Microcontroller based devices by the software development
  67. tools vendor community.
  68. </p>
  69. <p>
  70. Silicon vendors shall create and maintain a formalized description of the
  71. debug view for all the peripherals contained in their Cortex
  72. Microcontroller based devices. Tool vendors use such descriptions to
  73. establish device specific debug support in their debugging tools with minimal turn around times and
  74. manageable effort. Device support across many development tools&nbsp; is
  75. essential for silicon provider in order to promote new devices and device
  76. variants entering the market. Device aware debug views provide fast and
  77. convenient access to all registers and fields as well as a detailed
  78. description. This enables software developer to
  79. develop and debug code most efficiently and adopt new devices early and
  80. quickly.</p>
  81. <p>
  82. A standardized System View Description shall provide a common approach to
  83. capturing peripheral debug related information in a machine readable files.
  84. The scope of the contained information is agreed to match the level usually
  85. provided by silicon vendors in their device reference manuals, however in a
  86. formalized XML based format. There
  87. are other description languages already available. IP-XACT from the SPIRIT
  88. consortium is a prominent example. IP-XACT covers the register description
  89. sufficiently, however it comprises many other aspects of the devices like
  90. ports, bus-protocols, modeling, tool flows, etc. making a direct use of
  91. IP-XACT too complex. The design of the SVD language is
  92. taking some guidance from IP-XACT thus allowing straight forward conversion
  93. from IP-XACT to CMSIS-SVD where IP-XACT device information is already
  94. available.</p>
  95. <p>
  96. In a second step the CMSIS-SVD description shall be used for automatically
  97. generating CMSIS compliant a device header file. This enables the
  98. information in the header file to be consistent with what the debugger will
  99. display and CMSIS compliant by construction. The header file generation will
  100. require some additional pieces of information and therefore a future version
  101. of the description will need to include some extensions for this purpose.</p>
  102. <p>
  103. Device aware debugging support is only one aspect of device
  104. support essential to software development environments, however it is one of
  105. the most time consuming and error prone ones.</p>
  106. <h2><a name="2"></a>Motivation</h2>
  107. <p>
  108. The software developer of microcontroller devices is faced with a growing number
  109. of devices with an ever increasing number of peripheral blocks providing a wide
  110. range of distinct and complex functionality. The development of drivers for
  111. these peripherals is in the critical path of every project. Modern debuggers are supporting the software developer in getting the
  112. software to run according to the requirements. A debugger providing peripheral awareness improves the
  113. ability to access and interpret complex configuration and status information of
  114. peripherals. Even though this is only one aspect of device support within microcontroller
  115. development environments it is essential for the successful and timely adoption
  116. of development tools and the device by the market.</p>
  117. <p>Today software development environments address device aware
  118. debugging in various ways. They either use documents or proprietary file formats
  119. as input for providing peripheral views in the debuggers.
  120. Extracting peripheral information from written documentation is a very time
  121. consuming, tedious and error prone task. Having a file containing peripheral specific information to generate peripheral views
  122. is going to make device support more affordable, reliable and timely.
  123. The challenge for the tool providers is the support of many
  124. different and incompatible file formats from a growing number of silicon vendors.
  125. For silicon vendors it is time consuming and costly to engage with many tool
  126. provider in order to achieve device support in a wide range of development
  127. environments.</p>
  128. <p>Standardizing on a System View Description aims to ease this challenge
  129. by agreeing on a formal XML-based file format. In conjunction with supporting web server infrastructure silicon partner
  130. shall upload and maintain such descriptions in a tool vendor agnostic device
  131. database, hosted e.g. by the web server infrastructure
  132. <a href="http://cmsis.arm.com">
  133. cmsis.arm.com</a> . Access control to sensitive information is managed on a per user
  134. basis. This allows silicon vendors to upload information for devices that have
  135. not been made public.&nbsp; </p>
  136. <p>Such an approach provides benefits for silicon and tool vendors as well as
  137. software developers of Cortex-M based microcontroller devices</p>
  138. <ul>
  139. <li>timely and accurate device support provided by a whole range of tool providers </li>
  140. <li>tool providers become more efficient in supporting a multitude of devices
  141. and device variants</li>
  142. <li>less interaction required between silicon vendors and the
  143. tool providers</li>
  144. <li>silicon provider has control over and maintains the System View
  145. Description during the life cycle of the device</li>
  146. <li>high quality device support in terms of completeness and correctness of
  147. device aware debugging</li>
  148. <li>improved productivity and user experience for the software developer</li>
  149. </ul>
  150. <h2><a name="3"></a>Requirements</h2>
  151. <p>The debug description shall capture the information about all
  152. the peripherals contained in a specific device. This section describes which
  153. items of information are deemed relevant for a debugger. Silicon vendors are expected to
  154. provide the System View Description for their devices, matching the information
  155. contained in device reference manuals. The System View Description shall be suitable for straight forward
  156. generation from existing databases like IP-XACT descriptions or SIDSC. The size
  157. of device description is a concern and therefore redundancy in the description
  158. shall be avoided. The size of SVD files affects the efficiency of
  159. distribution as well as the loading time by the development tools. Last but not least manual editing of SVD files shall be possible for
  160. the purpose of customization by SW developers.</p>
  161. <h4>Required content of the description</h4>
  162. <p>From a programmer's perspective a peripheral can be seen as a set of registers
  163. with unique<em> names</em> being mapped to fixed<em> addresses</em> allocated
  164. within a defined <em>range</em> of an address space.</p>
  165. <p>From a debugger's point of view read accesses to a physical register need to be
  166. executed in order to display its current value. The debugger executes a write
  167. access to a register when a user edits its value. For this purpose the debugger
  168. needs to know about the following additional attributes: </p>
  169. <ul>
  170. <li><em>minimal addressable unit </em>= smallest series of bits
  171. identified by a unique address (e.g. byte-addressable memory) </li>
  172. <li><em>register size</em> = number of bits forming a register (ARM Cortex-M usually
  173. 32 bits)</li>
  174. <li><em>access permission</em> = read and write, read only,
  175. write only</li>
  176. <li><em>access side effects</em> = accesses by the debugger must
  177. be avoided if it has side effects. Some side effects may be
  178. reversed by the debugger to compensate for the side effect</li>
  179. </ul>
  180. <p>In many cases peripheral registers are partitioned into chunks of bits of
  181. distinct functionality. In this document these chunks are referred to as <em>
  182. field</em>. Each
  183. register that consists of fields shall&nbsp; be described by a list
  184. of <em>uniquely named</em> fields (Note: field names are not required to be
  185. unique across registers). In order for a debugger to extract the
  186. value of a field from the corresponding register the following attributes are required:</p>
  187. <ul>
  188. <li><em>most significant bit </em>= highest bit position of the
  189. bit-field in the corresponding register</li>
  190. <li><em>least significant bit</em> = lowest bit position of the
  191. bit-field within the corresponding register</li>
  192. <li><em>access permission</em> = read and write, read only,
  193. write only</li>
  194. </ul>
  195. <p>An enumerated value maps a number to a specific descriptive string
  196. representing the semantics of the value of a field. The debugger displays the
  197. descriptive string rather than the number to simplify the access to the
  198. information thus
  199. avoiding the necessity of a look-up in the device reference manual. Each item of
  200. an enumerated value has the following attributes:</p>
  201. <ul>
  202. <li><em>value</em> = value of the bit-field that corresponds to
  203. the string attribute</li>
  204. <li><em>name</em> = short string that describes the semantics of a
  205. field when the corresponding value is set</li>
  206. <li><em>description</em> = detailed description of the semantics
  207. of the field when the corresponding value is set</li>
  208. </ul>
  209. <p>The hierarchical structure of the description looks like this:</p>
  210. <p><strong>Device =</strong></p>
  211. <ul>
  212. <li>
  213. <p>&nbsp;<strong>Peripherals</strong></p>
  214. <ul>
  215. <li>
  216. <p class="style2"><strong>Peripheral</strong></p>
  217. <ul>
  218. <li>
  219. <p class="style2"><strong>Registers</strong></p>
  220. <ul>
  221. <li>
  222. <p class="style2">
  223. <strong>Register</strong></p>
  224. <ul>
  225. <li>
  226. <p class="style2">
  227. <strong>Fields</strong></p>
  228. <ul>
  229. <li>
  230. <p class="style2"><strong>Field</strong></p>
  231. <ul>
  232. <li>
  233. <p class="style2"><strong>Enumerated Values</strong></p>
  234. <ul>
  235. <li>
  236. <p class="style2"><strong>Enumerated Value</strong></p>
  237. </li>
  238. </ul>
  239. </li>
  240. </ul>
  241. </li>
  242. </ul>
  243. </li>
  244. </ul>
  245. </li>
  246. </ul>
  247. </li>
  248. </ul>
  249. </li>
  250. </ul>
  251. </li>
  252. </ul>
  253. <p>One file can only contain a description for a single device or device family
  254. sharing the identical description. Devices consists of a one or more peripherals.
  255. Each peripheral contains
  256. one or more registers, where each register may consist of one or more fields.
  257. The values of a field maybe represented through descriptive strings and detailed
  258. descriptions, the enumerated values.</p>
  259. <p>In many cases there are multiple
  260. instances of the same peripheral in a device (e.g. Timer0, Timer1, etc.). For
  261. this reason the description has the concept of deriving a peripheral from a peripheral
  262. that has already been described. The attribute <em>derivedFrom </em>specifies
  263. such a relationship.
  264. Similarly registers or fields can be reused within the device description. The
  265. grouping of&nbsp; peripherals providing
  266. similar functionality (e.g. Simple Timer, Complex Timer) is controlled via the element <em>groupName</em>.
  267. All peripherals associated with the same group name are collectively listed under this group
  268. in the order they have been specified in the file.
  269. Collecting&nbsp;
  270. similar or related peripherals into peripheral groups helps structuring the list
  271. of peripherals e.g. in a drop down menu (tool dependent). Devices with a large
  272. set of peripherals will benefit from this additional level of structure.</p>
  273. <p>Each of the items (i.e. Device, Peripheral, Register and
  274. Field) owns an <em>description </em>element containing verbose information about
  275. the respective element. The description field plays
  276. an important part in improving the software development productivity. Instead of
  277. searching through the reference manual the detailed explanation from the manual
  278. could become immediately accessible from within the development environment.</p>
  279. <p>Details about the exact display format and layout of the peripheral view are
  280. considered beyond the scope of the description. It is up to the tool vendor to
  281. visualize the contained information appropriately. The
  282. silicon vendor provides details about the device's peripherals that is commonly available. </p>
  283. <p>System View Description files need to be validated for:</p>
  284. <ol>
  285. <li>syntactical correctness using XML-Schema checking utilities</li>
  286. <li>consistency&nbsp; of the provided information (e.g. multiple registers mapped to the same address,
  287. all registers located within the specified address ranges of a
  288. peripheral, all fields are within the range of the register
  289. size, etc.) by a utility developed by ARM (SVDConv.exe)</li>
  290. <li>&nbsp;semantical correctness of the System View Description
  291. against the silicon specification executed by the silicon vendor</li>
  292. </ol>
  293. <p>The SVD description format was extended by numerous elements during the
  294. review period targeting version 1.0 and new extensions are expected for future
  295. versions of this format. A new section named &quot;vendorExtensions&quot; has been added
  296. to the end of the top level to allow silicon vendors and tool partners to
  297. innovate and expand the description in order to overcome limitations of the
  298. current specification until these can be incorporated into new versions of
  299. CMSIS-SVD. <br>
  300. </p>
  301. <h2>&nbsp;<a name="4"></a><span class="style9">Format</span></h2>
  302. <p>
  303. The following section describes the SVD file format in detail. Each subsection
  304. defines a single hierarchy level of the description and lists all mandatory
  305. and optional language elements for that specific level including type
  306. information for each element. Each element is discussed in more detail and a
  307. brief snippet is provided as an example. The sequence of elements shown
  308. below is binding. Optional elements are highlighted in green, blue elements
  309. are mandatory unless they have been already specified globally on a higher
  310. level.</p>
  311. <p>
  312. An XML-schema file is provided alongside this document for syntactical
  313. checking of descriptions being developed.</p>
  314. <h4>&lt;device schemaVersion=&quot;xs:decimal&quot; <span class="style2"><em>xmlns:xs=&quot;http://www.w3.org/2001/XMLSchema-instance&quot; xs:noNamespaceSchemaLocation=&quot;CMSIS-SVD_Schema_1_0.xsd</em></span>&quot;&gt;</h4>
  315. <p>&nbsp;&nbsp; &lt;<span class="style2">name&gt;<em>xs:Name</em>&lt;/name&gt;<br>
  316. &nbsp;&nbsp; &lt;version<em>&gt;xs:string&lt;</em>/version&gt;<br>
  317. &nbsp;&nbsp; &lt;description&gt;<em>xs:string</em>&lt;/description&gt;<br>
  318. </span>&nbsp;&nbsp; &lt;<span class="style2">addressUnitBits&gt;<em>scaledNonNegativeInteger</em>&lt;/addressUnitBits&gt;<br>
  319. &nbsp;&nbsp; &lt;width&gt;<em>scaledNonNegativeInteger</em> &lt;/width&gt;</span><br>
  320. <br>
  321. &nbsp;&nbsp;<span class="style4"> &lt;</span><span class="style2"><span class="style4">size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;<em><br>
  322. </em>&nbsp;&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
  323. &nbsp;&nbsp; &lt;resetValue&gt;<em>scaledNonNegativeIntege</em>r&lt;/resetValue&gt;<br>
  324. &nbsp;&nbsp; &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;</span></span></p>
  325. <p>&nbsp;&nbsp; &lt;peripherals&gt;<br>
  326. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
  327. &nbsp;&nbsp; &lt;/peripherals&gt;<br>
  328. <span class="style4">&nbsp;&nbsp; &lt;vendorExtensions&gt;<br>
  329. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
  330. &nbsp;&nbsp;&nbsp; &lt;/vendorExtensions&gt;</span></p>
  331. <h4>&lt;/device&gt;</h4>
  332. <p>The <strong>device</strong> provides the outermost frame of the description. All other
  333. elements like peripherals, registers and fields are described inside of this scope. A device contains one or more peripherals.
  334. The optional elements size, access, resetValue and resetMask are used as default values throughout the
  335. device description unless they get overruled on a lower level of the description
  336. (e.g. peripheral or register).</p>
  337. <h4>Mandatory items:</h4>
  338. <p><strong>name = </strong>the unique name string is used to identify the device.
  339. All devices of a silicon vendor are required to have a unique name. In case an
  340. SVD description covers a family or series of devices, the name of the series or
  341. family is placed here. The device names of the members of the series or family
  342. are listed in &lt;memberDevices&gt;</p>
  343. <p><strong>description = </strong>string describing main features of a device
  344. (e.g. CPU, clock frequency, peripheral overview, etc.)</p>
  345. <p><strong>version = </strong>the string is defining the version of the
  346. description for this device. Silicon vendors will maintain the description
  347. throughout the lifecycle of the device and need to ensure that all updated and
  348. released copies have a unique version string indicating the order in which. Note: this must not be used for
  349. detailing the version of the device.</p>
  350. <p>&nbsp;</p>
  351. <p><strong>addressUnitBits = </strong>defines the number of data bits for each address
  352. increment. The value for Cortex-M based devices is&nbsp; 8 (byte-addressable).</p>
  353. <p><strong>width = </strong>defines the number of bits for the maximum single
  354. transfer size allowed by the bus interface hence the maximum size of a single
  355. register that can be defined for the address space. This information is relevant
  356. for debuggers when determining the size of debug transfers. The expected value
  357. for Cortex-M based devices is 32.</p>
  358. <p><strong>peripherals = </strong>next level of description (see next section
  359. for details)</p>
  360. <h4>Optional Items:</h4>
  361. <p><strong>size = </strong>defines the default bit-width of registers contained
  362. in the device. This element can be overruled by re-specifying the size element on a lower level of the
  363. description.</p>
  364. <p><strong>access =</strong> defines the default access permissions for all
  365. registers in the device. The allowed tokens are:<br>
  366. &nbsp; - <em>read-only</em>: read access is permitted. Write operations have an undefined
  367. result.<br>
  368. &nbsp; - <em>write-only</em>: write access is permitted. Read operations have an
  369. undefined result. <br>
  370. &nbsp; -<em>read-write</em>: both read and write accesses are permitted. Writes affect
  371. the state of the register and reads return a value related to the register<br>
  372. &nbsp; -<em>writeOnce</em>: only the first write after reset has an effect on the
  373. register. Read operations deliver undefined results<br>
  374. &nbsp; -<em>read-writeOnce</em>: Read operations deliver a result related to the register
  375. content. Only the first write access to this register after a reset will have an
  376. effect on the register content.</p>
  377. <p><strong>resetValue = </strong>defines the default value of all registers
  378. after a reset. There are scenarios where SW developers need to know, what the
  379. reset value of a register or field is. Even though listed as optional on this
  380. level of the description, silicon vendors should ensure that this information is
  381. provided for all registers. </p>
  382. <p><strong>resetMask =</strong> defines those bit positions set to one to be
  383. taken from resetValue element. All other elements are undefined. If a register
  384. does not have a defined reset value the resetMask needs to be set to 0.</p>
  385. <p><strong>vendorExtensions </strong>= the content and format of this section of
  386. the description is unspecified. Silicon vendors may choose to provide additional
  387. information. The assumption is that by default this section is completely
  388. ignored by the debugger. It is up to the silicon vendor to specify the content
  389. of this section and share the specification with the tool vendors. The new
  390. elements shall be considered for a future version of the description format.</p>
  391. <h4>Example:</h4>
  392. <pre>&lt;device schemaVersion=&quot;1.0&quot; xmlns:xs=&quot;http://www.w3.org/2001/XMLSchema-instance&quot; xs:noNamespaceSchemaLocation=&quot;CMSIS-SVD_Schema_1_0.xsd&quot; &gt;
  393. &lt;name&gt;CMSIS_Cortex-M3&lt;/name&gt;
  394. &lt;version&gt;0.1&lt;/version&gt;
  395. &lt;description&gt;ARM Cortex-M3 based Microcontroller demonstration device&lt;/description&gt;
  396. &lt;addressUnitBits&gt;8&lt;/addressUnitBits&gt;
  397. &lt;width&gt;32&lt;/width&gt;
  398. &lt;size&gt;32&lt;/size&gt;
  399. &lt;access&gt;read-write&lt;/access&gt;
  400. &lt;resetValue&gt;0&lt;/resetValue&gt;
  401. &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;</pre>
  402. <pre> &lt;peripherals&gt;
  403. ...
  404. &lt;/peripherals&gt;
  405. &lt;/device&gt;</pre>
  406. <p>The device description above is at version 0.1 and uniquely identifies the
  407. device by the name &quot;CMSIS_Cortex-M3&quot;. The peripherals are memory mapped in a
  408. byte-addressable address space with a bus width of 32 bits. The default size of
  409. the registers contained in the peripherals is set to 32 bits. Unless redefined
  410. for specific peripherals, registers or fields all registers are read-write
  411. accessible. A reset value of 0 valid for all 32 bits as specified by the reset
  412. mask is set for all registers unless overruled at a lower level of the description.</p>
  413. <hr>
  414. <h4>&lt;peripherals&gt;</h4>
  415. <p>&nbsp;&nbsp; &lt;peripheral&gt;<br>
  416. &nbsp;&nbsp;&nbsp;&nbsp; ...<br>
  417. &nbsp;&nbsp; &lt;/peripheral&gt;</p>
  418. <p>&nbsp;&nbsp;&nbsp;&nbsp; ...</p>
  419. <p>&nbsp;&nbsp; &lt;peripheral&gt;<br>
  420. &nbsp;&nbsp;&nbsp;&nbsp; ...<br>
  421. &nbsp;&nbsp; &lt;/peripheral&gt;</p>
  422. <h4>&lt;/peripherals&gt;</h4>
  423. <p>This construct sets the frame for all peripherals and peripheral groups contained in a device. This
  424. creates a container element which ease-up processing with languages like Java.</p>
  425. <hr>
  426. <h4>&lt;peripheral <span class="style2"><span class="style4">derivedFrom=<em>&quot;xs:Name&quot;</em></span></span>&gt;</h4>
  427. <p>&nbsp;&nbsp; &lt;name&gt;<em>xs:Name</em>&lt;/name&gt;<br>
  428. &nbsp;&nbsp; <span class="style4">&lt;version&gt;xs:string&lt;/name&gt;</span><br>
  429. &nbsp;&nbsp; &lt;description&gt;<em>xs:string </em>&lt;/description&gt;<br>
  430. &nbsp;&nbsp; <span class="style4">&lt;groupName&gt;<em>xs:string</em>&lt;/groupName&gt;<br>
  431. &nbsp;&nbsp; &lt;prependToName&gt;<em>xs:string</em>&lt;/prependToName&gt;<br>
  432. &nbsp;&nbsp; &lt;appendToName&gt;<em>xs:string</em>&lt;/appendToName&gt;</span><br>
  433. &nbsp;&nbsp; <span class="style4">&lt;disableCondition&gt;<em>xs:string</em>&lt;/disableCondition&gt;</span><br>
  434. &nbsp;&nbsp; &lt;baseAddress&gt;<em>scaledNonNegativeInteger</em>&lt;/baseAddress&gt;<br>
  435. &nbsp;&nbsp;<span class="style4"> &lt;</span><span class="style2"><span class="style4">size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;<em><br>
  436. </em>&nbsp;&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
  437. &nbsp;&nbsp; &lt;resetValue&gt;<em>scaledNonNegativeIntege</em>r&lt;/resetValue&gt;<br>
  438. &nbsp;&nbsp; &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;</span></span></p>
  439. <p>&nbsp;&nbsp; <span class="style10">&lt;addressBlock&gt;<br>
  440. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;offset&gt;</span><em>scaledNonNegativeInteger</em><span class="style10">&lt;/offset&gt;<br>
  441. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;size&gt;</span><em>scaledNonNegativeInteger</em><span class="style10">&lt;/size&gt;<br>
  442. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;usage<em>&gt;usageType&lt;</em>/usage&gt;<br>
  443. <em>&nbsp;&nbsp; &lt;/</em>addressBlock&gt;<em><br>
  444. </em>&nbsp;&nbsp; ...<br>
  445. </span>&nbsp; <span class="style10"><span class="style4">&lt;addressBlock&gt;<br>
  446. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;offset&gt;</span></span><span class="style4"><em>scaledNonNegativeInteger</em></span><span class="style10"><span class="style4">&lt;/offset&gt;<br>
  447. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;size&gt;</span></span><span class="style4"><em>scaledNonNegativeInteger</em></span><span class="style10"><span class="style4">&lt;/size&gt;<br>
  448. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;usage&gt;<em>usageType</em>&lt;/usage&gt;<br>
  449. <em>&nbsp;&nbsp; &lt;/</em>addressBlock&gt;<br>
  450. &nbsp;&nbsp; &lt;interrupt&gt;<br>
  451. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;name&gt;<em>xs:string</em>&lt;/name&gt;<br>
  452. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;value&gt;<em>scaledNonNegativeInteger</em>&lt;/value&gt;<br>
  453. &nbsp;&nbsp; &lt;/interrupt&gt;</span><em><br>
  454. </em></span>&nbsp;&nbsp; &lt;registers&gt;<br>
  455. &nbsp;&nbsp; ...<br>
  456. &nbsp;&nbsp; &lt;/registers&gt;</p>
  457. <h4>&lt;/peripheral&gt;</h4>
  458. <p>A peripheral encloses the description of one or more registers belonging to
  459. this named peripheral. The address range allocated in the address space for this
  460. peripheral is defined through one or more address ranges. An address range is
  461. specified relative to the base address of the peripheral. This information
  462. allows to display a memory map overview for all peripherals. Please note that
  463. such a memory map does not contain any information for memories and unoccupied
  464. address ranges.</p>
  465. <h4>Mandatory items:</h4>
  466. <p><strong>name = </strong>name string used to identify the peripheral. Peripheral
  467. names are required to be unique within the scope of a device.</p>
  468. <p><strong>baseAddress </strong>= lowest address reserved or used by the peripheral</p>
  469. <p><strong>description = </strong>string providing an overview of the purpose
  470. and functionality of the peripheral</p>
  471. <p><strong>addressBlock = </strong>a peripheral may occupy one or more disparate
  472. blocks in the address space. An addressBlock is a complex element consisting of
  473. the mandatory elements:<br>
  474. &nbsp;&nbsp;&nbsp; <strong>offset</strong>: specifying the start address of an address block. It
  475. is calculated from the sum of baseAddress and offset<br>
  476. &nbsp;&nbsp;&nbsp; <strong>size</strong>: specifying the number of addressUnitBits being covered
  477. by this address block. The end address of an address block is the sum of start
  478. address and the size - 1.<br>
  479. &nbsp;&nbsp;&nbsp; <strong>usage</strong>: the usage element is of <em>usageType </em>specifying
  480. if the addresses within the specified address block is used for<strong> </strong>
  481. <em>registers</em><strong> </strong>or <em>buffer</em><strong> </strong>or is <em>reserved</em>.
  482. <br>
  483. Note: registers must not be allocated
  484. to an address within a reserved or buffer address range.</p>
  485. <p><strong>registers = </strong>next lower level of description (see next section
  486. for details)</p>
  487. <h4>Optional items:</h4>
  488. <p><strong>derivedFrom = </strong>this attribute specifies the name of a peripheral
  489. that has already been described for this device. The description of that device
  490. will be copied. It is mandatory to overwrite the name as well as the
  491. addressOffset. All other specified information will overwrite the respective
  492. elements in the copy.</p>
  493. <p><strong>version = </strong>the string specifies the version of this
  494. peripheral description.</p>
  495. <p><strong>disableCondition = </strong>C language compliant logical expression
  496. resulting in a true or false result. If &quot;true&quot; the refresh of the display
  497. for this peripheral is disabled
  498. and related accesses by the debugger are suppressed. Only constants and references to other registers
  499. contained in the description are allowed:&nbsp;
  500. &lt;peripheral&gt;-&gt;&lt;register&gt;-&gt;&lt;field&gt; (e.g.: (System-&gt;ClockControl-&gt;apbEnable == 0)).
  501. Only the following operators are allowed [&amp;&amp;,||, ==, !=, &gt;&gt;, &lt;&lt;, &amp;, |]. Warning!
  502. This feature must only be use in case accesses from the debugger to registers of
  503. un-clocked peripherals result in severe debugging failures. SVD is intended to
  504. be fully static information and not include any run-time computation or
  505. functions such capabilities may be added by the tools but is considered beyond
  506. the scope of this description language.</p>
  507. <p><strong>prependToName = </strong>all register names of this peripheral have
  508. their names prepended with the string specified</p>
  509. <p><strong>appendToName = </strong>all register names of this peripheral have
  510. their names appended with the string specified</p>
  511. <p><strong>size = </strong>defines the default bit-width of registers contained
  512. in the device. This element can be overruled by re-specifying the size element on a lower level of the
  513. description.</p>
  514. <p><strong>access =</strong> defines the default access permissions for all
  515. registers in the peripheral. The value can be reset on a lower level of the
  516. description. The allowed tokens are:<br>
  517. &nbsp; - <em>read-only</em>: read access is permitted. Write operations have an undefined
  518. result.<br>
  519. &nbsp; - <em>write-only</em>: write access is permitted. Read operations have an
  520. undefined result. <br>
  521. &nbsp; -<em>read-write</em>: both read and write accesses are permitted. Writes affect
  522. the state of the register and reads return a value related to the register<br>
  523. &nbsp; -<em>writeOnce</em>: only the first write after reset has an effect on the
  524. register. Read operations deliver undefined results<br>
  525. &nbsp; -<em>read-writeOnce</em>: Read operations deliver a result related to the register
  526. content. Only the first write access to this register after a reset will have an
  527. effect on the register content.</p>
  528. <p><strong>resetValue = </strong>defines the default value of all registers
  529. after a reset but can be set for individual registers and fields on a lower
  530. level of the description.</p>
  531. <p><strong>resetMask =</strong> defines those bit positions set to one to be
  532. taken from resetValue element. All other elements are undefined. This is the
  533. default value for the whole peripheral but can be readjusted on lower levels. If
  534. a register does not have a defined reset value the resetMask needs to be set to
  535. 0.</p>
  536. <p><strong>interrupt = </strong>is a complex type that consists of the <strong>name</strong> of
  537. the interrupt and the associated enumeration<strong> value</strong>. A peripheral can also have
  538. multiple associated interrupts. This entry is mainly intended for information
  539. only purposes in order to display the interrupts and respective interrupt
  540. numbers associated with a peripheral.</p>
  541. <h4>Example:</h4>
  542. <pre>...&nbsp;
  543. &lt;peripheral&gt;
  544. &lt;name&gt;Timer0&lt;/name&gt;
  545. &lt;version&gt;1.0.32&lt;/version&gt;
  546. &lt;description&gt;Timer 0 is a simple 16 bit timer counting down ... &lt;/description&gt;
  547. &lt;baseAddress&gt;0x40000000&lt;/baseAddress&gt;
  548. &lt;addressBlock&gt;
  549. &lt;offset&gt;0x0&lt;/offset&gt;
  550. &lt;size&gt;0x400&lt;/size&gt;
  551. &lt;usage&gt;registers&lt;/usage&gt;
  552. &lt;/addressBlock&gt;
  553. &lt;interrupt&gt;&lt;name&gt;TIM0_INT&lt;/name&gt;&lt;value&gt;34&lt;/value&gt;&lt;/interrupt&gt;
  554. &lt;registers&gt;
  555. ...
  556. &lt;/registers&gt;
  557. &lt;/peripheral&gt;
  558. &lt;peripheral derivedFrom=&quot;Timer0&quot;&gt;
  559. &lt;name&gt;Timer1&lt;/name&gt;
  560. &lt;baseAddress&gt;0x40000400&lt;/baseAddress&gt;
  561. &lt;/peripheral&gt;
  562. ...</pre>
  563. <hr>
  564. <h4>&lt;registers&gt; ... &lt;/registers&gt;</h4>
  565. <p>This construct sets the frame for all registers contained in a peripheral.
  566. This creates container elements which ease-up processing with languages like Java.</p>
  567. <hr>
  568. <h4>&lt;register <span class="style2">derivedFrom=<em>xs:Name</em></span>&gt;</h4>
  569. <p>&nbsp;&nbsp; <span class="style4">&lt;dim&gt;<em>scaledNonNegativeInteger</em>&lt;/dim&gt;<br>
  570. &nbsp;&nbsp; &lt;dimIncrement&gt;<em>scaledNonNegativeInteger</em>&lt;/dimIncrement&gt;<br>
  571. &nbsp;&nbsp; &lt;dimIndex&gt;<em>xs:string</em>&lt;/dimIndex&gt;</span><br>
  572. &nbsp;&nbsp; &lt;<span class="style2">name&gt;<em>xs:Name</em>&lt;/name&gt;<br>
  573. &nbsp;&nbsp; <span class="style4">&lt;displayName&gt;<em>xs:string</em>&lt;/displayName&gt;</span><br>
  574. </span>&nbsp;&nbsp; <span class="style2">&lt;description&gt;<em>xs:string</em>&lt;/description&gt;</span><br>
  575. &nbsp;<span class="style2">&nbsp; <span class="style4">&lt;alternateGroup&gt;<em>xs:Name</em>&lt;/alternateGroup&gt;</span><br>
  576. </span>&nbsp; <span class="style2">&nbsp;&lt;addressOffset&gt;<em>scaledNonNegativeInteger</em>
  577. &lt;/addressOffset&gt;<br>
  578. &nbsp;<span class="style5">&nbsp;&nbsp; &lt;size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;<br>
  579. </span><span class="style4">&nbsp;</span><span class="style5">&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
  580. &nbsp;&nbsp; </span><span class="style4">&lt;</span><span class="style5">resetValue&gt;<em>scaledNonNegativeInteger</em>&lt;/resetValue&gt;<br>
  581. &nbsp;&nbsp; &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;<br>
  582. </span>
  583. </span><span class="style4">&nbsp;&nbsp; &lt;modifiedWriteValues&gt;<em>writeValueType</em>&lt;/modifiedWriteValues&gt;<br>
  584. &nbsp;&nbsp; &lt;writeConstraint&gt;<em>writeConstraintType</em>&lt;/writeConstraint&gt;<br>
  585. &nbsp;&nbsp; &lt;readAction&gt;<em>readActionType</em> &lt;/readAction&gt;</span><span class="style2"><br>
  586. </span>&nbsp;&nbsp; <span class="style4">&lt;fields&gt;<br>
  587. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
  588. &nbsp;&nbsp; &lt;/fields&gt;</span> </p>
  589. <h4>&lt;/register&gt;</h4>
  590. <p>The definition of registers is the central part of the description. A
  591. register may use its complete size for a single purpose and therefore not
  592. consist of fields. Otherwise the description
  593. of fields is mandatory.</p>
  594. <h4>Mandatory items:<br>
  595. </h4>
  596. <p><strong>name = </strong>name string used to identify the register. Register
  597. names are required to be unique within the scope of a peripheral.</p>
  598. <p><strong>description = </strong>string describing the details of the register.</p>
  599. <p><strong>addressOffset = </strong>value defining the address of the register relative to
  600. the baseAddress defined by the peripheral the register belongs to.<br>
  601. </p>
  602. <p><span class="style5">The following elements can be omitted</span> if the corresponding value has been set
  603. on a higher level of the description and matches the value required for this register:</p>
  604. <p><strong>size =</strong>value defining the bit-width of the register</p>
  605. <p><strong>access =</strong> predefined tokens: read-only, write-only, read-write,
  606. writeOnce, read-writeOnce strings defining the allowed
  607. accesses for this register.</p>
  608. <p><strong>resetValue =</strong> element defining the value of the register
  609. immediately after a reset.</p>
  610. <p><strong>resetMask= </strong>element specifying those bits of the resetValue that
  611. are defined<strong> </strong>(bit positions containing a 0 bit are ignored, bit
  612. positions containing a 1 bit are taken from the corresponding bit position of
  613. the resetValue). If a register does not have a defined reset value the resetMask
  614. needs to be set to 0.</p>
  615. <h4>Optional items:</h4>
  616. <p><strong>dim = </strong>if this field is specified the value defines the
  617. number of elements in an array of registers.</p>
  618. <p><strong>dimIncrement =</strong> if dim is specified this element becomes
  619. mandatory and specifies the address increment in between
  620. two neighboring registers of the register array in the address map.</p>
  621. <p><strong>dimIndex = </strong>this element specifies the substrings within the
  622. register array names that will replace the %s within the register name. By
  623. default the index is a decimal value starting with 0 for the first register.
  624. Examples:<br>
  625. &nbsp;&nbsp; &lt;dim&gt;6&lt;/dim&gt; &lt;dimIncrement&gt;4&lt;/dimIncrement&gt; &lt;dimIndex&gt;A,B,C,D,E,Z&lt;/dimIndex&gt;
  626. &lt;name&gt;GPIO_%s_CTRL&lt;/name&gt; ...<br>
  627. &nbsp;&nbsp; =&gt; GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL,
  628. GPIO_Z_CTRL<br>
  629. &nbsp;&nbsp; &lt;dim&gt;4&lt;/dim&gt; &lt;dimIncrement&gt;4&lt;/dimIncrement&gt; &lt;dimIndex&gt;3-6&lt;/dimIndex&gt;
  630. &lt;name&gt;IRQ%s&lt;/name&gt; ... <br>
  631. &nbsp;&nbsp; =&gt; IRQ3, IRQ4, IRQ5, IRQ6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </p>
  632. <p><strong>displayName = </strong>when used, this is the string being used by a
  633. graphical frontend to visualize the register otherwise the name element is used.
  634. Note: the display name may contain special characters and white spaces. It also
  635. uses &quot;%s&quot; as the place holder for the dimIndex substring.</p>
  636. <p><strong>alternateGroup =</strong> when used, this element specifies a name of
  637. a group that all alternate register with the same name a associated with. At the
  638. same time it indicates that there is a register description allocating the same
  639. absolute address in the address space. </p>
  640. <p><strong>modifiedWriteValues = </strong>element to describe the manipulation of
  641. data written to a register. If not specified the value written to the field is the
  642. value stored in the field. The other options are bitwise operations: <br>
  643. &nbsp; <em>oneToClear:</em> write data bits of one shall clear (set to zero) the
  644. corresponding bit in the register<br>
  645. &nbsp; <em>oneToSet:</em> write data bits of one shall set (set to one) the
  646. corresponding bit in the register<br>
  647. &nbsp; <em>oneToToggle:</em> write data bits of one shall toggle (invert) the
  648. corresponding bit in the register<br>
  649. &nbsp; <em>zeroToClear:</em> write data bits of zero shall clear (set to zero)
  650. the corresponding bit in the register<br>
  651. &nbsp; <em>zeroToSet:</em> write data bits of zero shall set (set to one) the
  652. corresponding bit in the register<br>
  653. &nbsp; <em>zeroToToggle:</em> write data bits of zero shall toggle (invert) the
  654. corresponding bit in the register<br>
  655. &nbsp; <em>clear:</em> after a write operation all bits in the field are cleared (set to
  656. zero)<br>
  657. &nbsp; <em>set:</em> after a write operation all bits in the field are set (set to one)<br>
  658. &nbsp; <em>modify:</em> after a write operation all bit in the field may be modified
  659. (default)</p>
  660. <p><strong>writeConstraint: </strong>has a set of options:<br>
  661. &nbsp; <em>writeAsRead</em> = if true only the last read value can be written<br>
  662. &nbsp; <em>useEnumeratedValues</em> = if true only those values listed in the
  663. enumeratedValues list are considered valid write values<br>
  664. &nbsp; <em>minimum</em> = specifies the smallest number to be written to the
  665. register<br>
  666. &nbsp; <em>maximum</em> = specifies the largest number to be written to the
  667. register</p>
  668. <p><strong>readAction: </strong>if set it specifies the side effect following
  669. read operations. If not set the register is not modified following a read
  670. operations. The defined side effects are:<br>
  671. &nbsp; <em>clear:</em> indicates that the register is cleared (set to zero)
  672. following a read operation<br>
  673. &nbsp; <em>set:</em> indicates that the register is set (set to ones) following a
  674. read operation<br>
  675. &nbsp; <em>modify</em>: indicates that the register is modified in some way
  676. after a read operation<br>
  677. &nbsp; <em>modifyExternal: </em>indicates that one or more dependent resources
  678. other than the current register
  679. are immediately affected by a read (it is recommended that the register
  680. description specifies these dependencies). Debuggers are not expected to read
  681. this register location unless explicitly instructed by user.</p>
  682. <p><strong>fields = </strong>next lower level of description (see next section
  683. for details).</p>
  684. <h4>Optional attribute:</h4>
  685. <p><strong>derivedFrom = </strong>specifies the name of the register to be
  686. replicated. Elements being specified underneath will override the values specified
  687. from the register being derived from. Note that it is mandatory to overwrite at
  688. least name and addressOffset.</p>
  689. <h4>Example:</h4>
  690. <pre>...&nbsp;
  691. &lt;register&gt;
  692. &lt;name&gt;TimerCtrl0&lt;/name&gt;
  693. &lt;description&gt;Timer Control Register&lt;/description&gt;
  694. &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
  695. &lt;access&gt;read-write&lt;/access&gt;
  696. &lt;resetValue&gt;0x00008001&lt;/resetValue&gt;
  697. &lt;resetMask&gt;0x0000ffff&lt;/resetMask&gt;
  698. &lt;size&gt;32&lt;size&gt;
  699. &lt;fields&gt;
  700. ...
  701. &lt;/fields&gt;
  702. &lt;/register&gt;
  703. &lt;register derivedFrom=&quot;TimerCtrl0&quot;&gt;
  704. &lt;name&gt;TimerCtrl1&lt;/name&gt;
  705. &lt;addressOffset&gt;0x4&lt;addressOffset&gt;
  706. &lt;/register&gt;
  707. ...</pre>
  708. <hr>
  709. <h4>&lt;fields&gt; ... &lt;/fields&gt;</h4>
  710. <p>This construct sets the frame for all fields contained in a register.
  711. This creates container elements which ease-up processing with languages like Java.</p>
  712. <hr>
  713. <h4>&nbsp;&lt;field <span class="style2">derivedFrom=<em>&quot;xs:Name</em>&quot;</span>&gt;</h4>
  714. <p>&nbsp;<span class="style2">&nbsp; &lt;name&gt;<em>xs:Name&lt;/name&gt;<br>
  715. &nbsp;</em></span>&nbsp; &lt;description&gt;<em>xs:string</em>&lt;/description&gt;<br>
  716. <span class="style5">&nbsp;</span><span class="style2"><span class="style5"><em>&nbsp; </em>
  717. </span>&lt;<span class="style5">bitOffset&gt;<em>scaledNonNegativeInteger&lt;/</em>bitOffset&gt;
  718. </span>&lt;<span class="style5">bitWidth&gt;<em>scaledNonNegativeInteger</em>&lt;/bitWidth&gt;<br>
  719. &nbsp;&nbsp; </span><span class="style6">or</span><span class="style5"><br>
  720. &nbsp;&nbsp; &lt;lsb&gt;scaledNonNegativeInteger&lt;/lsb&gt; &lt;msb&gt;scaledNonNegativeInteger&lt;/msb&gt;<br>
  721. &nbsp;&nbsp; </span><span class="style6">or</span><span class="style5"><br>
  722. &nbsp;&nbsp; &lt;bitRange&gt;<em>pattern</em>&lt;/bitRange&gt;<br>
  723. &nbsp;&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
  724. </span></span><span class="style4">&nbsp;&nbsp; &lt;modifiedWriteValues&gt;<em>writeValueType</em>&lt;/modifiedWriteValues&gt;<br>
  725. &nbsp;&nbsp; &lt;writeConstraint&gt;<em>writeConstraintType</em>&lt;/writeConstraint&gt;<br>
  726. &nbsp;&nbsp; &lt;readAction&gt;<em>readActionType</em> &lt;/readAction&gt;</span><span class="style2"><br>
  727. &nbsp;</span>&nbsp; <span class="style4">&lt;enumeratedValues&gt;<br>
  728. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
  729. &nbsp;&nbsp; &lt;/enumeratedValues&gt;</span></p>
  730. <h4>&lt;/field&gt;</h4>
  731. <p>A bit-field has a name that is unique for the register it belongs to. The
  732. position and size within the register is either described by the combination of
  733. the least significant bit's position (lsb) and the most significant bit's
  734. position (msb) or the lsb and the size, specifying the bit-width of the
  735. field.&nbsp; A field may define an enumeratedValue in order to make the display
  736. more intuitive to read. </p>
  737. <h4>Mandatory items:</h4>
  738. <p><strong>name = </strong>name string used to identify the field. Field names
  739. are required to be unique within the scope of a register.<br>
  740. </p>
  741. <p><strong>description = </strong>string describing the details of the register.<br>
  742. </p>
  743. <p>There are 3 ways to describe a field to be used mutually exclusive:<br>
  744. a) specifying bitOffset and bitWidth (IP-XACT like)<br>
  745. b) specifying lsb and msb of the field.<br>
  746. c) specifying a bit range in the format &quot;[&lt;msb&gt;:&lt;lsb&gt;]&quot;</p>
  747. <p><strong>bitOffset = </strong>value defining the position of the least significant bit
  748. of the field within the register it belongs to.<br>
  749. <strong>bitWidth = </strong>value defining the bit-width of the bitfield within the
  750. register it belongs to.<br>
  751. </p>
  752. <p>
  753. <strong>lsb =</strong> value defining the bit position of the least significant
  754. bit within the register it belongs to.<br>
  755. <strong>msb =</strong> value defining the bit position of the most significant
  756. bit within the register it belongs to.
  757. </p>
  758. <p><strong>bitRange = </strong>a string in the format: [&lt;msb&gt;:&lt;lsb&gt;]<br>
  759. </p>
  760. <h4>Optional items:</h4>
  761. <p><strong>derivedFrom = </strong>the field is cloned
  762. from a previously defined field with a unique name.</p>
  763. <p><strong>access =</strong> predefined strings defining the allowed
  764. accesses for this register: <em>read-only, write-only, read-write, writeOnce,
  765. read-writeOnce</em><strong>.</strong> Can be omitted if it matches the access permission set for the parent register.</p>
  766. <p><strong>enumeratedValues = </strong>next lower level of description (see next section
  767. for details)</p>
  768. <p><strong>modifiedWriteValues = </strong>element to describe the manipulation of
  769. data written to a field. If not specified the value written to the field is the
  770. value stored in the field. The other options are bitwise operations: <br>
  771. &nbsp; <em>oneToClear:</em> write data bit of one shall clear (set to zero) the
  772. corresponding bit in the field<br>
  773. &nbsp; <em>oneToSet:</em> write data bit of one shall set (set to one) the corresponding
  774. bit in the field<br>
  775. &nbsp; <em>oneToToggle:</em> write data bit of one shall toggle (invert) the
  776. corresponding bit in the field<br>
  777. &nbsp; <em>zeroToClear:</em> write data bit of zero shall clear (set to zero) the
  778. corresponding bit in the field<br>
  779. &nbsp; <em>zeroToSet:</em> write data bit of zero shall set (set to one) the
  780. corresponding bit in the field<br>
  781. &nbsp; <em>zeroToToggle:</em> write data bit of zero shall toggle (invert) the
  782. corresponding bit in the field<br>
  783. &nbsp; <em>clear:</em> after a write operation all bits in the field are cleared (set to
  784. zero)<br>
  785. &nbsp; <em>set:</em> after a write operation all bits in the field are set (set to one)<br>
  786. &nbsp; <em>modify:</em> after a write operation all bit in the field may be modified
  787. (default)</p>
  788. <p><strong>writeConstraint: </strong>has a set of options:<br>
  789. &nbsp; <em>writeAsRead</em> = if true only the last read value can be written<br>
  790. &nbsp; <em>useEnumeratedValues</em> = if true only those values listed in the
  791. enumeratedValues list are considered valid write values<br>
  792. &nbsp; <em>minimum</em> = specifies the smallest number to be written to the field<br>
  793. &nbsp; <em>maximum</em> = specifies the largest number to be written to the field</p>
  794. <p><strong>readAction: </strong>if set it specifies the side effect following
  795. read operations. If not set the field is not modified following a read
  796. operations. The defined side effects are:<br>
  797. &nbsp; <em>clear:</em> indicates that the field is cleared (set to zero)
  798. following a read operation<br>
  799. &nbsp; <em>set:</em> indicates that the field is set (set to ones) following a
  800. read operation<br>
  801. &nbsp; <em>modify</em>: indicates that the field is modified in some way after a
  802. read operation&nbsp;
  803. <br>
  804. &nbsp; <em>modifyExternal: </em>indicates that one or more dependent resources
  805. other than this field are immediately affected by a read (it is recommended that
  806. the field description specifies these dependencies). Debuggers are not expected
  807. to read the field unless explicitly instructed by user.</p>
  808. <h4>Example:</h4>
  809. <pre>...
  810. &lt;field&gt;
  811. &lt;name&gt;TimerCtrl0_IntSel&lt;/name&gt;
  812. &lt;description&gt;Select interrupt line t<span class="style8">hat is triggered by timer overflow</span>.&lt;/description&gt;
  813. &lt;bitOffset&gt;1&lt;/bitOffset&gt;
  814. &lt;bitWidth&gt;3&lt;/bitWidth&gt;
  815. &lt;access&gt;read-write&lt;/access&gt;
  816. &lt;resetValue&gt;0x0&lt;/resetValue&gt;
  817. &lt;modifiedWriteValues&gt;oneToSet&lt;/modifiedWriteValues&gt;
  818. &lt;writeConstraint&gt;
  819. &lt;range&gt;
  820. &lt;minimum&gt;0&lt;/minimum&gt;
  821. &lt;maximum&gt;5&lt;/maximum&gt;
  822. &lt;/range&gt;
  823. &lt;/writeConstraint&gt;
  824. &lt;readAction&gt;clear&lt;/readAction&gt;
  825. &lt;enumeratedValues&gt;
  826. ...
  827. &lt;/enumeratedValues&gt;
  828. &lt;/field&gt;
  829. ...</pre>
  830. <hr>
  831. <h4 class="style3">&lt;enumeratedValues <span class="style2">
  832. <span class="style4">derivedFrom=</span><em>&quot;<span class="style4">xs:Name&quot;</span></em></span>&gt;</h4>
  833. <p>&nbsp;<span class="style2"><span class="style4">&nbsp; &lt;name&gt;<em>xs:Name</em>&lt;/name</span></span>&gt;<span class="style4"><br>
  834. &nbsp;&nbsp; &lt;usage&gt;<em>usageType</em>&lt;/usage&gt;</span><br>
  835. &nbsp;&nbsp; &lt;enumeratedValue&gt;<br>
  836. &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
  837. &nbsp;&nbsp; &lt;/enumeratedValue&gt;</p>
  838. <p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...&nbsp;</p>
  839. <p>&nbsp;&nbsp;&nbsp;&lt;enumeratedValue&gt;<br>
  840. &nbsp;&nbsp; &nbsp;&nbsp; ...<br>
  841. &nbsp;&nbsp; &lt;/enumeratedValue&gt;</p>
  842. <h4>&lt;/enumeratedValues&gt;</h4>
  843. <p>An enumerated value provides one or more enumeration items (enumeratedValue), defining a map
  844. between all possible values of the bit-field it belongs to and the corresponding
  845. human readable semantics of that value.</p>
  846. <p>Mandatory items:<br>
  847. <strong>enumeratedValue = </strong>next lower level of description (see next section
  848. for details)</p>
  849. <p>Optional items:<br>
  850. <strong>derivedFrom = </strong>the enumeratedValues can be copied or derived
  851. from a previously defined enumeratedValue that has been given a unique name.<br>
  852. <strong>name =</strong> name string to identify an enumeratedValue. Named
  853. enumeratedValues need to be unique in the scope of a device in order to be reusable
  854. throughout the description of a device.<br>
  855. <strong>usage = </strong>possible values are <strong>read, write </strong>or
  856. <strong>read-write.</strong> This allows to specify two different enumerated values
  857. depending whether it is to be used for a read or a write access. If not specified the enueratedValues are valid for read and write.</p>
  858. <h4>Example:</h4>
  859. <pre>...
  860. &lt;enumeratedValues&gt;
  861. &lt;name&gt;TimerIntSelect&lt;/name&gt;
  862. &lt;usage&gt;read-write&lt;/usage&gt;
  863. &lt;enumeratedValue&gt;
  864. &lt;name&gt;disabled&lt;/name&gt;
  865. &lt;description&gt;disabled bit&lt;/description&gt;
  866. &lt;value&gt;0&lt;/value&gt;
  867. &lt;/enumeratedValue&gt;
  868. ...
  869. &lt;enumeratedValue&gt;
  870. &lt;name&gt;reserved&lt;/name&gt;
  871. &lt;description&gt;reserved values. Do not use&lt;/description&gt;
  872. &lt;isDefault&gt;true&lt;/isDefault&gt;
  873. &lt;/enumeratedValue&gt;
  874. &lt;/enumeratedValues&gt;
  875. ...</pre>
  876. <hr>
  877. <h4>&lt;enumeratedValue&gt;</h4>
  878. <p>&nbsp;&nbsp; &lt;name<em>&gt;xs:name</em>&lt;/name&gt;<br>
  879. &nbsp;&nbsp; <span class="style10"><span class="style4">&lt;description&gt;xs:<em>string</em>&lt;/description&gt;</span><br>
  880. </span><em>&nbsp;&nbsp; &lt;</em>value<span class="style2">&gt;<em>scaledNonNegativeInteger</em>&lt;/value&gt;<em><br>
  881. &nbsp;&nbsp;
  882. </em>or<em><br>
  883. &nbsp;&nbsp; &lt;</em>isDefault&gt;<em>xs:boolean</em>&lt;/isDefault&gt;<em><br>
  884. </em></span></p>
  885. <h4>&lt;/enumeratedValue&gt;</h4>
  886. <p>An enumeratedValue defines a map between a value and the string reading the
  887. corresponding human readable semantics for that value in a brief and a detailed
  888. version</p>
  889. <h4>Mandatory items:</h4>
  890. <p><strong>name=</strong> brief string verbally describing the semantics of the value
  891. defined for this enumeratedValue. E.g. used for display in visualization of a bit-field
  892. instead of the value.</p>
  893. <p>
  894. <strong>value = </strong>defines the constant of the bit-field that the name
  895. corresponds to<strong>.</strong></p>
  896. <p><strong>isDefault = </strong>defines the name and description for all other
  897. values that are not explicitly listed</p>
  898. <h4>Optional item:</h4>
  899. <p><strong>description = </strong>extended string verbally describing the semantics
  900. of the value defined for this enumeratedValue in full detail.</p>
  901. <h4>Example:</h4>
  902. <pre>...
  903. &lt;enumeratedValue&gt;
  904. &lt;name&gt;disabled&lt;/name&gt;
  905. &lt;description&gt;Timer does not generate interrupts&lt;/description&gt;
  906. &lt;value&gt;0&lt;/value&gt;
  907. &lt;/enumeratedValue&gt;
  908. ...
  909. &lt;enumeratedValue&gt;
  910. &lt;name&gt;enabled&lt;/name&gt;
  911. &lt;description&gt;Timer does not generate interrupts&lt;/description&gt;
  912. &lt;isDefault&gt;true&lt;/isDefault&gt;
  913. &lt;/enumeratedValue&gt;
  914. ...</pre>
  915. <hr>
  916. <h4>Names</h4>
  917. <p>Names shall comply with ANSI C variable naming restrictions.</p>
  918. <h4>Constants</h4>
  919. <p>Number constants shall be entered in hexadecimal, decimal or binary format.</p>
  920. <ul>
  921. <li>hexadecimal is indicated by a leading &quot;0x&quot;</li>
  922. <li>binary format is indicated by a leading&nbsp; &quot;#&quot;</li>
  923. <li>all other formats are interpreted as decimal numbers</li>
  924. <li>the value tag in enumeratedValue accepts do not care bits
  925. represented by &quot;x&quot;</li>
  926. </ul>
  927. <h4><b>Comments</b> </h4>
  928. <p>Comments have the standard XML format <strong>&quot;&lt;!--&quot;</strong> starts a comment
  929. <strong><span class="style2">&quot;--&gt;&quot;</span></strong> terminates a comment</p>
  930. <h2>Example</h2>
  931. <pre>
  932. &lt;?xml version=&quot;1.0&quot; encoding=&quot;utf-8&quot;?&gt;
  933. &nbsp;
  934. &lt;device schemaVersion=&quot;1.0&quot; xmlns:xs=&quot;http://www.w3.org/2001/XMLSchema-instance&quot; xs:noNamespaceSchemaLocation=&quot;CMSIS-SVD_Schema_1_0.xsd&quot; &gt;
  935. &lt;name&gt;Cortex_M3_Sample&lt;/name&gt;
  936. &lt;version&gt;0.1&lt;/version&gt;
  937. &lt;description&gt;ARM Cortex-M3 based Microcontroller dummy device&lt;/description&gt;
  938. &lt;!-- Bus Interface Properties --&gt;
  939. &lt;!-- Cortex-M3 is byte addressable --&gt;
  940. &lt;addressUnitBits&gt;8&lt;/addressUnitBits&gt;
  941. &lt;!-- the maximum data bit width accessible within a single transfer is 32bits --&gt;
  942. &lt;width&gt;32&lt;/width&gt;
  943. &lt;!-- Register Default Properties --&gt;
  944. &lt;!-- the size of the registers is set to a bit width of 32. This can be overruled for individual peripherals and/or registers --&gt;
  945. &lt;size&gt;32&lt;/size&gt;
  946. &lt;!-- the access to all registers is set to be readable and writeable. This can be overruled for individual peripherals and/or registers --&gt;
  947. &lt;access&gt;read-write&lt;/access&gt;
  948. &lt;!-- for demonstration purposes the resetValue for all registers of the device is set to be 0. This can be overruled within the description --&gt;
  949. &lt;resetValue&gt;0&lt;/resetValue&gt;
  950. &lt;!-- the resetMask = 0 specifies that by default no register of this device has a defined reset value --&gt;
  951. &lt;resetMask&gt;0&lt;/resetMask&gt;
  952. &lt;peripherals&gt;
  953. &lt;peripheral&gt;
  954. &lt;name&gt;Timer0&lt;/name&gt;
  955. &lt;description&gt;A simple 16 bit timer counting down ... &lt;/description&gt;
  956. &lt;groupName&gt;Timer&lt;/groupName&gt;
  957. &lt;baseAddress&gt;0x40000000&lt;/baseAddress&gt;
  958. &lt;!-- the first addressBlock is occupied by registers. The second block is reserved -&gt; no access permission --&gt;
  959. &lt;addressBlock&gt;
  960. &lt;offset&gt;0&lt;/offset&gt;
  961. &lt;size&gt;0x8&lt;/size&gt;
  962. &lt;usage&gt;registers&lt;/usage&gt;
  963. &lt;/addressBlock&gt;
  964. &lt;addressBlock&gt;
  965. &lt;offset&gt;0x8&lt;/offset&gt;
  966. &lt;size&gt;0x3f8&lt;/size&gt;
  967. &lt;usage&gt;reserved&lt;/usage&gt;
  968. &lt;/addressBlock&gt;
  969. &lt;interrupt&gt;
  970. &lt;name&gt;TIM0_IRQn&lt;/name&gt;
  971. &lt;value&gt;34&lt;/value&gt;
  972. &lt;/interrupt&gt;
  973. &lt;registers&gt;
  974. &lt;register&gt;
  975. &lt;name&gt;TimerCtrl0&lt;/name&gt;
  976. &lt;!-- the display name is an unrestricted string. --&gt;
  977. &lt;displayName&gt;Timer Ctrl 0&lt;/displayName&gt;
  978. &lt;description&gt;Timer Control Register&lt;/description&gt;
  979. &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
  980. &lt;!-- size=32, access=read-write, resetValue=0x0, resetMask=0xffffffff, volatile=false --&gt;
  981. &lt;fields&gt;
  982. &lt;field&gt;
  983. &lt;name&gt;TimerCtrl0_En&lt;/name&gt;
  984. &lt;description&gt;Enable Bit activates the timer.&lt;/description&gt;
  985. &lt;!-- Spirit like bit range description: [0:0] --&gt;
  986. &lt;bitOffset&gt;0&lt;/bitOffset&gt;
  987. &lt;bitWidth&gt;1&lt;/bitWidth&gt;
  988. &lt;!-- Writing 1 enables, writing 0 has no effect --&gt;
  989. &lt;modifiedWriteValues&gt;oneToSet&lt;/modifiedWriteValues&gt;
  990. &lt;!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed --&gt;
  991. &lt;writeConstraint&gt;
  992. &lt;useEnumeratedValues&gt;true&lt;/useEnumeratedValues&gt;
  993. &lt;/writeConstraint&gt;
  994. &lt;!-- there is no side effect on reads, therefore &lt;readAction&gt; is not set --&gt;
  995. &lt;!-- oneBitEnable named enumeration that can be reused in other parts of the description --&gt;
  996. &lt;enumeratedValues&gt;
  997. &lt;name&gt;oneBitEnable&lt;/name&gt;
  998. &lt;!-- the same enumerated Values are used for read and write. This default is assumed when this tag is missing --&gt;
  999. &lt;usage&gt;read-write&lt;/usage&gt;
  1000. &lt;enumeratedValue&gt;
  1001. &lt;name&gt;enabled&lt;/name&gt;
  1002. &lt;description&gt;Timer is enabled and active&lt;/description&gt;
  1003. &lt;value&gt;0x0&lt;/value&gt;
  1004. &lt;/enumeratedValue&gt;
  1005. &lt;enumeratedValue&gt;
  1006. &lt;name&gt;disabled&lt;/name&gt;
  1007. &lt;description&gt;Timer is disabled and inactive&lt;/description&gt;
  1008. &lt;value&gt;0x1&lt;/value&gt;
  1009. &lt;/enumeratedValue&gt;
  1010. &lt;/enumeratedValues&gt;
  1011. &lt;/field&gt;
  1012. &lt;field&gt;
  1013. &lt;name&gt;TimerCtrl0_Dis&lt;/name&gt;
  1014. &lt;description&gt;Disable Bit deactivates the timer.&lt;/description&gt;
  1015. &lt;!-- Spirit like bit range description: [1:1] --&gt;
  1016. &lt;bitOffset&gt;1&lt;/bitOffset&gt;
  1017. &lt;bitWidth&gt;1&lt;/bitWidth&gt;
  1018. &lt;!-- Writing 1 sets, writing 0 has no effect --&gt;
  1019. &lt;modifiedWriteValues&gt;oneToSet&lt;/modifiedWriteValues&gt;
  1020. &lt;!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed --&gt;
  1021. &lt;writeConstraint&gt;
  1022. &lt;useEnumeratedValues&gt;true&lt;/useEnumeratedValues&gt;
  1023. &lt;/writeConstraint&gt;
  1024. &lt;!-- there is no side effect on reads, therefore &lt;readAction&gt; is not set --&gt;
  1025. &lt;!-- oneBitEnable named enumeration that can be reused in other parts of the description --&gt;
  1026. &lt;enumeratedValues derivedFrom=&quot;oneBitEnable&quot;&gt;&lt;/enumeratedValues&gt;
  1027. &lt;/field&gt;
  1028. &lt;field&gt;
  1029. &lt;name&gt;TimerCtrl0_Int&lt;/name&gt;
  1030. &lt;description&gt;Select interrupt line that is triggered by timer overflow.&lt;/description&gt;
  1031. &lt;!-- the position of the bit field is described in the bitRange style. --&gt;
  1032. &lt;bitRange&gt;[4:2]&lt;/bitRange&gt;
  1033. &lt;enumeratedValues&gt;
  1034. &lt;enumeratedValue&gt;
  1035. &lt;name&gt;disabled&lt;/name&gt;
  1036. &lt;description&gt;Timer does not generate interrupts&lt;/description&gt;
  1037. &lt;value&gt;0&lt;/value&gt;
  1038. &lt;/enumeratedValue&gt;
  1039. &lt;enumeratedValue&gt;
  1040. &lt;name&gt;int 0&lt;/name&gt;
  1041. &lt;description&gt;Timer does generate interrupts on interrupt line 0&lt;/description&gt;
  1042. &lt;value&gt;1&lt;/value&gt;
  1043. &lt;/enumeratedValue&gt;
  1044. &lt;enumeratedValue&gt;
  1045. &lt;name&gt;int 1&lt;/name&gt;
  1046. &lt;description&gt;Timer does generate interrupts on interrupt line 1&lt;/description&gt;
  1047. &lt;value&gt;2&lt;/value&gt;
  1048. &lt;/enumeratedValue&gt;
  1049. &lt;enumeratedValue&gt;
  1050. &lt;name&gt;int 2&lt;/name&gt;
  1051. &lt;description&gt;Timer does generate interrupts on interrupt line 2&lt;/description&gt;
  1052. &lt;value&gt;3&lt;/value&gt;
  1053. &lt;/enumeratedValue&gt;
  1054. &lt;enumeratedValue&gt;
  1055. &lt;name&gt;int 3&lt;/name&gt;
  1056. &lt;description&gt;Timer does generate interrupts on interrupt line 3&lt;/description&gt;
  1057. &lt;value&gt;4&lt;/value&gt;
  1058. &lt;/enumeratedValue&gt;
  1059. &lt;enumeratedValue&gt;
  1060. &lt;name&gt;int 4&lt;/name&gt;
  1061. &lt;description&gt;Timer does generate interrupts on interrupt line 4&lt;/description&gt;
  1062. &lt;value&gt;5&lt;/value&gt;
  1063. &lt;/enumeratedValue&gt;
  1064. &lt;!-- this is the default element. All the valid value not listed above (6,7) have the following name and description --&gt;
  1065. &lt;enumeratedValue&gt;
  1066. &lt;name&gt;reserved&lt;/name&gt;
  1067. &lt;description&gt;Timer is configured incorrectly and the functionality is considered unpredictable&lt;/description&gt;
  1068. &lt;isDefault&gt;true&lt;/isDefault&gt;
  1069. &lt;/enumeratedValue&gt;
  1070. &lt;/enumeratedValues&gt;
  1071. &lt;/field&gt;
  1072. &lt;/fields&gt;
  1073. &lt;/register&gt;
  1074. &lt;register&gt;
  1075. &lt;name&gt;TimerCounter0&lt;/name&gt;
  1076. &lt;description&gt;Timer0 16 Bit Counter Register&lt;/description&gt;
  1077. &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
  1078. &lt;size&gt;16&lt;/size&gt;
  1079. &lt;/register&gt;
  1080. &lt;!-- a copy of the counter register TimerCounter0 with the name=&quot;TimerCounter1&quot; and the addressOffset=&quot;0x8&quot; --&gt;
  1081. &lt;register derivedFrom=&quot;TimerCounter0&quot;&gt;
  1082. &lt;name&gt;TimerCounter1&lt;/name&gt;
  1083. &lt;addressOffset&gt;0x6&lt;/addressOffset&gt;
  1084. &lt;/register&gt;
  1085. &lt;!-- ... this is a restricted demo example and a real timer peripheral would have more register to be complete --&gt;
  1086. &lt;/registers&gt;
  1087. &lt;/peripheral&gt;
  1088. &lt;!-- a copy of Timer0 with the name=&quot;Timer1 and the baseAddress=&quot;0x40000400&quot; --&gt;
  1089. &lt;peripheral derivedFrom=&quot;Timer0&quot;&gt;
  1090. &lt;name&gt;Timer1&lt;/name&gt;
  1091. &lt;baseAddress&gt;0x40000400&lt;/baseAddress&gt;
  1092. &lt;interrupt&gt;
  1093. &lt;name&gt;TIM1_IRQn&lt;/name&gt;
  1094. &lt;value&gt;35&lt;/value&gt;
  1095. &lt;/interrupt&gt;
  1096. &lt;/peripheral&gt;
  1097. &lt;/peripherals&gt;
  1098. &lt;/device&gt;</pre>
  1099. <h2><a name="6"></a>Questions &amp; Answers</h2>
  1100. <h3>Is there any relation between the System View Description and the CMSIS
  1101. standard?</h3>
  1102. <p>Initiallly there was no immediate link but both initiatives had a common goal:
  1103. Create a sound software development eco-system for Cortex-M based
  1104. Microcontroller, giving the customers the free choice of devices and software
  1105. development environments and all resources required for a successful product
  1106. development in a single location.&nbsp;Meanwhile we have started to generate
  1107. CMSIS compliant device header files from the same CMSIS-SVD description. We will
  1108. introduce a small number of additional description tags in the next version of
  1109. the specification. The benefit is the synchronization between symbols used in
  1110. the application and the symbols displayed by the debugger.&nbsp; </p>
  1111. <h3>Why does the format not provide constructs like macros and
  1112. conditional statements?</h3>
  1113. <p>It is assumed that the description is generated from other sources and
  1114. therefore such concepts would only complicate the language unnecessarily. It is
  1115. recommended to use a standard C pre-processor to generate the debug description
  1116. format from a redundancy optimized description.</p>
  1117. <h3>Do we need to consider endianess in the description?</h3>
  1118. <p>This should be specified on a device configuration level and is not specific
  1119. to the visualization of peripheral details in a System View. Endianess becomes
  1120. relevant when using bit fields in the CMSIS compliant device header file.</p>
  1121. <h3>Is the System View Description limited to Cortex-M based devices ?</h3>
  1122. <p>There may have been assumptions made about the structure of the device due to
  1123. it being developed around a Cortex-M processor. E.g. that all peripherals are
  1124. assumed to be memory mapped and to reside in a single address space. It is quite
  1125. likely that the description format may also serve other architectures
  1126. sufficiently. There is no intent to limit the format to Cortex-M
  1127. processor based devices. </p>
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