stm32f2xx_adc.c 65 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f2xx_adc.c
  4. * @author MCD Application Team
  5. * @version V1.0.0
  6. * @date 18-April-2011
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the Analog to Digital Convertor (ADC) peripheral:
  9. * - Initialization and Configuration (in addition to ADC multi mode
  10. * selection)
  11. * - Analog Watchdog configuration
  12. * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
  13. * management
  14. * - Regular Channels Configuration
  15. * - Regular Channels DMA Configuration
  16. * - Injected channels Configuration
  17. * - Interrupts and flags management
  18. *
  19. * @verbatim
  20. *
  21. * ===================================================================
  22. * How to use this driver
  23. * ===================================================================
  24. * 1. Enable the ADC interface clock using
  25. * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
  26. *
  27. * 2. ADC pins configuration
  28. * - Enable the clock for the ADC GPIOs using the following function:
  29. * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
  30. * - Configure these ADC pins in analog mode using GPIO_Init();
  31. *
  32. * 3. Configure the ADC Prescaler, conversion resolution and data
  33. * alignment using the ADC_Init() function.
  34. * 4. Activate the ADC peripheral using ADC_Cmd() function.
  35. *
  36. * Regular channels group configuration
  37. * ====================================
  38. * - To configure the ADC regular channels group features, use
  39. * ADC_Init() and ADC_RegularChannelConfig() functions.
  40. * - To activate the continuous mode, use the ADC_continuousModeCmd()
  41. * function.
  42. * - To configurate and activate the Discontinuous mode, use the
  43. * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
  44. * - To read the ADC converted values, use the ADC_GetConversionValue()
  45. * function.
  46. *
  47. * Multi mode ADCs Regular channels configuration
  48. * ===============================================
  49. * - Refer to "Regular channels group configuration" description to
  50. * configure the ADC1, ADC2 and ADC3 regular channels.
  51. * - Select the Multi mode ADC regular channels features (dual or
  52. * triple mode) using ADC_CommonInit() function and configure
  53. * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
  54. * functions.
  55. * - Read the ADCs converted values using the
  56. * ADC_GetMultiModeConversionValue() function.
  57. *
  58. * DMA for Regular channels group features configuration
  59. * ======================================================
  60. * - To enable the DMA mode for regular channels group, use the
  61. * ADC_DMACmd() function.
  62. * - To enable the generation of DMA requests continuously at the end
  63. * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
  64. * function.
  65. *
  66. * Injected channels group configuration
  67. * =====================================
  68. * - To configure the ADC Injected channels group features, use
  69. * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
  70. * functions.
  71. * - To activate the continuous mode, use the ADC_continuousModeCmd()
  72. * function.
  73. * - To activate the Injected Discontinuous mode, use the
  74. * ADC_InjectedDiscModeCmd() function.
  75. * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
  76. * function.
  77. * - To read the ADC converted values, use the ADC_GetInjectedConversionValue()
  78. * function.
  79. *
  80. * @endverbatim
  81. *
  82. ******************************************************************************
  83. * @attention
  84. *
  85. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  86. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  87. * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  88. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  89. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  90. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  91. *
  92. * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  93. ******************************************************************************
  94. */
  95. /* Includes ------------------------------------------------------------------*/
  96. #include "stm32f2xx_adc.h"
  97. #include "stm32f2xx_rcc.h"
  98. /** @addtogroup STM32F2xx_StdPeriph_Driver
  99. * @{
  100. */
  101. /** @defgroup ADC
  102. * @brief ADC driver modules
  103. * @{
  104. */
  105. /* Private typedef -----------------------------------------------------------*/
  106. /* Private define ------------------------------------------------------------*/
  107. /* ADC DISCNUM mask */
  108. #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
  109. /* ADC AWDCH mask */
  110. #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
  111. /* ADC Analog watchdog enable mode mask */
  112. #define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
  113. /* CR1 register Mask */
  114. #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
  115. /* ADC EXTEN mask */
  116. #define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
  117. /* ADC JEXTEN mask */
  118. #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
  119. /* ADC JEXTSEL mask */
  120. #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
  121. /* CR2 register Mask */
  122. #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
  123. /* ADC SQx mask */
  124. #define SQR3_SQ_SET ((uint32_t)0x0000001F)
  125. #define SQR2_SQ_SET ((uint32_t)0x0000001F)
  126. #define SQR1_SQ_SET ((uint32_t)0x0000001F)
  127. /* ADC L Mask */
  128. #define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
  129. /* ADC JSQx mask */
  130. #define JSQR_JSQ_SET ((uint32_t)0x0000001F)
  131. /* ADC JL mask */
  132. #define JSQR_JL_SET ((uint32_t)0x00300000)
  133. #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
  134. /* ADC SMPx mask */
  135. #define SMPR1_SMP_SET ((uint32_t)0x00000007)
  136. #define SMPR2_SMP_SET ((uint32_t)0x00000007)
  137. /* ADC JDRx registers offset */
  138. #define JDR_OFFSET ((uint8_t)0x28)
  139. /* ADC CDR register base address */
  140. #define CDR_ADDRESS ((uint32_t)0x40012308)
  141. /* ADC CCR register Mask */
  142. #define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
  143. /* Private macro -------------------------------------------------------------*/
  144. /* Private variables ---------------------------------------------------------*/
  145. /* Private function prototypes -----------------------------------------------*/
  146. /* Private functions ---------------------------------------------------------*/
  147. /** @defgroup ADC_Private_Functions
  148. * @{
  149. */
  150. /** @defgroup ADC_Group1 Initialization and Configuration functions
  151. * @brief Initialization and Configuration functions
  152. *
  153. @verbatim
  154. ===============================================================================
  155. Initialization and Configuration functions
  156. ===============================================================================
  157. This section provides functions allowing to:
  158. - Initialize and configure the ADC Prescaler
  159. - ADC Conversion Resolution (12bit..6bit)
  160. - Scan Conversion Mode (multichannels or one channel) for regular group
  161. - ADC Continuous Conversion Mode (Continuous or Single conversion) for
  162. regular group
  163. - External trigger Edge and source of regular group,
  164. - Converted data alignment (left or right)
  165. - The number of ADC conversions that will be done using the sequencer for
  166. regular channel group
  167. - Multi ADC mode selection
  168. - Direct memory access mode selection for multi ADC mode
  169. - Delay between 2 sampling phases (used in dual or triple interleaved modes)
  170. - Enable or disable the ADC peripheral
  171. @endverbatim
  172. * @{
  173. */
  174. /**
  175. * @brief Deinitializes all ADCs peripherals registers to their default reset
  176. * values.
  177. * @param None
  178. * @retval None
  179. */
  180. void ADC_DeInit(void)
  181. {
  182. /* Enable all ADCs reset state */
  183. RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
  184. /* Release all ADCs from reset state */
  185. RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
  186. }
  187. /**
  188. * @brief Initializes the ADCx peripheral according to the specified parameters
  189. * in the ADC_InitStruct.
  190. * @note This function is used to configure the global features of the ADC (
  191. * Resolution and Data Alignment), however, the rest of the configuration
  192. * parameters are specific to the regular channels group (scan mode
  193. * activation, continuous mode activation, External trigger source and
  194. * edge, number of conversion in the regular channels group sequencer).
  195. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  196. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
  197. * the configuration information for the specified ADC peripheral.
  198. * @retval None
  199. */
  200. void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
  201. {
  202. uint32_t tmpreg1 = 0;
  203. uint8_t tmpreg2 = 0;
  204. /* Check the parameters */
  205. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  206. assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
  207. assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
  208. assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
  209. assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
  210. assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
  211. assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
  212. assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
  213. /*---------------------------- ADCx CR1 Configuration -----------------*/
  214. /* Get the ADCx CR1 value */
  215. tmpreg1 = ADCx->CR1;
  216. /* Clear RES and SCAN bits */
  217. tmpreg1 &= CR1_CLEAR_MASK;
  218. /* Configure ADCx: scan conversion mode and resolution */
  219. /* Set SCAN bit according to ADC_ScanConvMode value */
  220. /* Set RES bit according to ADC_Resolution value */
  221. tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
  222. ADC_InitStruct->ADC_Resolution);
  223. /* Write to ADCx CR1 */
  224. ADCx->CR1 = tmpreg1;
  225. /*---------------------------- ADCx CR2 Configuration -----------------*/
  226. /* Get the ADCx CR2 value */
  227. tmpreg1 = ADCx->CR2;
  228. /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
  229. tmpreg1 &= CR2_CLEAR_MASK;
  230. /* Configure ADCx: external trigger event and edge, data alignment and
  231. continuous conversion mode */
  232. /* Set ALIGN bit according to ADC_DataAlign value */
  233. /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
  234. /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
  235. /* Set CONT bit according to ADC_ContinuousConvMode value */
  236. tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
  237. ADC_InitStruct->ADC_ExternalTrigConv |
  238. ADC_InitStruct->ADC_ExternalTrigConvEdge | \
  239. ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
  240. /* Write to ADCx CR2 */
  241. ADCx->CR2 = tmpreg1;
  242. /*---------------------------- ADCx SQR1 Configuration -----------------*/
  243. /* Get the ADCx SQR1 value */
  244. tmpreg1 = ADCx->SQR1;
  245. /* Clear L bits */
  246. tmpreg1 &= SQR1_L_RESET;
  247. /* Configure ADCx: regular channel sequence length */
  248. /* Set L bits according to ADC_NbrOfConversion value */
  249. tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
  250. tmpreg1 |= ((uint32_t)tmpreg2 << 20);
  251. /* Write to ADCx SQR1 */
  252. ADCx->SQR1 = tmpreg1;
  253. }
  254. /**
  255. * @brief Fills each ADC_InitStruct member with its default value.
  256. * @note This function is used to initialize the global features of the ADC (
  257. * Resolution and Data Alignment), however, the rest of the configuration
  258. * parameters are specific to the regular channels group (scan mode
  259. * activation, continuous mode activation, External trigger source and
  260. * edge, number of conversion in the regular channels group sequencer).
  261. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
  262. * be initialized.
  263. * @retval None
  264. */
  265. void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
  266. {
  267. /* Initialize the ADC_Mode member */
  268. ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
  269. /* initialize the ADC_ScanConvMode member */
  270. ADC_InitStruct->ADC_ScanConvMode = DISABLE;
  271. /* Initialize the ADC_ContinuousConvMode member */
  272. ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
  273. /* Initialize the ADC_ExternalTrigConvEdge member */
  274. ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
  275. /* Initialize the ADC_ExternalTrigConv member */
  276. ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
  277. /* Initialize the ADC_DataAlign member */
  278. ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
  279. /* Initialize the ADC_NbrOfConversion member */
  280. ADC_InitStruct->ADC_NbrOfConversion = 1;
  281. }
  282. /**
  283. * @brief Initializes the ADCs peripherals according to the specified parameters
  284. * in the ADC_CommonInitStruct.
  285. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
  286. * that contains the configuration information for All ADCs peripherals.
  287. * @retval None
  288. */
  289. void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
  290. {
  291. uint32_t tmpreg1 = 0;
  292. /* Check the parameters */
  293. assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
  294. assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
  295. assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
  296. assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
  297. /*---------------------------- ADC CCR Configuration -----------------*/
  298. /* Get the ADC CCR value */
  299. tmpreg1 = ADC->CCR;
  300. /* Clear MULTI, DELAY, DMA and ADCPRE bits */
  301. tmpreg1 &= CR_CLEAR_MASK;
  302. /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
  303. and DMA access mode for multimode */
  304. /* Set MULTI bits according to ADC_Mode value */
  305. /* Set ADCPRE bits according to ADC_Prescaler value */
  306. /* Set DMA bits according to ADC_DMAAccessMode value */
  307. /* Set DELAY bits according to ADC_TwoSamplingDelay value */
  308. tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
  309. ADC_CommonInitStruct->ADC_Prescaler |
  310. ADC_CommonInitStruct->ADC_DMAAccessMode |
  311. ADC_CommonInitStruct->ADC_TwoSamplingDelay);
  312. /* Write to ADC CCR */
  313. ADC->CCR = tmpreg1;
  314. }
  315. /**
  316. * @brief Fills each ADC_CommonInitStruct member with its default value.
  317. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
  318. * which will be initialized.
  319. * @retval None
  320. */
  321. void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
  322. {
  323. /* Initialize the ADC_Mode member */
  324. ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
  325. /* initialize the ADC_Prescaler member */
  326. ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
  327. /* Initialize the ADC_DMAAccessMode member */
  328. ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
  329. /* Initialize the ADC_TwoSamplingDelay member */
  330. ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
  331. }
  332. /**
  333. * @brief Enables or disables the specified ADC peripheral.
  334. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  335. * @param NewState: new state of the ADCx peripheral.
  336. * This parameter can be: ENABLE or DISABLE.
  337. * @retval None
  338. */
  339. void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  340. {
  341. /* Check the parameters */
  342. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  343. assert_param(IS_FUNCTIONAL_STATE(NewState));
  344. if (NewState != DISABLE)
  345. {
  346. /* Set the ADON bit to wake up the ADC from power down mode */
  347. ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
  348. }
  349. else
  350. {
  351. /* Disable the selected ADC peripheral */
  352. ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
  353. }
  354. }
  355. /**
  356. * @}
  357. */
  358. /** @defgroup ADC_Group2 Analog Watchdog configuration functions
  359. * @brief Analog Watchdog configuration functions
  360. *
  361. @verbatim
  362. ===============================================================================
  363. Analog Watchdog configuration functions
  364. ===============================================================================
  365. This section provides functions allowing to configure the Analog Watchdog
  366. (AWD) feature in the ADC.
  367. A typical configuration Analog Watchdog is done following these steps :
  368. 1. the ADC guarded channel(s) is (are) selected using the
  369. ADC_AnalogWatchdogSingleChannelConfig() function.
  370. 2. The Analog watchdog lower and higher threshold are configured using the
  371. ADC_AnalogWatchdogThresholdsConfig() function.
  372. 3. The Analog watchdog is enabled and configured to enable the check, on one
  373. or more channels, using the ADC_AnalogWatchdogCmd() function.
  374. @endverbatim
  375. * @{
  376. */
  377. /**
  378. * @brief Enables or disables the analog watchdog on single/all regular or
  379. * injected channels
  380. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  381. * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
  382. * This parameter can be one of the following values:
  383. * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
  384. * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
  385. * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
  386. * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
  387. * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
  388. * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
  389. * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
  390. * @retval None
  391. */
  392. void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
  393. {
  394. uint32_t tmpreg = 0;
  395. /* Check the parameters */
  396. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  397. assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
  398. /* Get the old register value */
  399. tmpreg = ADCx->CR1;
  400. /* Clear AWDEN, JAWDEN and AWDSGL bits */
  401. tmpreg &= CR1_AWDMode_RESET;
  402. /* Set the analog watchdog enable mode */
  403. tmpreg |= ADC_AnalogWatchdog;
  404. /* Store the new register value */
  405. ADCx->CR1 = tmpreg;
  406. }
  407. /**
  408. * @brief Configures the high and low thresholds of the analog watchdog.
  409. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  410. * @param HighThreshold: the ADC analog watchdog High threshold value.
  411. * This parameter must be a 12-bit value.
  412. * @param LowThreshold: the ADC analog watchdog Low threshold value.
  413. * This parameter must be a 12-bit value.
  414. * @retval None
  415. */
  416. void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
  417. uint16_t LowThreshold)
  418. {
  419. /* Check the parameters */
  420. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  421. assert_param(IS_ADC_THRESHOLD(HighThreshold));
  422. assert_param(IS_ADC_THRESHOLD(LowThreshold));
  423. /* Set the ADCx high threshold */
  424. ADCx->HTR = HighThreshold;
  425. /* Set the ADCx low threshold */
  426. ADCx->LTR = LowThreshold;
  427. }
  428. /**
  429. * @brief Configures the analog watchdog guarded single channel
  430. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  431. * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
  432. * This parameter can be one of the following values:
  433. * @arg ADC_Channel_0: ADC Channel0 selected
  434. * @arg ADC_Channel_1: ADC Channel1 selected
  435. * @arg ADC_Channel_2: ADC Channel2 selected
  436. * @arg ADC_Channel_3: ADC Channel3 selected
  437. * @arg ADC_Channel_4: ADC Channel4 selected
  438. * @arg ADC_Channel_5: ADC Channel5 selected
  439. * @arg ADC_Channel_6: ADC Channel6 selected
  440. * @arg ADC_Channel_7: ADC Channel7 selected
  441. * @arg ADC_Channel_8: ADC Channel8 selected
  442. * @arg ADC_Channel_9: ADC Channel9 selected
  443. * @arg ADC_Channel_10: ADC Channel10 selected
  444. * @arg ADC_Channel_11: ADC Channel11 selected
  445. * @arg ADC_Channel_12: ADC Channel12 selected
  446. * @arg ADC_Channel_13: ADC Channel13 selected
  447. * @arg ADC_Channel_14: ADC Channel14 selected
  448. * @arg ADC_Channel_15: ADC Channel15 selected
  449. * @arg ADC_Channel_16: ADC Channel16 selected
  450. * @arg ADC_Channel_17: ADC Channel17 selected
  451. * @arg ADC_Channel_18: ADC Channel18 selected
  452. * @retval None
  453. */
  454. void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
  455. {
  456. uint32_t tmpreg = 0;
  457. /* Check the parameters */
  458. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  459. assert_param(IS_ADC_CHANNEL(ADC_Channel));
  460. /* Get the old register value */
  461. tmpreg = ADCx->CR1;
  462. /* Clear the Analog watchdog channel select bits */
  463. tmpreg &= CR1_AWDCH_RESET;
  464. /* Set the Analog watchdog channel */
  465. tmpreg |= ADC_Channel;
  466. /* Store the new register value */
  467. ADCx->CR1 = tmpreg;
  468. }
  469. /**
  470. * @}
  471. */
  472. /** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
  473. * and VBAT (Voltage BATtery) management functions
  474. * @brief Temperature Sensor, Vrefint and VBAT management functions
  475. *
  476. @verbatim
  477. ===============================================================================
  478. Temperature Sensor, Vrefint and VBAT management functions
  479. ===============================================================================
  480. This section provides functions allowing to enable/ disable the internal
  481. connections between the ADC and the Temperature Sensor, the Vrefint and the
  482. Vbat sources.
  483. A typical configuration to get the Temperature sensor and Vrefint channels
  484. voltages is done following these steps :
  485. 1. Enable the internal connection of Temperature sensor and Vrefint sources
  486. with the ADC channels using ADC_TempSensorVrefintCmd() function.
  487. 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
  488. ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
  489. 3. Get the voltage values, using ADC_GetConversionValue() or
  490. ADC_GetInjectedConversionValue().
  491. A typical configuration to get the VBAT channel voltage is done following
  492. these steps :
  493. 1. Enable the internal connection of VBAT source with the ADC channel using
  494. ADC_VBATCmd() function.
  495. 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
  496. ADC_InjectedChannelConfig() functions
  497. 3. Get the voltage value, using ADC_GetConversionValue() or
  498. ADC_GetInjectedConversionValue().
  499. @endverbatim
  500. * @{
  501. */
  502. /**
  503. * @brief Enables or disables the temperature sensor and Vrefint channels.
  504. * @param NewState: new state of the temperature sensor and Vrefint channels.
  505. * This parameter can be: ENABLE or DISABLE.
  506. * @retval None
  507. */
  508. void ADC_TempSensorVrefintCmd(FunctionalState NewState)
  509. {
  510. /* Check the parameters */
  511. assert_param(IS_FUNCTIONAL_STATE(NewState));
  512. if (NewState != DISABLE)
  513. {
  514. /* Enable the temperature sensor and Vrefint channel*/
  515. ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
  516. }
  517. else
  518. {
  519. /* Disable the temperature sensor and Vrefint channel*/
  520. ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
  521. }
  522. }
  523. /**
  524. * @brief Enables or disables the VBAT (Voltage Battery) channel.
  525. * @param NewState: new state of the VBAT channel.
  526. * This parameter can be: ENABLE or DISABLE.
  527. * @retval None
  528. */
  529. void ADC_VBATCmd(FunctionalState NewState)
  530. {
  531. /* Check the parameters */
  532. assert_param(IS_FUNCTIONAL_STATE(NewState));
  533. if (NewState != DISABLE)
  534. {
  535. /* Enable the VBAT channel*/
  536. ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
  537. }
  538. else
  539. {
  540. /* Disable the VBAT channel*/
  541. ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
  542. }
  543. }
  544. /**
  545. * @}
  546. */
  547. /** @defgroup ADC_Group4 Regular Channels Configuration functions
  548. * @brief Regular Channels Configuration functions
  549. *
  550. @verbatim
  551. ===============================================================================
  552. Regular Channels Configuration functions
  553. ===============================================================================
  554. This section provides functions allowing to manage the ADC's regular channels,
  555. it is composed of 2 sub sections :
  556. 1. Configuration and management functions for regular channels: This subsection
  557. provides functions allowing to configure the ADC regular channels :
  558. - Configure the rank in the regular group sequencer for each channel
  559. - Configure the sampling time for each channel
  560. - select the conversion Trigger for regular channels
  561. - select the desired EOC event behavior configuration
  562. - Activate the continuous Mode (*)
  563. - Activate the Discontinuous Mode
  564. Please Note that the following features for regular channels are configurated
  565. using the ADC_Init() function :
  566. - scan mode activation
  567. - continuous mode activation (**)
  568. - External trigger source
  569. - External trigger edge
  570. - number of conversion in the regular channels group sequencer.
  571. @note (*) and (**) are performing the same configuration
  572. 2. Get the conversion data: This subsection provides an important function in
  573. the ADC peripheral since it returns the converted data of the current
  574. regular channel. When the Conversion value is read, the EOC Flag is
  575. automatically cleared.
  576. @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
  577. results data (in the selected multi mode) can be returned in the same
  578. time using ADC_GetMultiModeConversionValue() function.
  579. @endverbatim
  580. * @{
  581. */
  582. /**
  583. * @brief Configures for the selected ADC regular channel its corresponding
  584. * rank in the sequencer and its sample time.
  585. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  586. * @param ADC_Channel: the ADC channel to configure.
  587. * This parameter can be one of the following values:
  588. * @arg ADC_Channel_0: ADC Channel0 selected
  589. * @arg ADC_Channel_1: ADC Channel1 selected
  590. * @arg ADC_Channel_2: ADC Channel2 selected
  591. * @arg ADC_Channel_3: ADC Channel3 selected
  592. * @arg ADC_Channel_4: ADC Channel4 selected
  593. * @arg ADC_Channel_5: ADC Channel5 selected
  594. * @arg ADC_Channel_6: ADC Channel6 selected
  595. * @arg ADC_Channel_7: ADC Channel7 selected
  596. * @arg ADC_Channel_8: ADC Channel8 selected
  597. * @arg ADC_Channel_9: ADC Channel9 selected
  598. * @arg ADC_Channel_10: ADC Channel10 selected
  599. * @arg ADC_Channel_11: ADC Channel11 selected
  600. * @arg ADC_Channel_12: ADC Channel12 selected
  601. * @arg ADC_Channel_13: ADC Channel13 selected
  602. * @arg ADC_Channel_14: ADC Channel14 selected
  603. * @arg ADC_Channel_15: ADC Channel15 selected
  604. * @arg ADC_Channel_16: ADC Channel16 selected
  605. * @arg ADC_Channel_17: ADC Channel17 selected
  606. * @arg ADC_Channel_18: ADC Channel18 selected
  607. * @param Rank: The rank in the regular group sequencer.
  608. * This parameter must be between 1 to 16.
  609. * @param ADC_SampleTime: The sample time value to be set for the selected channel.
  610. * This parameter can be one of the following values:
  611. * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
  612. * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
  613. * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
  614. * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
  615. * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
  616. * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
  617. * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
  618. * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
  619. * @retval None
  620. */
  621. void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
  622. {
  623. uint32_t tmpreg1 = 0, tmpreg2 = 0;
  624. /* Check the parameters */
  625. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  626. assert_param(IS_ADC_CHANNEL(ADC_Channel));
  627. assert_param(IS_ADC_REGULAR_RANK(Rank));
  628. assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
  629. /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
  630. if (ADC_Channel > ADC_Channel_9)
  631. {
  632. /* Get the old register value */
  633. tmpreg1 = ADCx->SMPR1;
  634. /* Calculate the mask to clear */
  635. tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
  636. /* Clear the old sample time */
  637. tmpreg1 &= ~tmpreg2;
  638. /* Calculate the mask to set */
  639. tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
  640. /* Set the new sample time */
  641. tmpreg1 |= tmpreg2;
  642. /* Store the new register value */
  643. ADCx->SMPR1 = tmpreg1;
  644. }
  645. else /* ADC_Channel include in ADC_Channel_[0..9] */
  646. {
  647. /* Get the old register value */
  648. tmpreg1 = ADCx->SMPR2;
  649. /* Calculate the mask to clear */
  650. tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
  651. /* Clear the old sample time */
  652. tmpreg1 &= ~tmpreg2;
  653. /* Calculate the mask to set */
  654. tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
  655. /* Set the new sample time */
  656. tmpreg1 |= tmpreg2;
  657. /* Store the new register value */
  658. ADCx->SMPR2 = tmpreg1;
  659. }
  660. /* For Rank 1 to 6 */
  661. if (Rank < 7)
  662. {
  663. /* Get the old register value */
  664. tmpreg1 = ADCx->SQR3;
  665. /* Calculate the mask to clear */
  666. tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
  667. /* Clear the old SQx bits for the selected rank */
  668. tmpreg1 &= ~tmpreg2;
  669. /* Calculate the mask to set */
  670. tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
  671. /* Set the SQx bits for the selected rank */
  672. tmpreg1 |= tmpreg2;
  673. /* Store the new register value */
  674. ADCx->SQR3 = tmpreg1;
  675. }
  676. /* For Rank 7 to 12 */
  677. else if (Rank < 13)
  678. {
  679. /* Get the old register value */
  680. tmpreg1 = ADCx->SQR2;
  681. /* Calculate the mask to clear */
  682. tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
  683. /* Clear the old SQx bits for the selected rank */
  684. tmpreg1 &= ~tmpreg2;
  685. /* Calculate the mask to set */
  686. tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
  687. /* Set the SQx bits for the selected rank */
  688. tmpreg1 |= tmpreg2;
  689. /* Store the new register value */
  690. ADCx->SQR2 = tmpreg1;
  691. }
  692. /* For Rank 13 to 16 */
  693. else
  694. {
  695. /* Get the old register value */
  696. tmpreg1 = ADCx->SQR1;
  697. /* Calculate the mask to clear */
  698. tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
  699. /* Clear the old SQx bits for the selected rank */
  700. tmpreg1 &= ~tmpreg2;
  701. /* Calculate the mask to set */
  702. tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
  703. /* Set the SQx bits for the selected rank */
  704. tmpreg1 |= tmpreg2;
  705. /* Store the new register value */
  706. ADCx->SQR1 = tmpreg1;
  707. }
  708. }
  709. /**
  710. * @brief Enables the selected ADC software start conversion of the regular channels.
  711. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  712. * @retval None
  713. */
  714. void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
  715. {
  716. /* Check the parameters */
  717. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  718. /* Enable the selected ADC conversion for regular group */
  719. ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
  720. }
  721. /**
  722. * @brief Gets the selected ADC Software start regular conversion Status.
  723. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  724. * @retval The new state of ADC software start conversion (SET or RESET).
  725. */
  726. FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
  727. {
  728. FlagStatus bitstatus = RESET;
  729. /* Check the parameters */
  730. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  731. /* Check the status of SWSTART bit */
  732. if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
  733. {
  734. /* SWSTART bit is set */
  735. bitstatus = SET;
  736. }
  737. else
  738. {
  739. /* SWSTART bit is reset */
  740. bitstatus = RESET;
  741. }
  742. /* Return the SWSTART bit status */
  743. return bitstatus;
  744. }
  745. /**
  746. * @brief Enables or disables the EOC on each regular channel conversion
  747. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  748. * @param NewState: new state of the selected ADC EOC flag rising
  749. * This parameter can be: ENABLE or DISABLE.
  750. * @retval None
  751. */
  752. void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  753. {
  754. /* Check the parameters */
  755. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  756. assert_param(IS_FUNCTIONAL_STATE(NewState));
  757. if (NewState != DISABLE)
  758. {
  759. /* Enable the selected ADC EOC rising on each regular channel conversion */
  760. ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
  761. }
  762. else
  763. {
  764. /* Disable the selected ADC EOC rising on each regular channel conversion */
  765. ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
  766. }
  767. }
  768. /**
  769. * @brief Enables or disables the ADC continuous conversion mode
  770. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  771. * @param NewState: new state of the selected ADC continuous conversion mode
  772. * This parameter can be: ENABLE or DISABLE.
  773. * @retval None
  774. */
  775. void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  776. {
  777. /* Check the parameters */
  778. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  779. assert_param(IS_FUNCTIONAL_STATE(NewState));
  780. if (NewState != DISABLE)
  781. {
  782. /* Enable the selected ADC continuous conversion mode */
  783. ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
  784. }
  785. else
  786. {
  787. /* Disable the selected ADC continuous conversion mode */
  788. ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
  789. }
  790. }
  791. /**
  792. * @brief Configures the discontinuous mode for the selected ADC regular group
  793. * channel.
  794. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  795. * @param Number: specifies the discontinuous mode regular channel count value.
  796. * This number must be between 1 and 8.
  797. * @retval None
  798. */
  799. void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
  800. {
  801. uint32_t tmpreg1 = 0;
  802. uint32_t tmpreg2 = 0;
  803. /* Check the parameters */
  804. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  805. assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
  806. /* Get the old register value */
  807. tmpreg1 = ADCx->CR1;
  808. /* Clear the old discontinuous mode channel count */
  809. tmpreg1 &= CR1_DISCNUM_RESET;
  810. /* Set the discontinuous mode channel count */
  811. tmpreg2 = Number - 1;
  812. tmpreg1 |= tmpreg2 << 13;
  813. /* Store the new register value */
  814. ADCx->CR1 = tmpreg1;
  815. }
  816. /**
  817. * @brief Enables or disables the discontinuous mode on regular group channel
  818. * for the specified ADC
  819. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  820. * @param NewState: new state of the selected ADC discontinuous mode on
  821. * regular group channel.
  822. * This parameter can be: ENABLE or DISABLE.
  823. * @retval None
  824. */
  825. void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  826. {
  827. /* Check the parameters */
  828. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  829. assert_param(IS_FUNCTIONAL_STATE(NewState));
  830. if (NewState != DISABLE)
  831. {
  832. /* Enable the selected ADC regular discontinuous mode */
  833. ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
  834. }
  835. else
  836. {
  837. /* Disable the selected ADC regular discontinuous mode */
  838. ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
  839. }
  840. }
  841. /**
  842. * @brief Returns the last ADCx conversion result data for regular channel.
  843. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  844. * @retval The Data conversion value.
  845. */
  846. uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
  847. {
  848. /* Check the parameters */
  849. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  850. /* Return the selected ADC conversion value */
  851. return (uint16_t) ADCx->DR;
  852. }
  853. /**
  854. * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
  855. * data in the selected multi mode.
  856. * @param None
  857. * @retval The Data conversion value.
  858. * @note In dual mode, the value returned by this function is as following
  859. * Data[15:0] : these bits contain the regular data of ADC1.
  860. * Data[31:16]: these bits contain the regular data of ADC2.
  861. * @note In triple mode, the value returned by this function is as following
  862. * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
  863. * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
  864. */
  865. uint32_t ADC_GetMultiModeConversionValue(void)
  866. {
  867. /* Return the multi mode conversion value */
  868. return (*(__IO uint32_t *) CDR_ADDRESS);
  869. }
  870. /**
  871. * @}
  872. */
  873. /** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
  874. * @brief Regular Channels DMA Configuration functions
  875. *
  876. @verbatim
  877. ===============================================================================
  878. Regular Channels DMA Configuration functions
  879. ===============================================================================
  880. This section provides functions allowing to configure the DMA for ADC regular
  881. channels.
  882. Since converted regular channel values are stored into a unique data register,
  883. it is useful to use DMA for conversion of more than one regular channel. This
  884. avoids the loss of the data already stored in the ADC Data register.
  885. When the DMA mode is enabled (using the ADC_DMACmd() function), after each
  886. conversion of a regular channel, a DMA request is generated.
  887. Depending on the "DMA disable selection for Independent ADC mode"
  888. configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
  889. at the end of the last DMA transfer, two possibilities are allowed:
  890. - No new DMA request is issued to the DMA controller (feature DISABLED)
  891. - Requests can continue to be generated (feature ENABLED).
  892. Depending on the "DMA disable selection for multi ADC mode" configuration
  893. (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
  894. at the end of the last DMA transfer, two possibilities are allowed:
  895. - No new DMA request is issued to the DMA controller (feature DISABLED)
  896. - Requests can continue to be generated (feature ENABLED).
  897. @endverbatim
  898. * @{
  899. */
  900. /**
  901. * @brief Enables or disables the specified ADC DMA request.
  902. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  903. * @param NewState: new state of the selected ADC DMA transfer.
  904. * This parameter can be: ENABLE or DISABLE.
  905. * @retval None
  906. */
  907. void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  908. {
  909. /* Check the parameters */
  910. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  911. assert_param(IS_FUNCTIONAL_STATE(NewState));
  912. if (NewState != DISABLE)
  913. {
  914. /* Enable the selected ADC DMA request */
  915. ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
  916. }
  917. else
  918. {
  919. /* Disable the selected ADC DMA request */
  920. ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
  921. }
  922. }
  923. /**
  924. * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
  925. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  926. * @param NewState: new state of the selected ADC DMA request after last transfer.
  927. * This parameter can be: ENABLE or DISABLE.
  928. * @retval None
  929. */
  930. void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  931. {
  932. /* Check the parameters */
  933. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  934. assert_param(IS_FUNCTIONAL_STATE(NewState));
  935. if (NewState != DISABLE)
  936. {
  937. /* Enable the selected ADC DMA request after last transfer */
  938. ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
  939. }
  940. else
  941. {
  942. /* Disable the selected ADC DMA request after last transfer */
  943. ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
  944. }
  945. }
  946. /**
  947. * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
  948. * @param NewState: new state of the selected ADC DMA request after last transfer.
  949. * This parameter can be: ENABLE or DISABLE.
  950. * @note if Enabled, DMA requests are issued as long as data are converted and
  951. * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
  952. * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
  953. * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
  954. * @retval None
  955. */
  956. void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
  957. {
  958. /* Check the parameters */
  959. assert_param(IS_FUNCTIONAL_STATE(NewState));
  960. if (NewState != DISABLE)
  961. {
  962. /* Enable the selected ADC DMA request after last transfer */
  963. ADC->CCR |= (uint32_t)ADC_CCR_DDS;
  964. }
  965. else
  966. {
  967. /* Disable the selected ADC DMA request after last transfer */
  968. ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
  969. }
  970. }
  971. /**
  972. * @}
  973. */
  974. /** @defgroup ADC_Group6 Injected channels Configuration functions
  975. * @brief Injected channels Configuration functions
  976. *
  977. @verbatim
  978. ===============================================================================
  979. Injected channels Configuration functions
  980. ===============================================================================
  981. This section provide functions allowing to configure the ADC Injected channels,
  982. it is composed of 2 sub sections :
  983. 1. Configuration functions for Injected channels: This subsection provides
  984. functions allowing to configure the ADC injected channels :
  985. - Configure the rank in the injected group sequencer for each channel
  986. - Configure the sampling time for each channel
  987. - Activate the Auto injected Mode
  988. - Activate the Discontinuous Mode
  989. - scan mode activation
  990. - External/software trigger source
  991. - External trigger edge
  992. - injected channels sequencer.
  993. 2. Get the Specified Injected channel conversion data: This subsection
  994. provides an important function in the ADC peripheral since it returns the
  995. converted data of the specific injected channel.
  996. @endverbatim
  997. * @{
  998. */
  999. /**
  1000. * @brief Configures for the selected ADC injected channel its corresponding
  1001. * rank in the sequencer and its sample time.
  1002. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1003. * @param ADC_Channel: the ADC channel to configure.
  1004. * This parameter can be one of the following values:
  1005. * @arg ADC_Channel_0: ADC Channel0 selected
  1006. * @arg ADC_Channel_1: ADC Channel1 selected
  1007. * @arg ADC_Channel_2: ADC Channel2 selected
  1008. * @arg ADC_Channel_3: ADC Channel3 selected
  1009. * @arg ADC_Channel_4: ADC Channel4 selected
  1010. * @arg ADC_Channel_5: ADC Channel5 selected
  1011. * @arg ADC_Channel_6: ADC Channel6 selected
  1012. * @arg ADC_Channel_7: ADC Channel7 selected
  1013. * @arg ADC_Channel_8: ADC Channel8 selected
  1014. * @arg ADC_Channel_9: ADC Channel9 selected
  1015. * @arg ADC_Channel_10: ADC Channel10 selected
  1016. * @arg ADC_Channel_11: ADC Channel11 selected
  1017. * @arg ADC_Channel_12: ADC Channel12 selected
  1018. * @arg ADC_Channel_13: ADC Channel13 selected
  1019. * @arg ADC_Channel_14: ADC Channel14 selected
  1020. * @arg ADC_Channel_15: ADC Channel15 selected
  1021. * @arg ADC_Channel_16: ADC Channel16 selected
  1022. * @arg ADC_Channel_17: ADC Channel17 selected
  1023. * @arg ADC_Channel_18: ADC Channel18 selected
  1024. * @param Rank: The rank in the injected group sequencer.
  1025. * This parameter must be between 1 to 4.
  1026. * @param ADC_SampleTime: The sample time value to be set for the selected channel.
  1027. * This parameter can be one of the following values:
  1028. * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
  1029. * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
  1030. * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
  1031. * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
  1032. * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
  1033. * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
  1034. * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
  1035. * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
  1036. * @retval None
  1037. */
  1038. void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
  1039. {
  1040. uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
  1041. /* Check the parameters */
  1042. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1043. assert_param(IS_ADC_CHANNEL(ADC_Channel));
  1044. assert_param(IS_ADC_INJECTED_RANK(Rank));
  1045. assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
  1046. /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
  1047. if (ADC_Channel > ADC_Channel_9)
  1048. {
  1049. /* Get the old register value */
  1050. tmpreg1 = ADCx->SMPR1;
  1051. /* Calculate the mask to clear */
  1052. tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
  1053. /* Clear the old sample time */
  1054. tmpreg1 &= ~tmpreg2;
  1055. /* Calculate the mask to set */
  1056. tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
  1057. /* Set the new sample time */
  1058. tmpreg1 |= tmpreg2;
  1059. /* Store the new register value */
  1060. ADCx->SMPR1 = tmpreg1;
  1061. }
  1062. else /* ADC_Channel include in ADC_Channel_[0..9] */
  1063. {
  1064. /* Get the old register value */
  1065. tmpreg1 = ADCx->SMPR2;
  1066. /* Calculate the mask to clear */
  1067. tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
  1068. /* Clear the old sample time */
  1069. tmpreg1 &= ~tmpreg2;
  1070. /* Calculate the mask to set */
  1071. tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
  1072. /* Set the new sample time */
  1073. tmpreg1 |= tmpreg2;
  1074. /* Store the new register value */
  1075. ADCx->SMPR2 = tmpreg1;
  1076. }
  1077. /* Rank configuration */
  1078. /* Get the old register value */
  1079. tmpreg1 = ADCx->JSQR;
  1080. /* Get JL value: Number = JL+1 */
  1081. tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
  1082. /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
  1083. tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
  1084. /* Clear the old JSQx bits for the selected rank */
  1085. tmpreg1 &= ~tmpreg2;
  1086. /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
  1087. tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
  1088. /* Set the JSQx bits for the selected rank */
  1089. tmpreg1 |= tmpreg2;
  1090. /* Store the new register value */
  1091. ADCx->JSQR = tmpreg1;
  1092. }
  1093. /**
  1094. * @brief Configures the sequencer length for injected channels
  1095. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1096. * @param Length: The sequencer length.
  1097. * This parameter must be a number between 1 to 4.
  1098. * @retval None
  1099. */
  1100. void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
  1101. {
  1102. uint32_t tmpreg1 = 0;
  1103. uint32_t tmpreg2 = 0;
  1104. /* Check the parameters */
  1105. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1106. assert_param(IS_ADC_INJECTED_LENGTH(Length));
  1107. /* Get the old register value */
  1108. tmpreg1 = ADCx->JSQR;
  1109. /* Clear the old injected sequence length JL bits */
  1110. tmpreg1 &= JSQR_JL_RESET;
  1111. /* Set the injected sequence length JL bits */
  1112. tmpreg2 = Length - 1;
  1113. tmpreg1 |= tmpreg2 << 20;
  1114. /* Store the new register value */
  1115. ADCx->JSQR = tmpreg1;
  1116. }
  1117. /**
  1118. * @brief Set the injected channels conversion value offset
  1119. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1120. * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
  1121. * This parameter can be one of the following values:
  1122. * @arg ADC_InjectedChannel_1: Injected Channel1 selected
  1123. * @arg ADC_InjectedChannel_2: Injected Channel2 selected
  1124. * @arg ADC_InjectedChannel_3: Injected Channel3 selected
  1125. * @arg ADC_InjectedChannel_4: Injected Channel4 selected
  1126. * @param Offset: the offset value for the selected ADC injected channel
  1127. * This parameter must be a 12bit value.
  1128. * @retval None
  1129. */
  1130. void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
  1131. {
  1132. __IO uint32_t tmp = 0;
  1133. /* Check the parameters */
  1134. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1135. assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
  1136. assert_param(IS_ADC_OFFSET(Offset));
  1137. tmp = (uint32_t)ADCx;
  1138. tmp += ADC_InjectedChannel;
  1139. /* Set the selected injected channel data offset */
  1140. *(__IO uint32_t *) tmp = (uint32_t)Offset;
  1141. }
  1142. /**
  1143. * @brief Configures the ADCx external trigger for injected channels conversion.
  1144. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1145. * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
  1146. * This parameter can be one of the following values:
  1147. * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
  1148. * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
  1149. * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
  1150. * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
  1151. * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
  1152. * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
  1153. * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
  1154. * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
  1155. * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
  1156. * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
  1157. * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
  1158. * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
  1159. * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
  1160. * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
  1161. * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
  1162. * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
  1163. * @retval None
  1164. */
  1165. void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
  1166. {
  1167. uint32_t tmpreg = 0;
  1168. /* Check the parameters */
  1169. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1170. assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
  1171. /* Get the old register value */
  1172. tmpreg = ADCx->CR2;
  1173. /* Clear the old external event selection for injected group */
  1174. tmpreg &= CR2_JEXTSEL_RESET;
  1175. /* Set the external event selection for injected group */
  1176. tmpreg |= ADC_ExternalTrigInjecConv;
  1177. /* Store the new register value */
  1178. ADCx->CR2 = tmpreg;
  1179. }
  1180. /**
  1181. * @brief Configures the ADCx external trigger edge for injected channels conversion.
  1182. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1183. * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
  1184. * to start injected conversion.
  1185. * This parameter can be one of the following values:
  1186. * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
  1187. * injected conversion
  1188. * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
  1189. * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
  1190. * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
  1191. * and falling edge
  1192. * @retval None
  1193. */
  1194. void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
  1195. {
  1196. uint32_t tmpreg = 0;
  1197. /* Check the parameters */
  1198. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1199. assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
  1200. /* Get the old register value */
  1201. tmpreg = ADCx->CR2;
  1202. /* Clear the old external trigger edge for injected group */
  1203. tmpreg &= CR2_JEXTEN_RESET;
  1204. /* Set the new external trigger edge for injected group */
  1205. tmpreg |= ADC_ExternalTrigInjecConvEdge;
  1206. /* Store the new register value */
  1207. ADCx->CR2 = tmpreg;
  1208. }
  1209. /**
  1210. * @brief Enables the selected ADC software start conversion of the injected channels.
  1211. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1212. * @retval None
  1213. */
  1214. void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
  1215. {
  1216. /* Check the parameters */
  1217. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1218. /* Enable the selected ADC conversion for injected group */
  1219. ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
  1220. }
  1221. /**
  1222. * @brief Gets the selected ADC Software start injected conversion Status.
  1223. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1224. * @retval The new state of ADC software start injected conversion (SET or RESET).
  1225. */
  1226. FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
  1227. {
  1228. FlagStatus bitstatus = RESET;
  1229. /* Check the parameters */
  1230. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1231. /* Check the status of JSWSTART bit */
  1232. if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
  1233. {
  1234. /* JSWSTART bit is set */
  1235. bitstatus = SET;
  1236. }
  1237. else
  1238. {
  1239. /* JSWSTART bit is reset */
  1240. bitstatus = RESET;
  1241. }
  1242. /* Return the JSWSTART bit status */
  1243. return bitstatus;
  1244. }
  1245. /**
  1246. * @brief Enables or disables the selected ADC automatic injected group
  1247. * conversion after regular one.
  1248. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1249. * @param NewState: new state of the selected ADC auto injected conversion
  1250. * This parameter can be: ENABLE or DISABLE.
  1251. * @retval None
  1252. */
  1253. void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  1254. {
  1255. /* Check the parameters */
  1256. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1257. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1258. if (NewState != DISABLE)
  1259. {
  1260. /* Enable the selected ADC automatic injected group conversion */
  1261. ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
  1262. }
  1263. else
  1264. {
  1265. /* Disable the selected ADC automatic injected group conversion */
  1266. ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
  1267. }
  1268. }
  1269. /**
  1270. * @brief Enables or disables the discontinuous mode for injected group
  1271. * channel for the specified ADC
  1272. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1273. * @param NewState: new state of the selected ADC discontinuous mode on injected
  1274. * group channel.
  1275. * This parameter can be: ENABLE or DISABLE.
  1276. * @retval None
  1277. */
  1278. void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  1279. {
  1280. /* Check the parameters */
  1281. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1282. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1283. if (NewState != DISABLE)
  1284. {
  1285. /* Enable the selected ADC injected discontinuous mode */
  1286. ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
  1287. }
  1288. else
  1289. {
  1290. /* Disable the selected ADC injected discontinuous mode */
  1291. ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
  1292. }
  1293. }
  1294. /**
  1295. * @brief Returns the ADC injected channel conversion result
  1296. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1297. * @param ADC_InjectedChannel: the converted ADC injected channel.
  1298. * This parameter can be one of the following values:
  1299. * @arg ADC_InjectedChannel_1: Injected Channel1 selected
  1300. * @arg ADC_InjectedChannel_2: Injected Channel2 selected
  1301. * @arg ADC_InjectedChannel_3: Injected Channel3 selected
  1302. * @arg ADC_InjectedChannel_4: Injected Channel4 selected
  1303. * @retval The Data conversion value.
  1304. */
  1305. uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
  1306. {
  1307. __IO uint32_t tmp = 0;
  1308. /* Check the parameters */
  1309. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1310. assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
  1311. tmp = (uint32_t)ADCx;
  1312. tmp += ADC_InjectedChannel + JDR_OFFSET;
  1313. /* Returns the selected injected channel conversion data value */
  1314. return (uint16_t) (*(__IO uint32_t*) tmp);
  1315. }
  1316. /**
  1317. * @}
  1318. */
  1319. /** @defgroup ADC_Group7 Interrupts and flags management functions
  1320. * @brief Interrupts and flags management functions
  1321. *
  1322. @verbatim
  1323. ===============================================================================
  1324. Interrupts and flags management functions
  1325. ===============================================================================
  1326. This section provides functions allowing to configure the ADC Interrupts and
  1327. to get the status and clear flags and Interrupts pending bits.
  1328. Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into
  1329. 3 groups:
  1330. I. Flags and Interrupts for ADC regular channels
  1331. =================================================
  1332. Flags :
  1333. ----------
  1334. 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost
  1335. 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending
  1336. on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of:
  1337. ==> a regular CHANNEL conversion
  1338. ==> sequence of regular GROUP conversions .
  1339. 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL
  1340. conversion starts.
  1341. Interrupts :
  1342. ------------
  1343. 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event.
  1344. 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of
  1345. conversion event.
  1346. II. Flags and Interrupts for ADC Injected channels
  1347. =================================================
  1348. Flags :
  1349. ----------
  1350. 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at
  1351. the end of injected GROUP conversion
  1352. 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when
  1353. injected GROUP conversion starts.
  1354. Interrupts :
  1355. ------------
  1356. 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of
  1357. conversion event.
  1358. III. General Flags and Interrupts for the ADC
  1359. =================================================
  1360. Flags :
  1361. ----------
  1362. 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
  1363. crosses the programmed thresholds values.
  1364. Interrupts :
  1365. ------------
  1366. 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
  1367. The user should identify which mode will be used in his application to manage
  1368. the ADC controller events: Polling mode or Interrupt mode.
  1369. In the Polling Mode it is advised to use the following functions:
  1370. - ADC_GetFlagStatus() : to check if flags events occur.
  1371. - ADC_ClearFlag() : to clear the flags events.
  1372. In the Interrupt Mode it is advised to use the following functions:
  1373. - ADC_ITConfig() : to enable or disable the interrupt source.
  1374. - ADC_GetITStatus() : to check if Interrupt occurs.
  1375. - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
  1376. (corresponding Flag).
  1377. @endverbatim
  1378. * @{
  1379. */
  1380. /**
  1381. * @brief Enables or disables the specified ADC interrupts.
  1382. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1383. * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
  1384. * This parameter can be one of the following values:
  1385. * @arg ADC_IT_EOC: End of conversion interrupt mask
  1386. * @arg ADC_IT_AWD: Analog watchdog interrupt mask
  1387. * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
  1388. * @arg ADC_IT_OVR: Overrun interrupt enable
  1389. * @param NewState: new state of the specified ADC interrupts.
  1390. * This parameter can be: ENABLE or DISABLE.
  1391. * @retval None
  1392. */
  1393. void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
  1394. {
  1395. uint32_t itmask = 0;
  1396. /* Check the parameters */
  1397. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1398. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1399. assert_param(IS_ADC_IT(ADC_IT));
  1400. /* Get the ADC IT index */
  1401. itmask = (uint8_t)ADC_IT;
  1402. itmask = (uint32_t)0x01 << itmask;
  1403. if (NewState != DISABLE)
  1404. {
  1405. /* Enable the selected ADC interrupts */
  1406. ADCx->CR1 |= itmask;
  1407. }
  1408. else
  1409. {
  1410. /* Disable the selected ADC interrupts */
  1411. ADCx->CR1 &= (~(uint32_t)itmask);
  1412. }
  1413. }
  1414. /**
  1415. * @brief Checks whether the specified ADC flag is set or not.
  1416. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1417. * @param ADC_FLAG: specifies the flag to check.
  1418. * This parameter can be one of the following values:
  1419. * @arg ADC_FLAG_AWD: Analog watchdog flag
  1420. * @arg ADC_FLAG_EOC: End of conversion flag
  1421. * @arg ADC_FLAG_JEOC: End of injected group conversion flag
  1422. * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
  1423. * @arg ADC_FLAG_STRT: Start of regular group conversion flag
  1424. * @arg ADC_FLAG_OVR: Overrun flag
  1425. * @retval The new state of ADC_FLAG (SET or RESET).
  1426. */
  1427. FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
  1428. {
  1429. FlagStatus bitstatus = RESET;
  1430. /* Check the parameters */
  1431. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1432. assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
  1433. /* Check the status of the specified ADC flag */
  1434. if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
  1435. {
  1436. /* ADC_FLAG is set */
  1437. bitstatus = SET;
  1438. }
  1439. else
  1440. {
  1441. /* ADC_FLAG is reset */
  1442. bitstatus = RESET;
  1443. }
  1444. /* Return the ADC_FLAG status */
  1445. return bitstatus;
  1446. }
  1447. /**
  1448. * @brief Clears the ADCx's pending flags.
  1449. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1450. * @param ADC_FLAG: specifies the flag to clear.
  1451. * This parameter can be any combination of the following values:
  1452. * @arg ADC_FLAG_AWD: Analog watchdog flag
  1453. * @arg ADC_FLAG_EOC: End of conversion flag
  1454. * @arg ADC_FLAG_JEOC: End of injected group conversion flag
  1455. * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
  1456. * @arg ADC_FLAG_STRT: Start of regular group conversion flag
  1457. * @arg ADC_FLAG_OVR: Overrun flag
  1458. * @retval None
  1459. */
  1460. void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
  1461. {
  1462. /* Check the parameters */
  1463. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1464. assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
  1465. /* Clear the selected ADC flags */
  1466. ADCx->SR = ~(uint32_t)ADC_FLAG;
  1467. }
  1468. /**
  1469. * @brief Checks whether the specified ADC interrupt has occurred or not.
  1470. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1471. * @param ADC_IT: specifies the ADC interrupt source to check.
  1472. * This parameter can be one of the following values:
  1473. * @arg ADC_IT_EOC: End of conversion interrupt mask
  1474. * @arg ADC_IT_AWD: Analog watchdog interrupt mask
  1475. * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
  1476. * @arg ADC_IT_OVR: Overrun interrupt mask
  1477. * @retval The new state of ADC_IT (SET or RESET).
  1478. */
  1479. ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
  1480. {
  1481. ITStatus bitstatus = RESET;
  1482. uint32_t itmask = 0, enablestatus = 0;
  1483. /* Check the parameters */
  1484. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1485. assert_param(IS_ADC_IT(ADC_IT));
  1486. /* Get the ADC IT index */
  1487. itmask = ADC_IT >> 8;
  1488. /* Get the ADC_IT enable bit status */
  1489. enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
  1490. /* Check the status of the specified ADC interrupt */
  1491. if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
  1492. {
  1493. /* ADC_IT is set */
  1494. bitstatus = SET;
  1495. }
  1496. else
  1497. {
  1498. /* ADC_IT is reset */
  1499. bitstatus = RESET;
  1500. }
  1501. /* Return the ADC_IT status */
  1502. return bitstatus;
  1503. }
  1504. /**
  1505. * @brief Clears the ADCx's interrupt pending bits.
  1506. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1507. * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
  1508. * This parameter can be one of the following values:
  1509. * @arg ADC_IT_EOC: End of conversion interrupt mask
  1510. * @arg ADC_IT_AWD: Analog watchdog interrupt mask
  1511. * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
  1512. * @arg ADC_IT_OVR: Overrun interrupt mask
  1513. * @retval None
  1514. */
  1515. void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
  1516. {
  1517. uint8_t itmask = 0;
  1518. /* Check the parameters */
  1519. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1520. assert_param(IS_ADC_IT(ADC_IT));
  1521. /* Get the ADC IT index */
  1522. itmask = (uint8_t)(ADC_IT >> 8);
  1523. /* Clear the selected ADC interrupt pending bits */
  1524. ADCx->SR = ~(uint32_t)itmask;
  1525. }
  1526. /**
  1527. * @}
  1528. */
  1529. /**
  1530. * @}
  1531. */
  1532. /**
  1533. * @}
  1534. */
  1535. /**
  1536. * @}
  1537. */
  1538. /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/