stm32f4xx_hal_dma.h 38 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_dma.h
  4. * @author MCD Application Team
  5. * @brief Header file of DMA HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  10. *
  11. * Redistribution and use in source and binary forms, with or without modification,
  12. * are permitted provided that the following conditions are met:
  13. * 1. Redistributions of source code must retain the above copyright notice,
  14. * this list of conditions and the following disclaimer.
  15. * 2. Redistributions in binary form must reproduce the above copyright notice,
  16. * this list of conditions and the following disclaimer in the documentation
  17. * and/or other materials provided with the distribution.
  18. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  19. * may be used to endorse or promote products derived from this software
  20. * without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. ******************************************************************************
  34. */
  35. /* Define to prevent recursive inclusion -------------------------------------*/
  36. #ifndef __STM32F4xx_HAL_DMA_H
  37. #define __STM32F4xx_HAL_DMA_H
  38. #ifdef __cplusplus
  39. extern "C" {
  40. #endif
  41. /* Includes ------------------------------------------------------------------*/
  42. #include "stm32f4xx_hal_def.h"
  43. /** @addtogroup STM32F4xx_HAL_Driver
  44. * @{
  45. */
  46. /** @addtogroup DMA
  47. * @{
  48. */
  49. /* Exported types ------------------------------------------------------------*/
  50. /** @defgroup DMA_Exported_Types DMA Exported Types
  51. * @brief DMA Exported Types
  52. * @{
  53. */
  54. /**
  55. * @brief DMA Configuration Structure definition
  56. */
  57. typedef struct
  58. {
  59. uint32_t Channel; /*!< Specifies the channel used for the specified stream.
  60. This parameter can be a value of @ref DMA_Channel_selection */
  61. uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
  62. from memory to memory or from peripheral to memory.
  63. This parameter can be a value of @ref DMA_Data_transfer_direction */
  64. uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
  65. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  66. uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
  67. This parameter can be a value of @ref DMA_Memory_incremented_mode */
  68. uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
  69. This parameter can be a value of @ref DMA_Peripheral_data_size */
  70. uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
  71. This parameter can be a value of @ref DMA_Memory_data_size */
  72. uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
  73. This parameter can be a value of @ref DMA_mode
  74. @note The circular buffer mode cannot be used if the memory-to-memory
  75. data transfer is configured on the selected Stream */
  76. uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
  77. This parameter can be a value of @ref DMA_Priority_level */
  78. uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
  79. This parameter can be a value of @ref DMA_FIFO_direct_mode
  80. @note The Direct mode (FIFO mode disabled) cannot be used if the
  81. memory-to-memory data transfer is configured on the selected stream */
  82. uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
  83. This parameter can be a value of @ref DMA_FIFO_threshold_level */
  84. uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
  85. It specifies the amount of data to be transferred in a single non interruptible
  86. transaction.
  87. This parameter can be a value of @ref DMA_Memory_burst
  88. @note The burst mode is possible only if the address Increment mode is enabled. */
  89. uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
  90. It specifies the amount of data to be transferred in a single non interruptible
  91. transaction.
  92. This parameter can be a value of @ref DMA_Peripheral_burst
  93. @note The burst mode is possible only if the address Increment mode is enabled. */
  94. }DMA_InitTypeDef;
  95. /**
  96. * @brief HAL DMA State structures definition
  97. */
  98. typedef enum
  99. {
  100. HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
  101. HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
  102. HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
  103. HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
  104. HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
  105. HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
  106. }HAL_DMA_StateTypeDef;
  107. /**
  108. * @brief HAL DMA Error Code structure definition
  109. */
  110. typedef enum
  111. {
  112. HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
  113. HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
  114. }HAL_DMA_LevelCompleteTypeDef;
  115. /**
  116. * @brief HAL DMA Error Code structure definition
  117. */
  118. typedef enum
  119. {
  120. HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
  121. HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
  122. HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
  123. HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
  124. HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
  125. HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
  126. HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
  127. }HAL_DMA_CallbackIDTypeDef;
  128. /**
  129. * @brief DMA handle Structure definition
  130. */
  131. typedef struct __DMA_HandleTypeDef
  132. {
  133. DMA_Stream_TypeDef *Instance; /*!< Register base address */
  134. DMA_InitTypeDef Init; /*!< DMA communication parameters */
  135. HAL_LockTypeDef Lock; /*!< DMA locking object */
  136. __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
  137. void *Parent; /*!< Parent object state */
  138. void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
  139. void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
  140. void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
  141. void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
  142. void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
  143. void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
  144. __IO uint32_t ErrorCode; /*!< DMA Error code */
  145. uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
  146. uint32_t StreamIndex; /*!< DMA Stream Index */
  147. }DMA_HandleTypeDef;
  148. /**
  149. * @}
  150. */
  151. /* Exported constants --------------------------------------------------------*/
  152. /** @defgroup DMA_Exported_Constants DMA Exported Constants
  153. * @brief DMA Exported constants
  154. * @{
  155. */
  156. /** @defgroup DMA_Error_Code DMA Error Code
  157. * @brief DMA Error Code
  158. * @{
  159. */
  160. #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
  161. #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
  162. #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
  163. #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
  164. #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
  165. #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
  166. #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
  167. #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
  168. /**
  169. * @}
  170. */
  171. /** @defgroup DMA_Channel_selection DMA Channel selection
  172. * @brief DMA channel selection
  173. * @{
  174. */
  175. #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
  176. #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
  177. #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
  178. #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
  179. #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
  180. #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
  181. #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
  182. #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
  183. #if defined (DMA_SxCR_CHSEL_3)
  184. #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
  185. #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
  186. #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
  187. #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
  188. #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
  189. #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
  190. #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
  191. #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
  192. #endif /* DMA_SxCR_CHSEL_3 */
  193. /**
  194. * @}
  195. */
  196. /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
  197. * @brief DMA data transfer direction
  198. * @{
  199. */
  200. #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
  201. #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
  202. #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
  203. /**
  204. * @}
  205. */
  206. /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
  207. * @brief DMA peripheral incremented mode
  208. * @{
  209. */
  210. #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
  211. #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
  212. /**
  213. * @}
  214. */
  215. /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
  216. * @brief DMA memory incremented mode
  217. * @{
  218. */
  219. #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
  220. #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
  221. /**
  222. * @}
  223. */
  224. /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
  225. * @brief DMA peripheral data size
  226. * @{
  227. */
  228. #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
  229. #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
  230. #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
  231. /**
  232. * @}
  233. */
  234. /** @defgroup DMA_Memory_data_size DMA Memory data size
  235. * @brief DMA memory data size
  236. * @{
  237. */
  238. #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
  239. #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
  240. #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
  241. /**
  242. * @}
  243. */
  244. /** @defgroup DMA_mode DMA mode
  245. * @brief DMA mode
  246. * @{
  247. */
  248. #define DMA_NORMAL 0x00000000U /*!< Normal mode */
  249. #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
  250. #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
  251. /**
  252. * @}
  253. */
  254. /** @defgroup DMA_Priority_level DMA Priority level
  255. * @brief DMA priority levels
  256. * @{
  257. */
  258. #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
  259. #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
  260. #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
  261. #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
  262. /**
  263. * @}
  264. */
  265. /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
  266. * @brief DMA FIFO direct mode
  267. * @{
  268. */
  269. #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
  270. #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
  271. /**
  272. * @}
  273. */
  274. /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
  275. * @brief DMA FIFO level
  276. * @{
  277. */
  278. #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
  279. #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
  280. #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
  281. #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
  282. /**
  283. * @}
  284. */
  285. /** @defgroup DMA_Memory_burst DMA Memory burst
  286. * @brief DMA memory burst
  287. * @{
  288. */
  289. #define DMA_MBURST_SINGLE 0x00000000U
  290. #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
  291. #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
  292. #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
  293. /**
  294. * @}
  295. */
  296. /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
  297. * @brief DMA peripheral burst
  298. * @{
  299. */
  300. #define DMA_PBURST_SINGLE 0x00000000U
  301. #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
  302. #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
  303. #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
  304. /**
  305. * @}
  306. */
  307. /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
  308. * @brief DMA interrupts definition
  309. * @{
  310. */
  311. #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
  312. #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
  313. #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
  314. #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
  315. #define DMA_IT_FE 0x00000080U
  316. /**
  317. * @}
  318. */
  319. /** @defgroup DMA_flag_definitions DMA flag definitions
  320. * @brief DMA flag definitions
  321. * @{
  322. */
  323. #define DMA_FLAG_FEIF0_4 0x00000001U
  324. #define DMA_FLAG_DMEIF0_4 0x00000004U
  325. #define DMA_FLAG_TEIF0_4 0x00000008U
  326. #define DMA_FLAG_HTIF0_4 0x00000010U
  327. #define DMA_FLAG_TCIF0_4 0x00000020U
  328. #define DMA_FLAG_FEIF1_5 0x00000040U
  329. #define DMA_FLAG_DMEIF1_5 0x00000100U
  330. #define DMA_FLAG_TEIF1_5 0x00000200U
  331. #define DMA_FLAG_HTIF1_5 0x00000400U
  332. #define DMA_FLAG_TCIF1_5 0x00000800U
  333. #define DMA_FLAG_FEIF2_6 0x00010000U
  334. #define DMA_FLAG_DMEIF2_6 0x00040000U
  335. #define DMA_FLAG_TEIF2_6 0x00080000U
  336. #define DMA_FLAG_HTIF2_6 0x00100000U
  337. #define DMA_FLAG_TCIF2_6 0x00200000U
  338. #define DMA_FLAG_FEIF3_7 0x00400000U
  339. #define DMA_FLAG_DMEIF3_7 0x01000000U
  340. #define DMA_FLAG_TEIF3_7 0x02000000U
  341. #define DMA_FLAG_HTIF3_7 0x04000000U
  342. #define DMA_FLAG_TCIF3_7 0x08000000U
  343. /**
  344. * @}
  345. */
  346. /**
  347. * @}
  348. */
  349. /* Exported macro ------------------------------------------------------------*/
  350. /** @brief Reset DMA handle state
  351. * @param __HANDLE__ specifies the DMA handle.
  352. * @retval None
  353. */
  354. #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
  355. /**
  356. * @brief Return the current DMA Stream FIFO filled level.
  357. * @param __HANDLE__ DMA handle
  358. * @retval The FIFO filling state.
  359. * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
  360. * and not empty.
  361. * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
  362. * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
  363. * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
  364. * - DMA_FIFOStatus_Empty: when FIFO is empty
  365. * - DMA_FIFOStatus_Full: when FIFO is full
  366. */
  367. #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
  368. /**
  369. * @brief Enable the specified DMA Stream.
  370. * @param __HANDLE__ DMA handle
  371. * @retval None
  372. */
  373. #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
  374. /**
  375. * @brief Disable the specified DMA Stream.
  376. * @param __HANDLE__ DMA handle
  377. * @retval None
  378. */
  379. #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
  380. /* Interrupt & Flag management */
  381. /**
  382. * @brief Return the current DMA Stream transfer complete flag.
  383. * @param __HANDLE__ DMA handle
  384. * @retval The specified transfer complete flag index.
  385. */
  386. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  387. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
  388. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
  389. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
  390. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
  391. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
  392. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
  393. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
  394. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
  395. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
  396. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
  397. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
  398. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
  399. DMA_FLAG_TCIF3_7)
  400. /**
  401. * @brief Return the current DMA Stream half transfer complete flag.
  402. * @param __HANDLE__ DMA handle
  403. * @retval The specified half transfer complete flag index.
  404. */
  405. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  406. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
  407. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
  408. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
  409. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
  410. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
  411. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
  412. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
  413. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
  414. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
  415. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
  416. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
  417. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
  418. DMA_FLAG_HTIF3_7)
  419. /**
  420. * @brief Return the current DMA Stream transfer error flag.
  421. * @param __HANDLE__ DMA handle
  422. * @retval The specified transfer error flag index.
  423. */
  424. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  425. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
  426. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
  427. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
  428. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
  429. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
  430. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
  431. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
  432. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
  433. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
  434. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
  435. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
  436. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
  437. DMA_FLAG_TEIF3_7)
  438. /**
  439. * @brief Return the current DMA Stream FIFO error flag.
  440. * @param __HANDLE__ DMA handle
  441. * @retval The specified FIFO error flag index.
  442. */
  443. #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
  444. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
  445. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
  446. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
  447. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
  448. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
  449. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
  450. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
  451. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
  452. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
  453. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
  454. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
  455. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
  456. DMA_FLAG_FEIF3_7)
  457. /**
  458. * @brief Return the current DMA Stream direct mode error flag.
  459. * @param __HANDLE__ DMA handle
  460. * @retval The specified direct mode error flag index.
  461. */
  462. #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
  463. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
  464. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
  465. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
  466. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
  467. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
  468. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
  469. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
  470. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
  471. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
  472. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
  473. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
  474. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
  475. DMA_FLAG_DMEIF3_7)
  476. /**
  477. * @brief Get the DMA Stream pending flags.
  478. * @param __HANDLE__ DMA handle
  479. * @param __FLAG__ Get the specified flag.
  480. * This parameter can be any combination of the following values:
  481. * @arg DMA_FLAG_TCIFx: Transfer complete flag.
  482. * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
  483. * @arg DMA_FLAG_TEIFx: Transfer error flag.
  484. * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
  485. * @arg DMA_FLAG_FEIFx: FIFO error flag.
  486. * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
  487. * @retval The state of FLAG (SET or RESET).
  488. */
  489. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
  490. (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
  491. ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
  492. ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
  493. /**
  494. * @brief Clear the DMA Stream pending flags.
  495. * @param __HANDLE__ DMA handle
  496. * @param __FLAG__ specifies the flag to clear.
  497. * This parameter can be any combination of the following values:
  498. * @arg DMA_FLAG_TCIFx: Transfer complete flag.
  499. * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
  500. * @arg DMA_FLAG_TEIFx: Transfer error flag.
  501. * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
  502. * @arg DMA_FLAG_FEIFx: FIFO error flag.
  503. * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
  504. * @retval None
  505. */
  506. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
  507. (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
  508. ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
  509. ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
  510. /**
  511. * @brief Enable the specified DMA Stream interrupts.
  512. * @param __HANDLE__ DMA handle
  513. * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
  514. * This parameter can be any combination of the following values:
  515. * @arg DMA_IT_TC: Transfer complete interrupt mask.
  516. * @arg DMA_IT_HT: Half transfer complete interrupt mask.
  517. * @arg DMA_IT_TE: Transfer error interrupt mask.
  518. * @arg DMA_IT_FE: FIFO error interrupt mask.
  519. * @arg DMA_IT_DME: Direct mode error interrupt.
  520. * @retval None
  521. */
  522. #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
  523. ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
  524. /**
  525. * @brief Disable the specified DMA Stream interrupts.
  526. * @param __HANDLE__ DMA handle
  527. * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
  528. * This parameter can be any combination of the following values:
  529. * @arg DMA_IT_TC: Transfer complete interrupt mask.
  530. * @arg DMA_IT_HT: Half transfer complete interrupt mask.
  531. * @arg DMA_IT_TE: Transfer error interrupt mask.
  532. * @arg DMA_IT_FE: FIFO error interrupt mask.
  533. * @arg DMA_IT_DME: Direct mode error interrupt.
  534. * @retval None
  535. */
  536. #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
  537. ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
  538. /**
  539. * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
  540. * @param __HANDLE__ DMA handle
  541. * @param __INTERRUPT__ specifies the DMA interrupt source to check.
  542. * This parameter can be one of the following values:
  543. * @arg DMA_IT_TC: Transfer complete interrupt mask.
  544. * @arg DMA_IT_HT: Half transfer complete interrupt mask.
  545. * @arg DMA_IT_TE: Transfer error interrupt mask.
  546. * @arg DMA_IT_FE: FIFO error interrupt mask.
  547. * @arg DMA_IT_DME: Direct mode error interrupt.
  548. * @retval The state of DMA_IT.
  549. */
  550. #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
  551. ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
  552. ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
  553. /**
  554. * @brief Writes the number of data units to be transferred on the DMA Stream.
  555. * @param __HANDLE__ DMA handle
  556. * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
  557. * Number of data items depends only on the Peripheral data format.
  558. *
  559. * @note If Peripheral data format is Bytes: number of data units is equal
  560. * to total number of bytes to be transferred.
  561. *
  562. * @note If Peripheral data format is Half-Word: number of data units is
  563. * equal to total number of bytes to be transferred / 2.
  564. *
  565. * @note If Peripheral data format is Word: number of data units is equal
  566. * to total number of bytes to be transferred / 4.
  567. *
  568. * @retval The number of remaining data units in the current DMAy Streamx transfer.
  569. */
  570. #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
  571. /**
  572. * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
  573. * @param __HANDLE__ DMA handle
  574. *
  575. * @retval The number of remaining data units in the current DMA Stream transfer.
  576. */
  577. #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
  578. /* Include DMA HAL Extension module */
  579. #include "stm32f4xx_hal_dma_ex.h"
  580. /* Exported functions --------------------------------------------------------*/
  581. /** @defgroup DMA_Exported_Functions DMA Exported Functions
  582. * @brief DMA Exported functions
  583. * @{
  584. */
  585. /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
  586. * @brief Initialization and de-initialization functions
  587. * @{
  588. */
  589. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
  590. HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
  591. /**
  592. * @}
  593. */
  594. /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
  595. * @brief I/O operation functions
  596. * @{
  597. */
  598. HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  599. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  600. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
  601. HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
  602. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
  603. void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
  604. HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
  605. HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
  606. HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
  607. /**
  608. * @}
  609. */
  610. /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
  611. * @brief Peripheral State functions
  612. * @{
  613. */
  614. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
  615. uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
  616. /**
  617. * @}
  618. */
  619. /**
  620. * @}
  621. */
  622. /* Private Constants -------------------------------------------------------------*/
  623. /** @defgroup DMA_Private_Constants DMA Private Constants
  624. * @brief DMA private defines and constants
  625. * @{
  626. */
  627. /**
  628. * @}
  629. */
  630. /* Private macros ------------------------------------------------------------*/
  631. /** @defgroup DMA_Private_Macros DMA Private Macros
  632. * @brief DMA private macros
  633. * @{
  634. */
  635. #if defined (DMA_SxCR_CHSEL_3)
  636. #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
  637. ((CHANNEL) == DMA_CHANNEL_1) || \
  638. ((CHANNEL) == DMA_CHANNEL_2) || \
  639. ((CHANNEL) == DMA_CHANNEL_3) || \
  640. ((CHANNEL) == DMA_CHANNEL_4) || \
  641. ((CHANNEL) == DMA_CHANNEL_5) || \
  642. ((CHANNEL) == DMA_CHANNEL_6) || \
  643. ((CHANNEL) == DMA_CHANNEL_7) || \
  644. ((CHANNEL) == DMA_CHANNEL_8) || \
  645. ((CHANNEL) == DMA_CHANNEL_9) || \
  646. ((CHANNEL) == DMA_CHANNEL_10)|| \
  647. ((CHANNEL) == DMA_CHANNEL_11)|| \
  648. ((CHANNEL) == DMA_CHANNEL_12)|| \
  649. ((CHANNEL) == DMA_CHANNEL_13)|| \
  650. ((CHANNEL) == DMA_CHANNEL_14)|| \
  651. ((CHANNEL) == DMA_CHANNEL_15))
  652. #else
  653. #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
  654. ((CHANNEL) == DMA_CHANNEL_1) || \
  655. ((CHANNEL) == DMA_CHANNEL_2) || \
  656. ((CHANNEL) == DMA_CHANNEL_3) || \
  657. ((CHANNEL) == DMA_CHANNEL_4) || \
  658. ((CHANNEL) == DMA_CHANNEL_5) || \
  659. ((CHANNEL) == DMA_CHANNEL_6) || \
  660. ((CHANNEL) == DMA_CHANNEL_7))
  661. #endif /* DMA_SxCR_CHSEL_3 */
  662. #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
  663. ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
  664. ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
  665. #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
  666. #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
  667. ((STATE) == DMA_PINC_DISABLE))
  668. #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
  669. ((STATE) == DMA_MINC_DISABLE))
  670. #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
  671. ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
  672. ((SIZE) == DMA_PDATAALIGN_WORD))
  673. #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
  674. ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
  675. ((SIZE) == DMA_MDATAALIGN_WORD ))
  676. #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
  677. ((MODE) == DMA_CIRCULAR) || \
  678. ((MODE) == DMA_PFCTRL))
  679. #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
  680. ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
  681. ((PRIORITY) == DMA_PRIORITY_HIGH) || \
  682. ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
  683. #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
  684. ((STATE) == DMA_FIFOMODE_ENABLE))
  685. #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
  686. ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
  687. ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
  688. ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
  689. #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
  690. ((BURST) == DMA_MBURST_INC4) || \
  691. ((BURST) == DMA_MBURST_INC8) || \
  692. ((BURST) == DMA_MBURST_INC16))
  693. #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
  694. ((BURST) == DMA_PBURST_INC4) || \
  695. ((BURST) == DMA_PBURST_INC8) || \
  696. ((BURST) == DMA_PBURST_INC16))
  697. /**
  698. * @}
  699. */
  700. /* Private functions ---------------------------------------------------------*/
  701. /** @defgroup DMA_Private_Functions DMA Private Functions
  702. * @brief DMA private functions
  703. * @{
  704. */
  705. /**
  706. * @}
  707. */
  708. /**
  709. * @}
  710. */
  711. /**
  712. * @}
  713. */
  714. #ifdef __cplusplus
  715. }
  716. #endif
  717. #endif /* __STM32F4xx_HAL_DMA_H */
  718. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/