stm32l0xx_hal_pwr.c 27 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l0xx_hal_pwr.c
  4. * @author MCD Application Team
  5. * @version V1.7.0
  6. * @date 31-May-2016
  7. * @brief PWR HAL module driver.
  8. *
  9. * This file provides firmware functions to manage the following
  10. * functionalities of the Power Controller (PWR) peripheral:
  11. * + Initialization/de-initialization functions
  12. * + Peripheral Control functions
  13. *
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  18. *
  19. * Redistribution and use in source and binary forms, with or without modification,
  20. * are permitted provided that the following conditions are met:
  21. * 1. Redistributions of source code must retain the above copyright notice,
  22. * this list of conditions and the following disclaimer.
  23. * 2. Redistributions in binary form must reproduce the above copyright notice,
  24. * this list of conditions and the following disclaimer in the documentation
  25. * and/or other materials provided with the distribution.
  26. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  27. * may be used to endorse or promote products derived from this software
  28. * without specific prior written permission.
  29. *
  30. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  31. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  34. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  36. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  37. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  38. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. *
  41. ******************************************************************************
  42. */
  43. /* Includes ------------------------------------------------------------------*/
  44. #include "stm32l0xx_hal.h"
  45. #ifdef HAL_PWR_MODULE_ENABLED
  46. /** @addtogroup STM32L0xx_HAL_Driver
  47. * @{
  48. */
  49. /** @addtogroup PWR
  50. * @{
  51. */
  52. /** @addtogroup PWR_Private
  53. * @{
  54. */
  55. /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
  56. * @{
  57. */
  58. #define PVD_MODE_IT ((uint32_t)0x00010000U)
  59. #define PVD_MODE_EVT ((uint32_t)0x00020000U)
  60. #define PVD_RISING_EDGE ((uint32_t)0x00000001U)
  61. #define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
  62. /**
  63. * @}
  64. */
  65. /**
  66. * @}
  67. */
  68. /** @addtogroup PWR_Exported_Functions
  69. * @{
  70. */
  71. /** @addtogroup PWR_Exported_Functions_Group1
  72. * @brief Initialization and de-initialization functions
  73. *
  74. @verbatim
  75. ===============================================================================
  76. ##### Initialization and de-initialization functions #####
  77. ===============================================================================
  78. @endverbatim
  79. * @{
  80. */
  81. /**
  82. * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
  83. * @retval None
  84. */
  85. void HAL_PWR_DeInit(void)
  86. {
  87. __HAL_RCC_PWR_FORCE_RESET();
  88. __HAL_RCC_PWR_RELEASE_RESET();
  89. }
  90. /**
  91. * @}
  92. */
  93. /** @addtogroup PWR_Exported_Functions_Group2
  94. * @brief Low Power modes configuration functions
  95. *
  96. @verbatim
  97. ===============================================================================
  98. ##### Peripheral Control functions #####
  99. ===============================================================================
  100. *** Backup domain ***
  101. =========================
  102. [..]
  103. After reset, the backup domain (RTC registers, RTC backup data
  104. registers) is protected against possible unwanted
  105. write accesses.
  106. To enable access to the RTC Domain and RTC registers, proceed as follows:
  107. (+) Enable the Power Controller (PWR) APB1 interface clock using the
  108. __HAL_RCC_PWR_CLK_ENABLE() macro.
  109. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
  110. *** PVD configuration ***
  111. =========================
  112. [..]
  113. (+) The PVD is used to monitor the VDD power supply by comparing it to a
  114. threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
  115. (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
  116. internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
  117. when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
  118. (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
  119. than the PVD threshold. This event is internally connected to the EXTI
  120. line16 and can generate an interrupt if enabled. This is done through
  121. __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
  122. (+) The PVD is stopped in Standby mode.
  123. *** WakeUp pin configuration ***
  124. ================================
  125. [..]
  126. (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
  127. forced in input pull-down configuration and is active on rising edges.
  128. (+) There are two WakeUp pins:
  129. WakeUp Pin 1 on PA.00.
  130. WakeUp Pin 2 on PC.13.
  131. WakeUp Pin 3 on PE.06 .
  132. [..]
  133. *** Main and Backup Regulators configuration ***
  134. ================================================
  135. (+) The main internal regulator can be configured to have a tradeoff between
  136. performance and power consumption when the device does not operate at
  137. the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
  138. macro which configures the two VOS bits in PWR_CR register:
  139. (++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mode selected and
  140. the System frequency can go up to 32 MHz.
  141. (++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mode selected and
  142. the System frequency can go up to 16 MHz.
  143. (++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mode selected and
  144. the System frequency can go up to 4.2 MHz.
  145. Refer to the datasheets for more details.
  146. *** Low Power modes configuration ***
  147. =====================================
  148. [..]
  149. The device features 5 low-power modes:
  150. (+) Low power run mode: regulator in low power mode, limited clock frequency,
  151. limited number of peripherals running.
  152. (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running.
  153. (+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency,
  154. limited number of peripherals running, regulator in low power mode.
  155. (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
  156. (+) Standby mode: VCORE domain powered off
  157. *** Low power run mode ***
  158. =========================
  159. [..]
  160. To further reduce the consumption when the system is in Run mode, the regulator can be
  161. configured in low power mode. In this mode, the system frequency should not exceed
  162. MSI frequency range1.
  163. In Low power run mode, all I/O pins keep the same state as in Run mode.
  164. (+) Entry:
  165. (++) VCORE in range2
  166. (++) Decrease the system frequency not to exceed the frequency of MSI frequency range1.
  167. (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
  168. function.
  169. (+) Exit:
  170. (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
  171. function.
  172. (++) Increase the system frequency if needed.
  173. *** Sleep mode ***
  174. ==================
  175. [..]
  176. (+) Entry:
  177. The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
  178. functions with
  179. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  180. (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  181. (+) Exit:
  182. (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
  183. controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was used to enter sleep mode,
  184. the MCU exits Sleep mode as soon as an event occurs.
  185. *** Low power sleep mode ***
  186. ============================
  187. [..]
  188. (+) Entry:
  189. The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
  190. functions with
  191. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  192. (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  193. (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
  194. This reduces power consumption but increases the wake-up time.
  195. (+) Exit:
  196. (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
  197. acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
  198. from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
  199. the MCU exits Sleep mode as soon as an event occurs.
  200. *** Stop mode ***
  201. =================
  202. [..]
  203. The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral
  204. clock gating. The voltage regulator can be configured either in normal or low-power mode.
  205. In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
  206. the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
  207. To get the lowest consumption in Stop mode, the internal Flash memory also enters low
  208. power mode. When the Flash memory is in power-down mode, an additional startup delay is
  209. incurred when waking up from Stop mode.
  210. To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
  211. sensor can be switched off before entering Stop mode. They can be switched on again by
  212. software after exiting Stop mode using the ULP bit in the PWR_CR register.
  213. In Stop mode, all I/O pins keep the same state as in Run mode.
  214. (+) Entry:
  215. The Stop mode is entered using the HAL_PWR_EnterSTOPMode
  216. function with:
  217. (++) Main regulator ON.
  218. (++) Low Power regulator ON.
  219. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  220. (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  221. (+) Exit:
  222. (++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC
  223. oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
  224. register
  225. *** Standby mode ***
  226. ====================
  227. [..]
  228. The Standby mode allows to achieve the lowest power consumption. It is based on the
  229. Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is
  230. consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
  231. also switched off. SRAM and register contents are lost except for the RTC registers, RTC
  232. backup registers and Standby circuitry.
  233. To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
  234. sensor can be switched off before entering the Standby mode. They can be switched
  235. on again by software after exiting the Standby mode.
  236. function.
  237. (+) Entry:
  238. (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
  239. (+) Exit:
  240. (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
  241. tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
  242. *** Auto-wakeup (AWU) from low-power mode ***
  243. =============================================
  244. [..]
  245. The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
  246. Wakeup event, a tamper event, a time-stamp event, or a comparator event,
  247. without depending on an external interrupt (Auto-wakeup mode).
  248. (+) RTC auto-wakeup (AWU) from the Stop mode
  249. (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
  250. (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
  251. or Event modes) using the EXTI_Init() function.
  252. (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
  253. (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
  254. and RTC_AlarmCmd() functions.
  255. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
  256. is necessary to:
  257. (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
  258. or Event modes) using the EXTI_Init() function.
  259. (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
  260. function.
  261. (+++) Configure the RTC to detect the tamper or time stamp event using the
  262. RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
  263. functions.
  264. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
  265. (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
  266. or Event modes) using the EXTI_Init() function.
  267. (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
  268. (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
  269. RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
  270. (+) RTC auto-wakeup (AWU) from the Standby mode
  271. (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
  272. (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
  273. (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
  274. and RTC_AlarmCmd() functions.
  275. (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
  276. is necessary to:
  277. (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
  278. function.
  279. (+++) Configure the RTC to detect the tamper or time stamp event using the
  280. RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
  281. functions.
  282. (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
  283. (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
  284. (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
  285. RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
  286. (+) Comparator auto-wakeup (AWU) from the Stop mode
  287. (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
  288. event, it is necessary to:
  289. (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
  290. to be sensitive to to the selected edges (falling, rising or falling
  291. and rising) (Interrupt or Event modes) using the EXTI_Init() function.
  292. (+++) Configure the comparator to generate the event.
  293. @endverbatim
  294. * @{
  295. */
  296. /**
  297. * @brief Enables access to the backup domain (RTC registers, RTC
  298. * backup data registers ).
  299. * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
  300. * Backup Domain Access should be kept enabled.
  301. * @retval None
  302. */
  303. void HAL_PWR_EnableBkUpAccess(void)
  304. {
  305. /* Enable access to RTC and backup registers */
  306. SET_BIT(PWR->CR, PWR_CR_DBP);
  307. }
  308. /**
  309. * @brief Disables access to the backup domain
  310. * @note Applies to RTC registers, RTC backup data registers.
  311. * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
  312. * Backup Domain Access should be kept enabled.
  313. * @retval None
  314. */
  315. void HAL_PWR_DisableBkUpAccess(void)
  316. {
  317. /* Disable access to RTC and backup registers */
  318. CLEAR_BIT(PWR->CR, PWR_CR_DBP);
  319. }
  320. /**
  321. * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
  322. * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
  323. * information for the PVD.
  324. * @note Refer to the electrical characteristics of your device datasheet for
  325. * more details about the voltage threshold corresponding to each
  326. * detection level.
  327. * @retval None
  328. */
  329. void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
  330. {
  331. /* Check the parameters */
  332. assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
  333. assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
  334. /* Set PLS[7:5] bits according to PVDLevel value */
  335. MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
  336. /* Clear any previous config. Keep it clear if no event or IT mode is selected */
  337. __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
  338. __HAL_PWR_PVD_EXTI_DISABLE_IT();
  339. __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
  340. __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
  341. /* Configure interrupt mode */
  342. if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
  343. {
  344. __HAL_PWR_PVD_EXTI_ENABLE_IT();
  345. }
  346. /* Configure event mode */
  347. if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
  348. {
  349. __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
  350. }
  351. /* Configure the edge */
  352. if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
  353. {
  354. __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
  355. }
  356. if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
  357. {
  358. __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
  359. }
  360. }
  361. /**
  362. * @brief Enables the Power Voltage Detector(PVD).
  363. * @retval None
  364. */
  365. void HAL_PWR_EnablePVD(void)
  366. {
  367. /* Enable the power voltage detector */
  368. SET_BIT(PWR->CR, PWR_CR_PVDE);
  369. }
  370. /**
  371. * @brief Disables the Power Voltage Detector(PVD).
  372. * @retval None
  373. */
  374. void HAL_PWR_DisablePVD(void)
  375. {
  376. /* Disable the power voltage detector */
  377. CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
  378. }
  379. /**
  380. * @brief Enables the WakeUp PINx functionality.
  381. * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
  382. * This parameter can be one of the following values:
  383. * @arg PWR_WAKEUP_PIN1
  384. * @arg PWR_WAKEUP_PIN2
  385. * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
  386. * @retval None
  387. */
  388. void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
  389. {
  390. /* Check the parameter */
  391. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  392. /* Enable the EWUPx pin */
  393. SET_BIT(PWR->CSR, WakeUpPinx);
  394. }
  395. /**
  396. * @brief Disables the WakeUp PINx functionality.
  397. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
  398. * This parameter can be one of the following values:
  399. * @arg PWR_WAKEUP_PIN1
  400. * @arg PWR_WAKEUP_PIN2
  401. * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
  402. * @retval None
  403. */
  404. void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
  405. {
  406. /* Check the parameter */
  407. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  408. /* Disable the EWUPx pin */
  409. CLEAR_BIT(PWR->CSR, WakeUpPinx);
  410. }
  411. /**
  412. * @brief Enters Sleep mode.
  413. * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
  414. * @param Regulator: Specifies the regulator state in SLEEP mode.
  415. * This parameter can be one of the following values:
  416. * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
  417. * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
  418. * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
  419. * When WFI entry is used, tick interrupt have to be disabled if not desired as
  420. * the interrupt wake up source.
  421. * This parameter can be one of the following values:
  422. * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  423. * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  424. * @retval None
  425. */
  426. void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
  427. {
  428. uint32_t tmpreg = 0U;
  429. /* Check the parameters */
  430. assert_param(IS_PWR_REGULATOR(Regulator));
  431. assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
  432. /* Select the regulator state in Sleep mode ---------------------------------*/
  433. tmpreg = PWR->CR;
  434. /* Clear PDDS and LPDS bits */
  435. CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
  436. /* Set LPSDSR bit according to PWR_Regulator value */
  437. SET_BIT(tmpreg, Regulator);
  438. /* Store the new value */
  439. PWR->CR = tmpreg;
  440. /* Clear SLEEPDEEP bit of Cortex System Control Register */
  441. CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
  442. /* Select SLEEP mode entry -------------------------------------------------*/
  443. if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
  444. {
  445. /* Request Wait For Interrupt */
  446. __WFI();
  447. }
  448. else
  449. {
  450. /* Request Wait For Event */
  451. __SEV();
  452. __WFE();
  453. __WFE();
  454. }
  455. }
  456. /**
  457. * @brief Enters Stop mode.
  458. * @note In Stop mode, all I/O pins keep the same state as in Run mode.
  459. * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
  460. * MSI or HSI16 RCoscillator is selected as system clock depending
  461. * the bit STOPWUCK in the RCC_CFGR register.
  462. * @note When the voltage regulator operates in low power mode, an additional
  463. * startup delay is incurred when waking up from Stop mode.
  464. * By keeping the internal regulator ON during Stop mode, the consumption
  465. * is higher although the startup time is reduced.
  466. * @note Before entering in this function, it is important to ensure that the WUF
  467. * wakeup flag is cleared. To perform this action, it is possible to call the
  468. * following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU)
  469. *
  470. * @param Regulator: Specifies the regulator state in Stop mode.
  471. * This parameter can be one of the following values:
  472. * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  473. * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
  474. * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
  475. * This parameter can be one of the following values:
  476. * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  477. * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
  478. * @retval None
  479. */
  480. void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  481. {
  482. uint32_t tmpreg = 0U;
  483. /* Check the parameters */
  484. assert_param(IS_PWR_REGULATOR(Regulator));
  485. assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
  486. /* Select the regulator state in Stop mode ---------------------------------*/
  487. tmpreg = PWR->CR;
  488. /* Clear PDDS and LPDS bits */
  489. CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
  490. /* Set LPSDSR bit according to PWR_Regulator value */
  491. SET_BIT(tmpreg, Regulator);
  492. /* Store the new value */
  493. PWR->CR = tmpreg;
  494. /* Set SLEEPDEEP bit of Cortex System Control Register */
  495. SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
  496. /* Select Stop mode entry --------------------------------------------------*/
  497. if(STOPEntry == PWR_STOPENTRY_WFI)
  498. {
  499. /* Request Wait For Interrupt */
  500. __WFI();
  501. }
  502. else
  503. {
  504. /* Request Wait For Event */
  505. __SEV();
  506. __WFE();
  507. __WFE();
  508. }
  509. /* Reset SLEEPDEEP bit of Cortex System Control Register */
  510. CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
  511. }
  512. /**
  513. * @brief Enters Standby mode.
  514. * @note In Standby mode, all I/O pins are high impedance except for:
  515. * - Reset pad (still available)
  516. * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
  517. * Alarm out, or RTC clock calibration out.
  518. * - RTC_AF2 pin (PC13) if configured for tamper.
  519. * - WKUP pin 1 (PA00) if enabled.
  520. * - WKUP pin 2 (PC13) if enabled.
  521. * - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only.
  522. * - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only.
  523. * @retval None
  524. */
  525. void HAL_PWR_EnterSTANDBYMode(void)
  526. {
  527. /* Select Standby mode */
  528. SET_BIT(PWR->CR, PWR_CR_PDDS);
  529. /* Set SLEEPDEEP bit of Cortex System Control Register */
  530. SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
  531. /* This option is used to ensure that store operations are completed */
  532. #if defined ( __CC_ARM)
  533. __force_stores();
  534. #endif
  535. /* Request Wait For Interrupt */
  536. __WFI();
  537. }
  538. /**
  539. * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
  540. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  541. * re-enters SLEEP mode when an interruption handling is over.
  542. * Setting this bit is useful when the processor is expected to run only on
  543. * interruptions handling.
  544. * @retval None
  545. */
  546. void HAL_PWR_EnableSleepOnExit(void)
  547. {
  548. /* Set SLEEPONEXIT bit of Cortex System Control Register */
  549. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  550. }
  551. /**
  552. * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
  553. * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  554. * re-enters SLEEP mode when an interruption handling is over.
  555. * @retval None
  556. */
  557. void HAL_PWR_DisableSleepOnExit(void)
  558. {
  559. /* Clear SLEEPONEXIT bit of Cortex System Control Register */
  560. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  561. }
  562. /**
  563. * @brief Enables CORTEX M0+ SEVONPEND bit.
  564. * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
  565. * WFE to wake up when an interrupt moves from inactive to pended.
  566. * @retval None
  567. */
  568. void HAL_PWR_EnableSEVOnPend(void)
  569. {
  570. /* Set SEVONPEND bit of Cortex System Control Register */
  571. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  572. }
  573. /**
  574. * @brief Disables CORTEX M0+ SEVONPEND bit.
  575. * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
  576. * WFE to wake up when an interrupt moves from inactive to pended.
  577. * @retval None
  578. */
  579. void HAL_PWR_DisableSEVOnPend(void)
  580. {
  581. /* Clear SEVONPEND bit of Cortex System Control Register */
  582. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  583. }
  584. /**
  585. * @brief This function handles the PWR PVD interrupt request.
  586. * @note This API should be called under the PVD_IRQHandler().
  587. * @retval None
  588. */
  589. void HAL_PWR_PVD_IRQHandler(void)
  590. {
  591. /* Check PWR exti flag */
  592. if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
  593. {
  594. /* PWR PVD interrupt user callback */
  595. HAL_PWR_PVDCallback();
  596. /* Clear PWR Exti pending bit */
  597. __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
  598. }
  599. }
  600. /**
  601. * @brief PWR PVD interrupt callback
  602. * @retval None
  603. */
  604. __weak void HAL_PWR_PVDCallback(void)
  605. {
  606. /* NOTE : This function Should not be modified, when the callback is needed,
  607. the HAL_PWR_PVDCallback could be implemented in the user file
  608. */
  609. }
  610. /**
  611. * @}
  612. */
  613. /**
  614. * @}
  615. */
  616. #endif /* HAL_PWR_MODULE_ENABLED */
  617. /**
  618. * @}
  619. */
  620. /**
  621. * @}
  622. */
  623. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/