contex_ck802_gcc.S 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152
  1. /*
  2. * File : contex_ck802.S
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * Change Logs:
  21. * Date Author Notes
  22. * 2017-01-01 Urey first version
  23. * 2018-06-05 tanek clean code
  24. */
  25. .file "contex_ck802.S"
  26. #undef VIC_TSPDR
  27. #define VIC_TSPDR 0XE000EC08
  28. .global rt_thread_switch_interrupt_flag
  29. .global rt_interrupt_from_thread
  30. .global rt_interrupt_to_thread
  31. .text
  32. .align 2
  33. /*
  34. * rt_base_t rt_hw_interrupt_disable(void);
  35. */
  36. .global rt_hw_interrupt_disable
  37. .type rt_hw_interrupt_disable, %function
  38. rt_hw_interrupt_disable:
  39. mfcr r0, psr
  40. psrclr ie
  41. rts
  42. /*
  43. * void rt_hw_interrupt_enable(rt_base_t psr);
  44. */
  45. .global rt_hw_interrupt_enable
  46. .type rt_hw_interrupt_enable, %function
  47. rt_hw_interrupt_enable:
  48. mtcr r0, psr
  49. rts
  50. /*
  51. * void rt_hw_context_switch_to(rt_uint32 to);
  52. * R0 --> to
  53. */
  54. .global rt_hw_context_switch_to
  55. .type rt_hw_context_switch_to, %function
  56. rt_hw_context_switch_to:
  57. lrw r2, rt_interrupt_to_thread
  58. stw r0, (r2)
  59. /* set form thread = 0 */
  60. lrw r2, rt_interrupt_from_thread
  61. movi r0, 0
  62. stw r0, (r2)
  63. psrclr ie
  64. jbr __tspend_handler_nosave
  65. /*
  66. * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
  67. * r0 --> from
  68. * r1 --> to
  69. */
  70. .global rt_hw_context_switch_interrupt
  71. .type rt_hw_context_switch_interrupt, %function
  72. rt_hw_context_switch_interrupt:
  73. lrw r2, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
  74. stw r0, (r2)
  75. lrw r2, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
  76. stw r1, (r2)
  77. lrw r0, VIC_TSPDR
  78. bgeni r1, 0
  79. stw r1, (r0)
  80. rts
  81. /*
  82. * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
  83. * r0 --> from
  84. * r1 --> to
  85. */
  86. .global rt_hw_context_switch
  87. .type rt_hw_context_switch, %function
  88. rt_hw_context_switch:
  89. lrw r2, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
  90. stw r0, (r2)
  91. lrw r2, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
  92. stw r1, (r2)
  93. lrw r0, VIC_TSPDR
  94. bgeni r1, 0
  95. stw r1, (r0)
  96. rts
  97. .global PendSV_Handler
  98. .type PendSV_Handler, %function
  99. PendSV_Handler:
  100. subi sp, 68
  101. stm r0-r13, (sp)
  102. stw r15, (sp, 56)
  103. mfcr r0, epsr
  104. stw r0, (sp, 60)
  105. mfcr r0, epc
  106. stw r0, (sp, 64)
  107. lrw r0, rt_interrupt_from_thread
  108. ldw r1, (r0)
  109. stw sp, (r1)
  110. __tspend_handler_nosave:
  111. lrw r6, rt_interrupt_to_thread
  112. lrw r7, rt_interrupt_from_thread
  113. ldw r8, (r6)
  114. stw r8, (r7)
  115. ldw sp, (r8)
  116. #ifdef CONFIG_STACK_GUARD
  117. mfcr r3, cr<0, 4>
  118. bseti r3, 0
  119. bseti r3, 1
  120. mtcr r3, cr<0, 4>
  121. #endif
  122. ldw r0, (sp, 64)
  123. mtcr r0, epc
  124. ldw r0, (sp, 60)
  125. bseti r0, 6
  126. mtcr r0, epsr
  127. ldw r15, (sp, 56)
  128. ldm r0-r13, (sp)
  129. addi sp, 68
  130. rte