phytium_cpu_id.S 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Email: opensource_embedded@phytium.com.cn
  7. *
  8. * Change Logs:
  9. * Date Author Notes
  10. * 2023-07-26 huanghe first commit
  11. *
  12. */
  13. #include "fparameters.h"
  14. #include "rtconfig.h"
  15. #ifndef __aarch64__
  16. .globl cpu_id_mapping
  17. cpu_id_mapping:
  18. #if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
  19. cmp r0, #0 // compare cpu_id with 0
  20. beq map_cpu_id_0
  21. cmp r0, #1 // compare cpu_id with 1
  22. beq map_cpu_id_1
  23. cmp r0, #2 // compare cpu_id with 2
  24. beq map_cpu_id_2
  25. cmp r0, #3 // compare cpu_id with 3
  26. beq map_cpu_id_3
  27. mov pc, lr // no mapping needed
  28. #endif
  29. mov pc, lr // no mapping needed
  30. // Mapping for E2000Q
  31. map_cpu_id_0:
  32. mov r0, #2
  33. mov pc, lr
  34. map_cpu_id_1:
  35. mov r0, #3
  36. mov pc, lr
  37. map_cpu_id_2:
  38. mov r0, #0
  39. mov pc, lr
  40. map_cpu_id_3:
  41. mov r0, #1
  42. mov pc, lr
  43. .globl rt_hw_cpu_id_early
  44. rt_hw_cpu_id_early:
  45. // read MPIDR
  46. mov r9, lr
  47. mrc p15, 0, r0, c0, c0, 5
  48. ubfx r0, r0, #0, #12
  49. ldr r1,= CORE0_AFF
  50. cmp r0, r1
  51. beq core0
  52. #if defined(CORE1_AFF)
  53. ldr r1,= CORE1_AFF
  54. cmp r0, r1
  55. beq core1
  56. #endif
  57. #if defined(CORE2_AFF)
  58. ldr r1,= CORE2_AFF
  59. cmp r0, r1
  60. beq core2
  61. #endif
  62. #if defined(CORE3_AFF)
  63. ldr r1,= CORE3_AFF
  64. cmp r0, r1
  65. beq core3
  66. #endif
  67. b default
  68. core0:
  69. mov r0, #0
  70. b return
  71. core1:
  72. mov r0, #1
  73. b return
  74. core2:
  75. mov r0, #2
  76. b return
  77. core3:
  78. mov r0, #3
  79. b return
  80. core4:
  81. mov r0, #4
  82. b return
  83. core5:
  84. mov r0, #5
  85. b return
  86. core6:
  87. mov r0, #6
  88. b return
  89. core8:
  90. mov r0, #8
  91. b return
  92. default:
  93. and r0, r0, #15
  94. return:
  95. bl cpu_id_mapping
  96. mov pc, r9
  97. #else
  98. .globl cpu_id_mapping
  99. cpu_id_mapping:
  100. #if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
  101. cmp x0, #0 // compare cpu_id with 0
  102. beq map_cpu_id_0
  103. cmp x0, #1 // compare cpu_id with 1
  104. beq map_cpu_id_1
  105. cmp x0, #2 // compare cpu_id with 2
  106. beq map_cpu_id_2
  107. cmp x0, #3 // compare cpu_id with 3
  108. beq map_cpu_id_3
  109. RET // no mapping needed
  110. #endif
  111. RET // no mapping needed
  112. // Mapping for E2000Q
  113. map_cpu_id_0:
  114. mov x0, #2
  115. RET
  116. map_cpu_id_1:
  117. mov x0, #3
  118. RET
  119. map_cpu_id_2:
  120. mov x0, #0
  121. RET
  122. map_cpu_id_3:
  123. mov x0, #1
  124. RET
  125. .globl rt_hw_cpu_id_set
  126. rt_hw_cpu_id_set:
  127. mov x9, lr
  128. mrs x0,MPIDR_EL1
  129. and x1, x0, #15
  130. msr tpidr_el1, x1
  131. ubfx x0, x0, #0, #12
  132. ldr x1,= CORE0_AFF
  133. cmp x0, x1
  134. beq core0
  135. #if defined(CORE1_AFF)
  136. ldr x1,= CORE1_AFF
  137. cmp x0, x1
  138. beq core1
  139. #endif
  140. #if defined(CORE2_AFF)
  141. ldr x1,= CORE2_AFF
  142. cmp x0, x1
  143. beq core2
  144. #endif
  145. #if defined(CORE3_AFF)
  146. ldr x1,= CORE3_AFF
  147. cmp x0, x1
  148. beq core3
  149. #endif
  150. b default
  151. core0:
  152. mov x0, #0
  153. b return
  154. core1:
  155. mov x0, #1
  156. b return
  157. core2:
  158. mov x0, #2
  159. b return
  160. core3:
  161. mov x0, #3
  162. b return
  163. core4:
  164. mov x0, #4
  165. b return
  166. core5:
  167. mov x0, #5
  168. b return
  169. core6:
  170. mov x0, #6
  171. b return
  172. core8:
  173. mov x0, #8
  174. b return
  175. default:
  176. and x0, x0, #15
  177. return:
  178. //bl cpu_id_mapping
  179. mov lr, x9
  180. RET
  181. #endif