board_dev.c 4.2 KB

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  1. /**************************************************************************//**
  2. *
  3. * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Change Logs:
  8. * Date Author Notes
  9. * 2022-02-22 klcheng First version
  10. *
  11. ******************************************************************************/
  12. #include "NuMicro.h"
  13. #include <rtdevice.h>
  14. #include <drv_gpio.h>
  15. #if defined(BOARD_USING_STORAGE_SPIFLASH)
  16. #if defined(RT_USING_SFUD)
  17. #include "spi_flash.h"
  18. #include "spi_flash_sfud.h"
  19. #endif
  20. #include "drv_qspi.h"
  21. #define W25X_REG_READSTATUS (0x05)
  22. #define W25X_REG_READSTATUS2 (0x35)
  23. #define W25X_REG_WRITEENABLE (0x06)
  24. #define W25X_REG_WRITESTATUS (0x01)
  25. #define W25X_REG_QUADENABLE (0x02)
  26. static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
  27. {
  28. rt_uint8_t u8Val;
  29. rt_err_t result = RT_EOK;
  30. rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
  31. result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
  32. RT_ASSERT(result > 0);
  33. return u8Val;
  34. }
  35. static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
  36. {
  37. rt_uint8_t u8Val;
  38. rt_err_t result = RT_EOK;
  39. rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
  40. result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
  41. RT_ASSERT(result > 0);
  42. return u8Val;
  43. }
  44. static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
  45. {
  46. rt_uint8_t w25x_txCMD1;
  47. rt_uint8_t au8Val[2];
  48. rt_err_t result;
  49. struct rt_qspi_message qspi_message = {0};
  50. /* Enable WE */
  51. w25x_txCMD1 = W25X_REG_WRITEENABLE;
  52. result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1));
  53. if (result != sizeof(w25x_txCMD1))
  54. goto exit_SpiFlash_WriteStatusReg;
  55. /* Prepare status-1, 2 data */
  56. au8Val[0] = u8Value1;
  57. au8Val[1] = u8Value2;
  58. /* 1-bit mode: Instruction+payload */
  59. qspi_message.instruction.content = W25X_REG_WRITESTATUS;
  60. qspi_message.instruction.qspi_lines = 1;
  61. qspi_message.qspi_data_lines = 1;
  62. qspi_message.parent.cs_take = 1;
  63. qspi_message.parent.cs_release = 1;
  64. qspi_message.parent.send_buf = &au8Val[0];
  65. qspi_message.parent.length = sizeof(au8Val);
  66. qspi_message.parent.next = RT_NULL;
  67. if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val))
  68. {
  69. result = -RT_ERROR;
  70. }
  71. result = RT_EOK;
  72. exit_SpiFlash_WriteStatusReg:
  73. return result;
  74. }
  75. static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
  76. {
  77. volatile uint8_t u8ReturnValue;
  78. do
  79. {
  80. u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
  81. u8ReturnValue = u8ReturnValue & 1;
  82. }
  83. while (u8ReturnValue != 0); // check the BUSY bit
  84. }
  85. static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
  86. {
  87. rt_err_t result = RT_EOK;
  88. uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
  89. uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
  90. u8Status2 |= W25X_REG_QUADENABLE;
  91. result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
  92. RT_ASSERT(result == RT_EOK);
  93. SpiFlash_WaitReady(qspi_device);
  94. }
  95. static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
  96. {
  97. rt_err_t result = RT_EOK;
  98. uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
  99. uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
  100. u8Status2 &= ~W25X_REG_QUADENABLE;
  101. result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
  102. RT_ASSERT(result == RT_EOK);
  103. SpiFlash_WaitReady(qspi_device);
  104. }
  105. static int rt_hw_spiflash_init(void)
  106. {
  107. /* Here, we use Dual I/O to drive the SPI flash by default. */
  108. /* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */
  109. if (nu_qspi_bus_attach_device("qspi0", "qspi01", 2, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
  110. return -1;
  111. #if defined(RT_USING_SFUD)
  112. if (rt_sfud_flash_probe("flash0", "qspi01") == RT_NULL)
  113. {
  114. return -(RT_ERROR);
  115. }
  116. #endif
  117. return 0;
  118. }
  119. INIT_COMPONENT_EXPORT(rt_hw_spiflash_init);
  120. #endif /* BOARD_USING_STORAGE_SPIFLASH */