drv_tim.c 15 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-10 zylx first version
  9. * 2020-06-16 thread-liu Porting for stm32mp1
  10. * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem
  11. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  12. * 2020-11-18 leizhixiong add STM32H7 series support
  13. */
  14. #include <rtdevice.h>
  15. #include "drv_config.h"
  16. //#define DRV_DEBUG
  17. #define LOG_TAG "drv.tim"
  18. #include <drv_log.h>
  19. /* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
  20. void stm32_tim_pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
  21. {
  22. rt_uint32_t flatency = 0;
  23. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  24. RT_ASSERT(pclk1_doubler != RT_NULL);
  25. RT_ASSERT(pclk1_doubler != RT_NULL);
  26. HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
  27. *pclk1_doubler = 1;
  28. *pclk2_doubler = 1;
  29. #if defined(SOC_SERIES_STM32MP1)
  30. if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
  31. {
  32. *pclk1_doubler = 2;
  33. }
  34. if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
  35. {
  36. *pclk2_doubler = 2;
  37. }
  38. #else
  39. if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
  40. {
  41. *pclk1_doubler = 2;
  42. }
  43. #if !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0))
  44. if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
  45. {
  46. *pclk2_doubler = 2;
  47. }
  48. #endif
  49. #endif
  50. }
  51. #ifdef BSP_USING_TIM
  52. enum
  53. {
  54. #ifdef BSP_USING_TIM1
  55. TIM1_INDEX,
  56. #endif
  57. #ifdef BSP_USING_TIM2
  58. TIM2_INDEX,
  59. #endif
  60. #ifdef BSP_USING_TIM3
  61. TIM3_INDEX,
  62. #endif
  63. #ifdef BSP_USING_TIM4
  64. TIM4_INDEX,
  65. #endif
  66. #ifdef BSP_USING_TIM5
  67. TIM5_INDEX,
  68. #endif
  69. #ifdef BSP_USING_TIM6
  70. TIM6_INDEX,
  71. #endif
  72. #ifdef BSP_USING_TIM7
  73. TIM7_INDEX,
  74. #endif
  75. #ifdef BSP_USING_TIM8
  76. TIM8_INDEX,
  77. #endif
  78. #ifdef BSP_USING_TIM9
  79. TIM9_INDEX,
  80. #endif
  81. #ifdef BSP_USING_TIM10
  82. TIM10_INDEX,
  83. #endif
  84. #ifdef BSP_USING_TIM11
  85. TIM11_INDEX,
  86. #endif
  87. #ifdef BSP_USING_TIM12
  88. TIM12_INDEX,
  89. #endif
  90. #ifdef BSP_USING_TIM13
  91. TIM13_INDEX,
  92. #endif
  93. #ifdef BSP_USING_TIM14
  94. TIM14_INDEX,
  95. #endif
  96. #ifdef BSP_USING_TIM15
  97. TIM15_INDEX,
  98. #endif
  99. #ifdef BSP_USING_TIM16
  100. TIM16_INDEX,
  101. #endif
  102. #ifdef BSP_USING_TIM17
  103. TIM17_INDEX,
  104. #endif
  105. };
  106. struct stm32_hwtimer
  107. {
  108. rt_hwtimer_t time_device;
  109. TIM_HandleTypeDef tim_handle;
  110. IRQn_Type tim_irqn;
  111. char *name;
  112. };
  113. static struct stm32_hwtimer stm32_hwtimer_obj[] =
  114. {
  115. #ifdef BSP_USING_TIM1
  116. TIM1_CONFIG,
  117. #endif
  118. #ifdef BSP_USING_TIM2
  119. TIM2_CONFIG,
  120. #endif
  121. #ifdef BSP_USING_TIM3
  122. TIM3_CONFIG,
  123. #endif
  124. #ifdef BSP_USING_TIM4
  125. TIM4_CONFIG,
  126. #endif
  127. #ifdef BSP_USING_TIM5
  128. TIM5_CONFIG,
  129. #endif
  130. #ifdef BSP_USING_TIM6
  131. TIM6_CONFIG,
  132. #endif
  133. #ifdef BSP_USING_TIM7
  134. TIM7_CONFIG,
  135. #endif
  136. #ifdef BSP_USING_TIM8
  137. TIM8_CONFIG,
  138. #endif
  139. #ifdef BSP_USING_TIM9
  140. TIM9_CONFIG,
  141. #endif
  142. #ifdef BSP_USING_TIM10
  143. TIM10_CONFIG,
  144. #endif
  145. #ifdef BSP_USING_TIM11
  146. TIM11_CONFIG,
  147. #endif
  148. #ifdef BSP_USING_TIM12
  149. TIM12_CONFIG,
  150. #endif
  151. #ifdef BSP_USING_TIM13
  152. TIM13_CONFIG,
  153. #endif
  154. #ifdef BSP_USING_TIM14
  155. TIM14_CONFIG,
  156. #endif
  157. #ifdef BSP_USING_TIM15
  158. TIM15_CONFIG,
  159. #endif
  160. #ifdef BSP_USING_TIM16
  161. TIM16_CONFIG,
  162. #endif
  163. #ifdef BSP_USING_TIM17
  164. TIM17_CONFIG,
  165. #endif
  166. };
  167. static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
  168. {
  169. uint32_t prescaler_value = 0;
  170. uint32_t pclk1_doubler, pclk2_doubler;
  171. TIM_HandleTypeDef *tim = RT_NULL;
  172. struct stm32_hwtimer *tim_device = RT_NULL;
  173. RT_ASSERT(timer != RT_NULL);
  174. if (state)
  175. {
  176. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  177. tim_device = (struct stm32_hwtimer *)timer;
  178. stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  179. /* time init */
  180. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  181. if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
  182. #elif defined(SOC_SERIES_STM32L4)
  183. if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
  184. #elif defined(SOC_SERIES_STM32WB)
  185. if (tim->Instance == TIM16 || tim->Instance == TIM17)
  186. #elif defined(SOC_SERIES_STM32MP1)
  187. if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
  188. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7)
  189. if (0)
  190. #else
  191. #error "This driver has not supported this series yet!"
  192. #endif
  193. {
  194. #if !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0))
  195. prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler / 10000) - 1;
  196. #endif
  197. }
  198. else
  199. {
  200. prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
  201. }
  202. tim->Init.Period = 10000 - 1;
  203. tim->Init.Prescaler = prescaler_value;
  204. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  205. if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
  206. {
  207. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  208. }
  209. else
  210. {
  211. tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
  212. }
  213. tim->Init.RepetitionCounter = 0;
  214. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
  215. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  216. #endif
  217. if (HAL_TIM_Base_Init(tim) != HAL_OK)
  218. {
  219. LOG_E("%s init failed", tim_device->name);
  220. return;
  221. }
  222. else
  223. {
  224. /* set the TIMx priority */
  225. HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0);
  226. /* enable the TIMx global Interrupt */
  227. HAL_NVIC_EnableIRQ(tim_device->tim_irqn);
  228. /* clear update flag */
  229. __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE);
  230. /* enable update request source */
  231. __HAL_TIM_URS_ENABLE(tim);
  232. LOG_D("%s init success", tim_device->name);
  233. }
  234. }
  235. }
  236. static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
  237. {
  238. rt_err_t result = RT_EOK;
  239. TIM_HandleTypeDef *tim = RT_NULL;
  240. RT_ASSERT(timer != RT_NULL);
  241. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  242. /* set tim cnt */
  243. __HAL_TIM_SET_COUNTER(tim, 0);
  244. /* set tim arr */
  245. __HAL_TIM_SET_AUTORELOAD(tim, t - 1);
  246. if (opmode == HWTIMER_MODE_ONESHOT)
  247. {
  248. /* set timer to single mode */
  249. tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
  250. }
  251. else
  252. {
  253. tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
  254. }
  255. /* start timer */
  256. if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
  257. {
  258. LOG_E("TIM start failed");
  259. result = -RT_ERROR;
  260. }
  261. return result;
  262. }
  263. static void timer_stop(rt_hwtimer_t *timer)
  264. {
  265. TIM_HandleTypeDef *tim = RT_NULL;
  266. RT_ASSERT(timer != RT_NULL);
  267. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  268. /* stop timer */
  269. HAL_TIM_Base_Stop_IT(tim);
  270. /* set tim cnt */
  271. __HAL_TIM_SET_COUNTER(tim, 0);
  272. }
  273. static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
  274. {
  275. TIM_HandleTypeDef *tim = RT_NULL;
  276. rt_err_t result = -RT_ERROR;
  277. uint32_t pclk1_doubler, pclk2_doubler;
  278. RT_ASSERT(timer != RT_NULL);
  279. RT_ASSERT(arg != RT_NULL);
  280. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  281. switch (cmd)
  282. {
  283. case HWTIMER_CTRL_FREQ_SET:
  284. {
  285. rt_uint32_t freq;
  286. rt_uint16_t val;
  287. /* set timer frequence */
  288. freq = *((rt_uint32_t *)arg);
  289. stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  290. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  291. if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
  292. #elif defined(SOC_SERIES_STM32L4)
  293. if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
  294. #elif defined(SOC_SERIES_STM32WB)
  295. if (tim->Instance == TIM16 || tim->Instance == TIM17)
  296. #elif defined(SOC_SERIES_STM32MP1)
  297. if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
  298. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7)
  299. if (0)
  300. #else
  301. #error "This driver has not supported this series yet!"
  302. #endif
  303. {
  304. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  305. val = HAL_RCC_GetPCLK2Freq() * pclk2_doubler / freq;
  306. #endif
  307. }
  308. else
  309. {
  310. val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq;
  311. }
  312. __HAL_TIM_SET_PRESCALER(tim, val - 1);
  313. /* Update frequency value */
  314. tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
  315. result = RT_EOK;
  316. }
  317. break;
  318. default:
  319. {
  320. result = -RT_EINVAL;
  321. }
  322. break;
  323. }
  324. return result;
  325. }
  326. static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
  327. {
  328. TIM_HandleTypeDef *tim = RT_NULL;
  329. RT_ASSERT(timer != RT_NULL);
  330. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  331. return tim->Instance->CNT;
  332. }
  333. static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
  334. static const struct rt_hwtimer_ops _ops =
  335. {
  336. .init = timer_init,
  337. .start = timer_start,
  338. .stop = timer_stop,
  339. .count_get = timer_counter_get,
  340. .control = timer_ctrl,
  341. };
  342. #ifdef BSP_USING_TIM2
  343. void TIM2_IRQHandler(void)
  344. {
  345. /* enter interrupt */
  346. rt_interrupt_enter();
  347. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
  348. /* leave interrupt */
  349. rt_interrupt_leave();
  350. }
  351. #endif
  352. #ifdef BSP_USING_TIM3
  353. void TIM3_IRQHandler(void)
  354. {
  355. /* enter interrupt */
  356. rt_interrupt_enter();
  357. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
  358. /* leave interrupt */
  359. rt_interrupt_leave();
  360. }
  361. #endif
  362. #ifdef BSP_USING_TIM4
  363. void TIM4_IRQHandler(void)
  364. {
  365. /* enter interrupt */
  366. rt_interrupt_enter();
  367. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
  368. /* leave interrupt */
  369. rt_interrupt_leave();
  370. }
  371. #endif
  372. #ifdef BSP_USING_TIM5
  373. void TIM5_IRQHandler(void)
  374. {
  375. /* enter interrupt */
  376. rt_interrupt_enter();
  377. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
  378. /* leave interrupt */
  379. rt_interrupt_leave();
  380. }
  381. #endif
  382. #ifdef BSP_USING_TIM7
  383. void TIM7_IRQHandler(void)
  384. {
  385. /* enter interrupt */
  386. rt_interrupt_enter();
  387. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM7_INDEX].tim_handle);
  388. /* leave interrupt */
  389. rt_interrupt_leave();
  390. }
  391. #endif
  392. #ifdef BSP_USING_TIM11
  393. void TIM1_TRG_COM_TIM11_IRQHandler(void)
  394. {
  395. /* enter interrupt */
  396. rt_interrupt_enter();
  397. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
  398. /* leave interrupt */
  399. rt_interrupt_leave();
  400. }
  401. #endif
  402. #ifdef BSP_USING_TIM13
  403. void TIM8_UP_TIM13_IRQHandler(void)
  404. {
  405. /* enter interrupt */
  406. rt_interrupt_enter();
  407. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
  408. /* leave interrupt */
  409. rt_interrupt_leave();
  410. }
  411. #endif
  412. #ifdef BSP_USING_TIM14
  413. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  414. void TIM8_TRG_COM_TIM14_IRQHandler(void)
  415. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  416. void TIM14_IRQHandler(void)
  417. #endif
  418. {
  419. /* enter interrupt */
  420. rt_interrupt_enter();
  421. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
  422. /* leave interrupt */
  423. rt_interrupt_leave();
  424. }
  425. #endif
  426. #ifdef BSP_USING_TIM15
  427. void TIM1_BRK_TIM15_IRQHandler(void)
  428. {
  429. /* enter interrupt */
  430. rt_interrupt_enter();
  431. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
  432. /* leave interrupt */
  433. rt_interrupt_leave();
  434. }
  435. #endif
  436. #ifdef BSP_USING_TIM16
  437. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
  438. void TIM1_UP_TIM16_IRQHandler(void)
  439. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  440. void TIM16_IRQHandler(void)
  441. #endif
  442. {
  443. /* enter interrupt */
  444. rt_interrupt_enter();
  445. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
  446. /* leave interrupt */
  447. rt_interrupt_leave();
  448. }
  449. #endif
  450. #ifdef BSP_USING_TIM17
  451. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
  452. void TIM1_TRG_COM_TIM17_IRQHandler(void)
  453. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  454. void TIM17_IRQHandler(void)
  455. #endif
  456. {
  457. /* enter interrupt */
  458. rt_interrupt_enter();
  459. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
  460. /* leave interrupt */
  461. rt_interrupt_leave();
  462. }
  463. #endif
  464. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  465. {
  466. #ifdef BSP_USING_TIM2
  467. if (htim->Instance == TIM2)
  468. {
  469. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
  470. }
  471. #endif
  472. #ifdef BSP_USING_TIM3
  473. if (htim->Instance == TIM3)
  474. {
  475. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
  476. }
  477. #endif
  478. #ifdef BSP_USING_TIM4
  479. if (htim->Instance == TIM4)
  480. {
  481. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
  482. }
  483. #endif
  484. #ifdef BSP_USING_TIM5
  485. if (htim->Instance == TIM5)
  486. {
  487. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
  488. }
  489. #endif
  490. #ifdef BSP_USING_TIM7
  491. if (htim->Instance == TIM7)
  492. {
  493. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM7_INDEX].time_device);
  494. }
  495. #endif
  496. #ifdef BSP_USING_TIM11
  497. if (htim->Instance == TIM11)
  498. {
  499. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
  500. }
  501. #endif
  502. #ifdef BSP_USING_TIM13
  503. if (htim->Instance == TIM13)
  504. {
  505. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
  506. }
  507. #endif
  508. #ifdef BSP_USING_TIM14
  509. if (htim->Instance == TIM14)
  510. {
  511. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
  512. }
  513. #endif
  514. #ifdef BSP_USING_TIM15
  515. if (htim->Instance == TIM15)
  516. {
  517. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
  518. }
  519. #endif
  520. #ifdef BSP_USING_TIM16
  521. if (htim->Instance == TIM16)
  522. {
  523. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
  524. }
  525. #endif
  526. #ifdef BSP_USING_TIM17
  527. if (htim->Instance == TIM17)
  528. {
  529. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
  530. }
  531. #endif
  532. }
  533. static int stm32_hwtimer_init(void)
  534. {
  535. int i = 0;
  536. int result = RT_EOK;
  537. for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
  538. {
  539. stm32_hwtimer_obj[i].time_device.info = &_info;
  540. stm32_hwtimer_obj[i].time_device.ops = &_ops;
  541. if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device,
  542. stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
  543. {
  544. LOG_D("%s register success", stm32_hwtimer_obj[i].name);
  545. }
  546. else
  547. {
  548. LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
  549. result = -RT_ERROR;
  550. }
  551. }
  552. return result;
  553. }
  554. INIT_BOARD_EXPORT(stm32_hwtimer_init);
  555. #endif /* BSP_USING_TIM */