context_gcc.S 1.3 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018/10/28 Bernard The unify RISC-V porting implementation
  9. * 2018/12/27 Jesven Add SMP support
  10. * 2021/02/02 lizhirui Add userspace support
  11. */
  12. #define __ASSEMBLY__
  13. #include "cpuport.h"
  14. #include "stackframe.h"
  15. .globl rt_hw_context_switch_to
  16. rt_hw_context_switch_to:
  17. LOAD sp, (a0)
  18. la s0, rt_current_thread
  19. LOAD s1, (s0)
  20. #ifdef RT_USING_USERSPACE
  21. mv a0, s1
  22. jal lwp_mmu_switch
  23. #endif
  24. RESTORE_ALL
  25. sret
  26. /*
  27. * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
  28. *
  29. * a0 --> from
  30. * a1 --> to
  31. */
  32. .globl rt_hw_context_switch
  33. rt_hw_context_switch:
  34. mv t2, sp
  35. li t0, 0x120//set SPIE and SPP = 1
  36. csrs sstatus, t0//if enter here,caller must be in system thread
  37. csrw sepc, ra//return address
  38. //saved from thread context
  39. SAVE_ALL
  40. STORE t2, 32 * REGBYTES(sp)//save user_sp
  41. STORE sp, (a0)
  42. //restore to thread context
  43. LOAD sp, (a1)
  44. la s0, rt_current_thread
  45. LOAD s1, (s0)
  46. #ifdef RT_USING_USERSPACE
  47. mv a0, s1
  48. jal lwp_mmu_switch
  49. #endif
  50. LOAD t0, 2 * REGBYTES(sp)
  51. andi t0, t0, 0x100
  52. beqz t0, ret_to_user
  53. RESTORE_ALL
  54. sret