ch56x_uart.c 8.7 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-07-15 Emuzit first version
  9. */
  10. #include <rthw.h>
  11. #include <rtdebug.h>
  12. #include <ipc/completion.h>
  13. #include <ipc/dataqueue.h>
  14. #ifdef RT_USING_SERIAL_V2
  15. #include <drivers/serial_v2.h>
  16. #else
  17. #include <drivers/serial.h>
  18. #endif
  19. #include <drivers/pin.h>
  20. #include "ch56x_sys.h"
  21. #include "ch56x_uart.h"
  22. #include "isr_sp.h"
  23. #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \
  24. !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3)
  25. #error "Please define at least one UARTx"
  26. #endif
  27. /* Type of irqn/rxd_pin/txd_pin are per uart driver perspective
  28. * to save some space, still compatible to RT api call, anyway.
  29. */
  30. struct serial_device
  31. {
  32. struct rt_serial_device parent;
  33. volatile struct uart_registers *reg_base;
  34. uint8_t irqn;
  35. uint8_t resv;
  36. uint8_t rxd_pin;
  37. uint8_t txd_pin;
  38. char *name;
  39. };
  40. #ifdef BSP_USING_UART0
  41. static struct serial_device serial_device_0 =
  42. {
  43. .reg_base = (struct uart_registers *)UART0_REG_BASE,
  44. .irqn = UART0_IRQn,
  45. #ifndef BSP_USING_UART0_PIN_ALT
  46. .rxd_pin = UART_RXD0_PIN,
  47. .txd_pin = UART_TXD0_PIN,
  48. #else
  49. .rxd_pin = UART_RXD0_ALT,
  50. .txd_pin = UART_TXD0_ALT,
  51. #endif
  52. .name = "uart0",
  53. };
  54. #endif
  55. #ifdef BSP_USING_UART1
  56. static struct serial_device serial_device_1 =
  57. {
  58. .reg_base = (struct uart_registers *)UART1_REG_BASE,
  59. .irqn = UART1_IRQn,
  60. .rxd_pin = UART_RXD1_PIN,
  61. .txd_pin = UART_TXD1_PIN,
  62. .name = "uart1",
  63. };
  64. #endif
  65. #ifdef BSP_USING_UART2
  66. static struct serial_device serial_device_2 =
  67. {
  68. .reg_base = (struct uart_registers *)UART2_REG_BASE,
  69. .irqn = UART2_IRQn,
  70. .rxd_pin = UART_RXD2_PIN,
  71. .txd_pin = UART_TXD2_PIN,
  72. .name = "uart2",
  73. };
  74. #endif
  75. #ifdef BSP_USING_UART3
  76. static struct serial_device serial_device_3 =
  77. {
  78. .reg_base = (struct uart_registers *)UART3_REG_BASE,
  79. .irqn = UART3_IRQn,
  80. .rxd_pin = UART_RXD3_PIN,
  81. .txd_pin = UART_TXD3_PIN,
  82. .name = "uart3",
  83. };
  84. #endif
  85. static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  86. {
  87. struct serial_device *serial_device = (struct serial_device *)serial;
  88. volatile struct uart_registers *uxreg = serial_device->reg_base;
  89. union _uart_fcr fcr;
  90. union _uart_lcr lcr;
  91. uint32_t x;
  92. x = 10 * sys_hclk_get() / 8 / cfg->baud_rate;
  93. x = (x + 5) / 10;
  94. uxreg->DL = x;
  95. uxreg->DIV = 1;
  96. lcr.reg = 0;
  97. switch (cfg->data_bits)
  98. {
  99. case DATA_BITS_5:
  100. lcr.word_sz = LCR_DATA_BITS_5;
  101. break;
  102. case DATA_BITS_6:
  103. lcr.word_sz = LCR_DATA_BITS_6;
  104. break;
  105. case DATA_BITS_7:
  106. lcr.word_sz = LCR_DATA_BITS_7;
  107. break;
  108. case DATA_BITS_8:
  109. default:
  110. lcr.word_sz = LCR_DATA_BITS_8;
  111. break;
  112. }
  113. switch (cfg->stop_bits)
  114. {
  115. case STOP_BITS_2:
  116. lcr.stop_bit = LCR_STOP_BITS_2;
  117. break;
  118. case STOP_BITS_1:
  119. default:
  120. lcr.stop_bit = LCR_STOP_BITS_1;
  121. break;
  122. }
  123. switch (cfg->parity)
  124. {
  125. case PARITY_ODD:
  126. lcr.par_mod = LCR_PARITY_ODD;
  127. lcr.par_en = 1;
  128. break;
  129. case PARITY_EVEN:
  130. lcr.par_mod = LCR_PARITY_EVEN;
  131. lcr.par_en = 1;
  132. break;
  133. case PARITY_NONE:
  134. default:
  135. lcr.par_en = 0;
  136. break;
  137. }
  138. uxreg->LCR.reg = lcr.reg;
  139. fcr.reg = RB_FCR_FIFO_EN | RB_FCR_RX_FIFO_CLR | RB_FCR_TX_FIFO_CLR;
  140. fcr.fifo_trig = UART_1BYTE_TRIG;
  141. uxreg->FCR.reg = fcr.reg;
  142. /* TXD pin output enable */
  143. uxreg->IER.txd_en = 1;
  144. return RT_EOK;
  145. }
  146. static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *args)
  147. {
  148. struct serial_device *serial_device = (struct serial_device *)serial;
  149. volatile struct uart_registers *uxreg = serial_device->reg_base;
  150. switch (cmd)
  151. {
  152. case RT_DEVICE_CTRL_CLR_INT:
  153. uxreg->IER.recv_rdy = 0;
  154. uxreg->IER.line_stat = 0;
  155. uxreg->IER.thr_empty = 0;
  156. rt_hw_interrupt_mask(serial_device->irqn);
  157. break;
  158. case RT_DEVICE_CTRL_SET_INT:
  159. uxreg->FCR.fifo_trig = UART_1BYTE_TRIG;
  160. uxreg->MCR.int_oe = 1;
  161. uxreg->IER.recv_rdy = 1;
  162. uxreg->IER.line_stat = 1;
  163. if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
  164. {
  165. uxreg->IER.thr_empty = 1;
  166. }
  167. rt_hw_interrupt_umask(serial_device->irqn);
  168. break;
  169. default:
  170. break;
  171. }
  172. return RT_EOK;
  173. }
  174. static int uart_putc(struct rt_serial_device *serial, char ch)
  175. {
  176. struct serial_device *serial_device = (struct serial_device *)serial;
  177. volatile struct uart_registers *uxreg = serial_device->reg_base;
  178. if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
  179. {
  180. if (uxreg->TFC >= UART_FIFO_SIZE)
  181. return -1;
  182. }
  183. else
  184. {
  185. while (uxreg->TFC >= UART_FIFO_SIZE)
  186. {
  187. if (rt_thread_self() && rt_interrupt_get_nest() == 0)
  188. rt_thread_yield();
  189. }
  190. }
  191. uxreg->THR = ch;
  192. return 1;
  193. }
  194. static int uart_getc(struct rt_serial_device *serial)
  195. {
  196. struct serial_device *serial_device = (struct serial_device *)serial;
  197. volatile struct uart_registers *uxreg = serial_device->reg_base;
  198. /* UART_II_RECV_RDY is cleared by reading RBR */
  199. return (uxreg->RFC > 0) ? uxreg->RBR : -1;
  200. }
  201. static const struct rt_uart_ops uart_ops =
  202. {
  203. .configure = uart_configure,
  204. .control = uart_control,
  205. .putc = uart_putc,
  206. .getc = uart_getc,
  207. .dma_transmit = RT_NULL,
  208. };
  209. int rt_hw_uart_init(void)
  210. {
  211. struct serial_device *devices[4];
  212. /* Note: HCLK should be at least 8MHz for default 115200 baud to work */
  213. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  214. int n = 0;
  215. #ifdef BSP_USING_UART3
  216. devices[n++] = &serial_device_3;
  217. #endif
  218. #ifdef BSP_USING_UART2
  219. devices[n++] = &serial_device_2;
  220. #endif
  221. #ifdef BSP_USING_UART1
  222. devices[n++] = &serial_device_1;
  223. #endif
  224. #ifdef BSP_USING_UART0
  225. devices[n++] = &serial_device_0;
  226. #endif
  227. while (--n >= 0)
  228. {
  229. uint32_t flag;
  230. struct serial_device *serial = devices[n];
  231. serial->parent.ops = &uart_ops;
  232. serial->parent.config = config;
  233. rt_pin_mode(serial->txd_pin, PIN_MODE_OUTPUT);
  234. rt_pin_mode(serial->rxd_pin, PIN_MODE_INPUT_PULLUP);
  235. sys_clk_off_by_irqn(serial->irqn, SYS_SLP_CLK_ON);
  236. flag = RT_DEVICE_FLAG_RDWR |
  237. RT_DEVICE_FLAG_STREAM | // for converting '\n'
  238. RT_DEVICE_FLAG_INT_TX |
  239. RT_DEVICE_FLAG_INT_RX ;
  240. rt_hw_serial_register(&serial->parent, serial->name, flag, RT_NULL);
  241. /* rt_serial_open => uart_control with RT_DEVICE_CTRL_SET_INT */
  242. }
  243. return 0;
  244. }
  245. static void _uart_isr_common(struct serial_device *serial_device)
  246. {
  247. struct rt_serial_device *serial = &serial_device->parent;
  248. volatile struct uart_registers *uxreg = serial_device->reg_base;
  249. switch (uxreg->IIR.int_mask)
  250. {
  251. case UART_II_RECV_TOUT:
  252. /* FIXME: It's a bad idea to read RBR to clear UART_II_RECV_TOUT.
  253. * Race condition may happen that actual rx data is dropped.
  254. */
  255. if (uxreg->RFC == 0)
  256. {
  257. uxreg->RBR;
  258. //rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_TIMEOUT);
  259. break;
  260. }
  261. /* pass through as if UART_II_RECV_RDY */
  262. case UART_II_RECV_RDY:
  263. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  264. break;
  265. case UART_II_THR_EMPTY:
  266. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  267. break;
  268. case UART_II_LINE_STAT:
  269. uxreg->LSR;
  270. break;
  271. case UART_II_MODEM_CHG:
  272. uxreg->MSR;
  273. break;
  274. case UART_II_SLV_ADDR:
  275. uxreg->IIR;
  276. break;
  277. default:
  278. break;
  279. }
  280. }
  281. #ifdef BSP_USING_UART0
  282. void uart0_irq_handler(void) __attribute__((interrupt()));
  283. void uart0_irq_handler(void)
  284. {
  285. isr_sp_enter();
  286. rt_interrupt_enter();
  287. _uart_isr_common(&serial_device_0);
  288. rt_interrupt_leave();
  289. isr_sp_leave();
  290. }
  291. #endif
  292. #ifdef BSP_USING_UART1
  293. void uart1_irq_handler(void) __attribute__((interrupt()));
  294. void uart1_irq_handler(void)
  295. {
  296. isr_sp_enter();
  297. rt_interrupt_enter();
  298. _uart_isr_common(&serial_device_1);
  299. rt_interrupt_leave();
  300. isr_sp_leave();
  301. }
  302. #endif
  303. #ifdef BSP_USING_UART2
  304. void uart2_irq_handler(void) __attribute__((interrupt()));
  305. void uart2_irq_handler(void)
  306. {
  307. isr_sp_enter();
  308. rt_interrupt_enter();
  309. _uart_isr_common(&serial_device_2);
  310. rt_interrupt_leave();
  311. isr_sp_leave();
  312. }
  313. #endif
  314. #ifdef BSP_USING_UART3
  315. void uart3_irq_handler(void) __attribute__((interrupt()));
  316. void uart3_irq_handler(void)
  317. {
  318. isr_sp_enter();
  319. rt_interrupt_enter();
  320. _uart_isr_common(&serial_device_3);
  321. rt_interrupt_leave();
  322. isr_sp_leave();
  323. }
  324. #endif