context_rvds.S 2.6 KB

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  1. ;/*
  2. ; * File : context_rvds.S
  3. ; * This file is part of RT-Thread RTOS
  4. ; * COPYRIGHT (C) 2006, RT-Thread Development Team
  5. ; *
  6. ; * The license and distribution terms for this file may be
  7. ; * found in the file LICENSE in this distribution or at
  8. ; * http://www.rt-thread.org/license/LICENSE
  9. ; *
  10. ; * Change Logs:
  11. ; * Date Author Notes
  12. ; * 2009-01-20 Bernard first version
  13. ; */
  14. NOINT EQU 0xc0 ; disable interrupt in psr
  15. AREA |.text|, CODE, READONLY, ALIGN=2
  16. ARM
  17. REQUIRE8
  18. PRESERVE8
  19. ;/*
  20. ; * rt_base_t rt_hw_interrupt_disable();
  21. ; */
  22. rt_hw_interrupt_disable PROC
  23. EXPORT rt_hw_interrupt_disable
  24. MRS r0, cpsr
  25. ORR r1, r0, #NOINT
  26. MSR cpsr_c, r1
  27. BX lr
  28. ENDP
  29. ;/*
  30. ; * void rt_hw_interrupt_enable(rt_base_t level);
  31. ; */
  32. rt_hw_interrupt_enable PROC
  33. EXPORT rt_hw_interrupt_enable
  34. MSR cpsr_c, r0
  35. BX lr
  36. ENDP
  37. ;/*
  38. ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
  39. ; * r0 --> from
  40. ; * r1 --> to
  41. ; */
  42. rt_hw_context_switch PROC
  43. EXPORT rt_hw_context_switch
  44. STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
  45. STMFD sp!, {r0-r12, lr} ; push lr & register file
  46. MRS r4, cpsr
  47. TST lr, #0x01
  48. BEQ _ARM_MODE
  49. ORR r4, r4, #0x20 ; it's thumb code
  50. _ARM_MODE
  51. STMFD sp!, {r4} ; push cpsr
  52. STR sp, [r0] ; store sp in preempted tasks TCB
  53. LDR sp, [r1] ; get new task stack pointer
  54. LDMFD sp!, {r4} ; pop new task cpsr to spsr
  55. MSR spsr_cxsf, r4
  56. BIC r4, r4, #0x20 ; must be ARM mode
  57. MSR cpsr_cxsf, r4
  58. LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
  59. ENDP
  60. ;/*
  61. ; * void rt_hw_context_switch_to(rt_uint32 to);
  62. ; * r0 --> to
  63. ; */
  64. rt_hw_context_switch_to PROC
  65. EXPORT rt_hw_context_switch_to
  66. LDR sp, [r0] ; get new task stack pointer
  67. LDMFD sp!, {r4} ; pop new task cpsr to spsr
  68. MSR spsr_cxsf, r4
  69. BIC r4, r4, #0x20 ; must be ARM mode
  70. MSR cpsr_cxsf, r4
  71. LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
  72. ENDP
  73. ;/*
  74. ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
  75. ; */
  76. IMPORT rt_thread_switch_interrput_flag
  77. IMPORT rt_interrupt_from_thread
  78. IMPORT rt_interrupt_to_thread
  79. rt_hw_context_switch_interrupt PROC
  80. EXPORT rt_hw_context_switch_interrupt
  81. LDR r2, =rt_thread_switch_interrput_flag
  82. LDR r3, [r2]
  83. CMP r3, #1
  84. BEQ _reswitch
  85. MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
  86. STR r3, [r2]
  87. LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
  88. STR r0, [r2]
  89. _reswitch
  90. LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
  91. STR r1, [r2]
  92. BX lr
  93. ENDP
  94. END