fsl_spdif.c 21 KB

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  1. /*
  2. * The Clear BSD License
  3. * Copyright (c) 2017, NXP Semiconductor, Inc.
  4. * All rights reserved.
  5. *
  6. *
  7. * Redistribution and use in source and binary forms, with or without modification,
  8. * are permitted (subject to the limitations in the disclaimer below) provided
  9. * that the following conditions are met:
  10. *
  11. * o Redistributions of source code must retain the above copyright notice, this list
  12. * of conditions and the following disclaimer.
  13. *
  14. * o Redistributions in binary form must reproduce the above copyright notice, this
  15. * list of conditions and the following disclaimer in the documentation and/or
  16. * other materials provided with the distribution.
  17. *
  18. * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  24. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  27. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #include "fsl_spdif.h"
  35. /* Component ID definition, used by tools. */
  36. #ifndef FSL_COMPONENT_ID
  37. #define FSL_COMPONENT_ID "platform.drivers.spdif"
  38. #endif
  39. /*******************************************************************************
  40. * Definitations
  41. ******************************************************************************/
  42. enum _spdif_transfer_state
  43. {
  44. kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */
  45. kSPDIF_Idle, /*!< Transfer is done. */
  46. kSPDIF_Error /*!< Transfer error occured. */
  47. };
  48. /*! @brief Typedef for spdif tx interrupt handler. */
  49. typedef void (*spdif_isr_t)(SPDIF_Type *base, spdif_handle_t *handle);
  50. /*******************************************************************************
  51. * Prototypes
  52. ******************************************************************************/
  53. /*!
  54. * @brief Get the instance number for SPDIF.
  55. *
  56. * @param base SPDIF base pointer.
  57. */
  58. uint32_t SPDIF_GetInstance(SPDIF_Type *base);
  59. /*******************************************************************************
  60. * Variables
  61. ******************************************************************************/
  62. /* Base pointer array */
  63. static SPDIF_Type *const s_spdifBases[] = SPDIF_BASE_PTRS;
  64. /*! @brief SPDIF handle pointer */
  65. spdif_handle_t *s_spdifHandle[ARRAY_SIZE(s_spdifBases)][2];
  66. /* IRQ number array */
  67. static const IRQn_Type s_spdifIRQ[] = SPDIF_IRQS;
  68. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  69. /* Clock name array */
  70. static const clock_ip_name_t s_spdifClock[] = SPDIF_CLOCKS;
  71. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  72. /*! @brief Pointer to IRQ handler for each instance. */
  73. static spdif_isr_t s_spdifTxIsr;
  74. /*! @brief Pointer to IRQ handler for each instance. */
  75. static spdif_isr_t s_spdifRxIsr;
  76. /*! @brief Used for spdif gain */
  77. static uint8_t s_spdif_gain[8] = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U};
  78. static uint8_t s_spdif_tx_watermark[4] = {16, 12, 8, 4};
  79. static uint8_t s_spdif_rx_watermark[4] = {1, 4, 8, 16};
  80. /*******************************************************************************
  81. * Code
  82. ******************************************************************************/
  83. uint32_t SPDIF_GetInstance(SPDIF_Type *base)
  84. {
  85. uint32_t instance;
  86. /* Find the instance index from base address mappings. */
  87. for (instance = 0; instance < ARRAY_SIZE(s_spdifBases); instance++)
  88. {
  89. if (s_spdifBases[instance] == base)
  90. {
  91. break;
  92. }
  93. }
  94. assert(instance < ARRAY_SIZE(s_spdifBases));
  95. return instance;
  96. }
  97. void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config)
  98. {
  99. uint32_t val = 0;
  100. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  101. /* Enable the SPDIF clock */
  102. CLOCK_EnableClock(s_spdifClock[SPDIF_GetInstance(base)]);
  103. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  104. /* Reset the internal logic */
  105. base->SCR |= SPDIF_SCR_SOFT_RESET_MASK;
  106. /* Waiting for reset finish */
  107. while (base->SCR & SPDIF_SCR_SOFT_RESET_MASK)
  108. {
  109. }
  110. /* Setting the SPDIF settings */
  111. base->SCR = SPDIF_SCR_RXFIFOFULL_SEL(config->rxFullSelect) | SPDIF_SCR_RXAUTOSYNC(config->isRxAutoSync) |
  112. SPDIF_SCR_TXAUTOSYNC(config->isRxAutoSync) | SPDIF_SCR_TXFIFOEMPTY_SEL(config->txFullSelect) |
  113. SPDIF_SCR_TXFIFO_CTRL(1U) | SPDIF_SCR_VALCTRL(config->validityConfig) |
  114. SPDIF_SCR_TXSEL(config->txSource) | SPDIF_SCR_USRC_SEL(config->uChannelSrc);
  115. /* Set DPLL clock source */
  116. base->SRPC = SPDIF_SRPC_CLKSRC_SEL(config->DPLLClkSource) | SPDIF_SRPC_GAINSEL(config->gain);
  117. /* Set SPDIF tx clock source */
  118. val = base->STC & ~SPDIF_STC_TXCLK_SOURCE_MASK;
  119. val |= SPDIF_STC_TXCLK_SOURCE(config->txClkSource);
  120. base->STC = val;
  121. }
  122. void SPDIF_Deinit(SPDIF_Type *base)
  123. {
  124. SPDIF_TxEnable(base, false);
  125. SPDIF_RxEnable(base, false);
  126. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  127. CLOCK_DisableClock(s_spdifClock[SPDIF_GetInstance(base)]);
  128. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  129. }
  130. void SPDIF_GetDefaultConfig(spdif_config_t *config)
  131. {
  132. config->isTxAutoSync = true;
  133. config->isRxAutoSync = true;
  134. config->DPLLClkSource = 1;
  135. config->txClkSource = 1;
  136. config->rxFullSelect = kSPDIF_RxFull8Samples;
  137. config->txFullSelect = kSPDIF_TxEmpty8Samples;
  138. config->uChannelSrc = kSPDIF_UChannelFromTx;
  139. config->txSource = kSPDIF_txNormal;
  140. config->validityConfig = kSPDIF_validityFlagAlwaysClear;
  141. config->gain = kSPDIF_GAIN_8;
  142. }
  143. void SPDIF_TxEnable(SPDIF_Type *base, bool enable)
  144. {
  145. uint32_t val = 0;
  146. if (enable)
  147. {
  148. /* Open Tx FIFO */
  149. val = base->SCR & (~SPDIF_SCR_TXFIFO_CTRL_MASK);
  150. val |= SPDIF_SCR_TXFIFO_CTRL(1U);
  151. base->SCR = val;
  152. /* Enable transfer clock */
  153. base->STC |= SPDIF_STC_TX_ALL_CLK_EN_MASK;
  154. }
  155. else
  156. {
  157. base->SCR &= ~(SPDIF_SCR_TXFIFO_CTRL_MASK | SPDIF_SCR_TXSEL_MASK);
  158. /* Disable transfer clock */
  159. base->STC &= ~SPDIF_STC_TX_ALL_CLK_EN_MASK;
  160. }
  161. }
  162. void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz)
  163. {
  164. uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64);
  165. uint32_t mod = sourceClockFreq_Hz % (sampleRate_Hz * 64);
  166. uint32_t val = 0;
  167. uint8_t clockSource = (((base->STC) & SPDIF_STC_TXCLK_SOURCE_MASK) >> SPDIF_STC_TXCLK_SOURCE_SHIFT);
  168. /* Compute the nearest divider */
  169. if (mod > ((sampleRate_Hz * 64) / 2))
  170. {
  171. clkDiv += 1U;
  172. }
  173. /* If use divided systeme clock */
  174. if (clockSource == 5U)
  175. {
  176. if (clkDiv > 256)
  177. {
  178. val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK));
  179. val |= SPDIF_STC_SYSCLK_DF(clkDiv / 128U - 1U) | SPDIF_STC_TXCLK_DF(127U);
  180. base->STC = val;
  181. }
  182. else
  183. {
  184. val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK));
  185. val |= SPDIF_STC_SYSCLK_DF(1U) | SPDIF_STC_TXCLK_DF(clkDiv - 1U);
  186. base->STC = val;
  187. }
  188. }
  189. else
  190. {
  191. /* Other clock only uses txclk div */
  192. val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK));
  193. val |= SPDIF_STC_TXCLK_DF(clkDiv - 1U);
  194. base->STC = val;
  195. }
  196. }
  197. uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz)
  198. {
  199. uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)];
  200. uint32_t measure = 0, sampleRate = 0;
  201. uint64_t temp = 0;
  202. /* Wait the DPLL locked */
  203. while ((base->SRPC & SPDIF_SRPC_LOCK_MASK) == 0U)
  204. {
  205. }
  206. /* Get the measure value */
  207. measure = base->SRFM;
  208. temp = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz;
  209. temp /= (uint64_t)(1024 * 1024 * 128 * gain);
  210. sampleRate = (uint32_t)temp;
  211. return sampleRate;
  212. }
  213. void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
  214. {
  215. assert(buffer);
  216. assert(size / 6U == 0U);
  217. uint32_t i = 0, j = 0, data = 0;
  218. while (i < size)
  219. {
  220. /* Wait until it can write data */
  221. while ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) == 0U)
  222. {
  223. }
  224. /* Write left channel data */
  225. for (j = 0; j < 3U; j++)
  226. {
  227. data |= ((uint32_t)(*buffer) << (j * 8U));
  228. buffer++;
  229. }
  230. SPDIF_WriteLeftData(base, data);
  231. /* Write right channel data */
  232. data = 0;
  233. for (j = 0; j < 3U; j++)
  234. {
  235. data |= ((uint32_t)(*buffer) << (j * 8U));
  236. buffer++;
  237. }
  238. SPDIF_WriteRightData(base, data);
  239. i += 6U;
  240. }
  241. }
  242. void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
  243. {
  244. assert(buffer);
  245. assert(size / 6U == 0U);
  246. uint32_t i = 0, j = 0, data = 0;
  247. while (i < size)
  248. {
  249. /* Wait until it can write data */
  250. while ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) == 0U)
  251. {
  252. }
  253. /* Write left channel data */
  254. data = SPDIF_ReadLeftData(base);
  255. for (j = 0; j < 3U; j++)
  256. {
  257. *buffer = ((data >> (j * 8U)) & 0xFFU);
  258. buffer++;
  259. }
  260. /* Write right channel data */
  261. data = SPDIF_ReadRightData(base);
  262. for (j = 0; j < 3U; j++)
  263. {
  264. *buffer = ((data >> (j * 8U)) & 0xFFU);
  265. buffer++;
  266. }
  267. i += 6U;
  268. }
  269. }
  270. void SPDIF_TransferTxCreateHandle(SPDIF_Type *base,
  271. spdif_handle_t *handle,
  272. spdif_transfer_callback_t callback,
  273. void *userData)
  274. {
  275. assert(handle);
  276. /* Zero the handle */
  277. memset(handle, 0, sizeof(*handle));
  278. s_spdifHandle[SPDIF_GetInstance(base)][0] = handle;
  279. handle->callback = callback;
  280. handle->userData = userData;
  281. handle->watermark =
  282. s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT];
  283. /* Set the isr pointer */
  284. s_spdifTxIsr = SPDIF_TransferTxHandleIRQ;
  285. /* Enable Tx irq */
  286. EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]);
  287. }
  288. void SPDIF_TransferRxCreateHandle(SPDIF_Type *base,
  289. spdif_handle_t *handle,
  290. spdif_transfer_callback_t callback,
  291. void *userData)
  292. {
  293. assert(handle);
  294. /* Zero the handle */
  295. memset(handle, 0, sizeof(*handle));
  296. s_spdifHandle[SPDIF_GetInstance(base)][1] = handle;
  297. handle->callback = callback;
  298. handle->userData = userData;
  299. handle->watermark =
  300. s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT];
  301. /* Set the isr pointer */
  302. s_spdifRxIsr = SPDIF_TransferRxHandleIRQ;
  303. /* Enable Rx irq */
  304. EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]);
  305. }
  306. status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)
  307. {
  308. assert(handle);
  309. /* Check if the queue is full */
  310. if (handle->spdifQueue[handle->queueUser].data)
  311. {
  312. return kStatus_SPDIF_QueueFull;
  313. }
  314. /* Add into queue */
  315. handle->transferSize[handle->queueUser] = xfer->dataSize;
  316. handle->spdifQueue[handle->queueUser].data = xfer->data;
  317. handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize;
  318. handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
  319. /* Set the state to busy */
  320. handle->state = kSPDIF_Busy;
  321. /* Enable interrupt */
  322. SPDIF_EnableInterrupts(base, kSPDIF_TxFIFOEmpty);
  323. /* Enable Tx transfer */
  324. SPDIF_TxEnable(base, true);
  325. return kStatus_Success;
  326. }
  327. status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)
  328. {
  329. assert(handle);
  330. /* Check if the queue is full */
  331. if (handle->spdifQueue[handle->queueUser].data)
  332. {
  333. return kStatus_SPDIF_QueueFull;
  334. }
  335. /* Add into queue */
  336. handle->transferSize[handle->queueUser] = xfer->dataSize;
  337. handle->spdifQueue[handle->queueUser].data = xfer->data;
  338. handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize;
  339. handle->spdifQueue[handle->queueUser].udata = xfer->udata;
  340. handle->spdifQueue[handle->queueUser].qdata = xfer->qdata;
  341. handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
  342. /* Set state to busy */
  343. handle->state = kSPDIF_Busy;
  344. /* Enable interrupt */
  345. SPDIF_EnableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull |
  346. kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange);
  347. /* Enable Rx transfer */
  348. SPDIF_RxEnable(base, true);
  349. return kStatus_Success;
  350. }
  351. status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
  352. {
  353. assert(handle);
  354. status_t status = kStatus_Success;
  355. if (handle->state != kSPDIF_Busy)
  356. {
  357. status = kStatus_NoTransferInProgress;
  358. }
  359. else
  360. {
  361. *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize);
  362. }
  363. return status;
  364. }
  365. status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
  366. {
  367. assert(handle);
  368. status_t status = kStatus_Success;
  369. if (handle->state != kSPDIF_Busy)
  370. {
  371. status = kStatus_NoTransferInProgress;
  372. }
  373. else
  374. {
  375. *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize);
  376. }
  377. return status;
  378. }
  379. void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle)
  380. {
  381. assert(handle);
  382. /* Use FIFO request interrupt and fifo error */
  383. SPDIF_DisableInterrupts(base, kSPDIF_TxFIFOEmpty);
  384. handle->state = kSPDIF_Idle;
  385. /* Clear the queue */
  386. memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE);
  387. handle->queueDriver = 0;
  388. handle->queueUser = 0;
  389. }
  390. void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle)
  391. {
  392. assert(handle);
  393. /* Disable interrupt */
  394. SPDIF_DisableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull |
  395. kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange);
  396. handle->state = kSPDIF_Idle;
  397. /* Clear the queue */
  398. memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE);
  399. handle->queueDriver = 0;
  400. handle->queueUser = 0;
  401. }
  402. void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
  403. {
  404. assert(handle);
  405. uint8_t *buffer = handle->spdifQueue[handle->queueDriver].data;
  406. uint8_t dataSize = 0;
  407. uint32_t i = 0, j = 0, data = 0;
  408. /* Do Transfer */
  409. if ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) && (base->SIE & kSPDIF_TxFIFOEmpty))
  410. {
  411. dataSize = handle->watermark;
  412. while (i < dataSize)
  413. {
  414. data = 0;
  415. /* Write left channel data */
  416. for (j = 0; j < 3U; j++)
  417. {
  418. data |= ((uint32_t)(*buffer) << (j * 8U));
  419. buffer++;
  420. }
  421. SPDIF_WriteLeftData(base, data);
  422. /* Write right channel data */
  423. data = 0;
  424. for (j = 0; j < 3U; j++)
  425. {
  426. data |= ((uint32_t)(*buffer) << (j * 8U));
  427. buffer++;
  428. }
  429. SPDIF_WriteRightData(base, data);
  430. i++;
  431. }
  432. handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U;
  433. handle->spdifQueue[handle->queueDriver].data += dataSize * 6U;
  434. /* If finished a blcok, call the callback function */
  435. if (handle->spdifQueue[handle->queueDriver].dataSize == 0U)
  436. {
  437. memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t));
  438. handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE;
  439. if (handle->callback)
  440. {
  441. (handle->callback)(base, handle, kStatus_SPDIF_TxIdle, handle->userData);
  442. }
  443. }
  444. /* If all data finished, just stop the transfer */
  445. if (handle->spdifQueue[handle->queueDriver].data == NULL)
  446. {
  447. SPDIF_TransferAbortSend(base, handle);
  448. }
  449. }
  450. }
  451. void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
  452. {
  453. assert(handle);
  454. uint8_t *buffer = NULL;
  455. uint8_t dataSize = 0;
  456. uint32_t i = 0, j = 0, data = 0;
  457. /* Handle Cnew flag */
  458. if (SPDIF_GetStatusFlag(base) & kSPDIF_RxControlChannelChange)
  459. {
  460. /* Clear the interrupt flag */
  461. SPDIF_ClearStatusFlags(base, SPDIF_SIE_CNEW_MASK);
  462. if (handle->callback)
  463. {
  464. (handle->callback)(base, handle, kStatus_SPDIF_RxCnew, handle->userData);
  465. }
  466. }
  467. /* Handle illegal symbol */
  468. if (SPDIF_GetStatusFlag(base) & kSPDIF_RxIllegalSymbol)
  469. {
  470. SPDIF_ClearStatusFlags(base, kSPDIF_RxIllegalSymbol);
  471. if (handle->callback)
  472. {
  473. (handle->callback)(base, handle, kStatus_SPDIF_RxIllegalSymbol, handle->userData);
  474. }
  475. }
  476. /* Handle Parity Bit Error */
  477. if (SPDIF_GetStatusFlag(base) & kSPDIF_RxParityBitError)
  478. {
  479. SPDIF_ClearStatusFlags(base, kSPDIF_RxParityBitError);
  480. if (handle->callback)
  481. {
  482. (handle->callback)(base, handle, kStatus_SPDIF_RxParityBitError, handle->userData);
  483. }
  484. }
  485. /* Handle DPlocked */
  486. if (SPDIF_GetStatusFlag(base) & kSPDIF_RxDPLLLocked)
  487. {
  488. SPDIF_ClearStatusFlags(base, kSPDIF_RxDPLLLocked);
  489. if (handle->callback)
  490. {
  491. (handle->callback)(base, handle, kStatus_SPDIF_RxDPLLLocked, handle->userData);
  492. }
  493. }
  494. /* Handle Q channel full flag */
  495. if ((SPDIF_GetStatusFlag(base) & kSPDIF_QChannelReceiveRegisterFull) &&
  496. (base->SIE & kSPDIF_QChannelReceiveRegisterFull))
  497. {
  498. buffer = handle->spdifQueue[handle->queueDriver].qdata;
  499. data = SPDIF_ReadQChannel(base);
  500. buffer[0] = data & 0xFFU;
  501. buffer[1] = (data >> 8U) & 0xFFU;
  502. buffer[2] = (data >> 16U) & 0xFFU;
  503. }
  504. /* Handle U channel full flag */
  505. if ((SPDIF_GetStatusFlag(base) & kSPDIF_UChannelReceiveRegisterFull) &&
  506. (base->SIE & kSPDIF_UChannelReceiveRegisterFull))
  507. {
  508. buffer = handle->spdifQueue[handle->queueDriver].udata;
  509. data = SPDIF_ReadUChannel(base);
  510. buffer[0] = data & 0xFFU;
  511. buffer[1] = (data >> 8U) & 0xFFU;
  512. buffer[2] = (data >> 16U) & 0xFFU;
  513. }
  514. /* Handle audio data transfer */
  515. if ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) && (base->SIE & kSPDIF_RxFIFOFull))
  516. {
  517. dataSize = handle->watermark;
  518. buffer = handle->spdifQueue[handle->queueDriver].data;
  519. while (i < dataSize)
  520. {
  521. /* Read left channel data */
  522. data = SPDIF_ReadLeftData(base);
  523. for (j = 0; j < 3U; j++)
  524. {
  525. *buffer = ((data >> (j * 8U)) & 0xFFU);
  526. buffer++;
  527. }
  528. /* Read right channel data */
  529. data = SPDIF_ReadRightData(base);
  530. for (j = 0; j < 3U; j++)
  531. {
  532. *buffer = ((data >> (j * 8U)) & 0xFFU);
  533. buffer++;
  534. }
  535. i++;
  536. }
  537. handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U;
  538. handle->spdifQueue[handle->queueDriver].data += dataSize * 6U;
  539. /* If finished a blcok, call the callback function */
  540. if (handle->spdifQueue[handle->queueDriver].dataSize == 0U)
  541. {
  542. memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t));
  543. handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE;
  544. if (handle->callback)
  545. {
  546. (handle->callback)(base, handle, kStatus_SPDIF_RxIdle, handle->userData);
  547. }
  548. }
  549. /* If all data finished, just stop the transfer */
  550. if (handle->spdifQueue[handle->queueDriver].data == NULL)
  551. {
  552. SPDIF_TransferAbortReceive(base, handle);
  553. }
  554. }
  555. }
  556. #if defined(SPDIF)
  557. void SPDIF_DriverIRQHandler(void)
  558. {
  559. if ((s_spdifHandle[0][0]) && s_spdifTxIsr)
  560. {
  561. s_spdifTxIsr(SPDIF, s_spdifHandle[0][0]);
  562. }
  563. if ((s_spdifHandle[0][1]) && s_spdifRxIsr)
  564. {
  565. s_spdifRxIsr(SPDIF, s_spdifHandle[0][1]);
  566. }
  567. /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
  568. exception return operation might vector to incorrect interrupt */
  569. #if defined __CORTEX_M && (__CORTEX_M == 4U)
  570. __DSB();
  571. #endif
  572. }
  573. #endif