fsl_usdhc.h 59 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505
  1. /*
  2. * The Clear BSD License
  3. * Copyright (c) 2016, Freescale Semiconductor, Inc.
  4. * Copyright 2016-2017 NXP
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without modification,
  8. * are permitted (subject to the limitations in the disclaimer below) provided
  9. * that the following conditions are met:
  10. *
  11. * o Redistributions of source code must retain the above copyright notice, this list
  12. * of conditions and the following disclaimer.
  13. *
  14. * o Redistributions in binary form must reproduce the above copyright notice, this
  15. * list of conditions and the following disclaimer in the documentation and/or
  16. * other materials provided with the distribution.
  17. *
  18. * o Neither the name of the copyright holder nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  24. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  27. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #ifndef _FSL_USDHC_H_
  35. #define _FSL_USDHC_H_
  36. #include "fsl_common.h"
  37. /*!
  38. * @addtogroup usdhc
  39. * @{
  40. */
  41. /******************************************************************************
  42. * Definitions.
  43. *****************************************************************************/
  44. /*! @name Driver version */
  45. /*@{*/
  46. /*! @brief Driver version 2.2.3. */
  47. #define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 3U))
  48. /*@}*/
  49. /*! @brief Maximum block count can be set one time */
  50. #define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT)
  51. /*! @brief USDHC status */
  52. enum _usdhc_status
  53. {
  54. kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */
  55. kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */
  56. kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */
  57. kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */
  58. kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */
  59. kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */
  60. kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */
  61. kStatus_USDHC_NotSupport = MAKE_STATUS(kStatusGroup_USDHC, 7U), /*!< not support */
  62. };
  63. /*! @brief Host controller capabilities flag mask */
  64. enum _usdhc_capability_flag
  65. {
  66. kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */
  67. kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */
  68. kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */
  69. kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */
  70. kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */
  71. kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */
  72. kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */
  73. /* Put additional two flags in HTCAPBLT_MBL's position. */
  74. kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */
  75. kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */
  76. /* sd version 3.0 new feature */
  77. kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */
  78. #if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE)
  79. kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */
  80. #else
  81. kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */
  82. #endif
  83. #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
  84. kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */
  85. #else
  86. kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */
  87. #endif
  88. };
  89. /*! @brief Wakeup event mask */
  90. enum _usdhc_wakeup_event
  91. {
  92. kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */
  93. kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */
  94. kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */
  95. kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert |
  96. kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */
  97. };
  98. /*! @brief Reset type mask */
  99. enum _usdhc_reset
  100. {
  101. kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */
  102. kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */
  103. kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */
  104. #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
  105. kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */
  106. #else
  107. kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */
  108. #endif
  109. kUSDHC_ResetsAll =
  110. (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */
  111. };
  112. /*! @brief Transfer flag mask */
  113. enum _usdhc_transfer_flag
  114. {
  115. kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */
  116. kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */
  117. kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */
  118. kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */
  119. kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */
  120. kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */
  121. kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */
  122. kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */
  123. kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */
  124. kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */
  125. kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */
  126. kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */
  127. kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */
  128. kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */
  129. kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */
  130. };
  131. /*! @brief Present status flag mask */
  132. enum _usdhc_present_status_flag
  133. {
  134. kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */
  135. kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */
  136. kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */
  137. kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */
  138. kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */
  139. kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */
  140. kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */
  141. kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */
  142. #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
  143. kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */
  144. kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */
  145. #else
  146. kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */
  147. kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */
  148. #endif
  149. kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */
  150. kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */
  151. kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT), /*!< Data0 line signal level */
  152. kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */
  153. kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */
  154. kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */
  155. kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */
  156. kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */
  157. kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */
  158. kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */
  159. };
  160. /*! @brief Interrupt status flag mask */
  161. enum _usdhc_interrupt_status_flag
  162. {
  163. kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */
  164. kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */
  165. kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */
  166. kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */
  167. kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */
  168. kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */
  169. kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */
  170. kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */
  171. kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */
  172. #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
  173. kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */
  174. kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */
  175. kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */
  176. #else
  177. kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */
  178. kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */
  179. kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */
  180. #endif
  181. kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */
  182. kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */
  183. kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */
  184. kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */
  185. kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */
  186. kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */
  187. kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */
  188. kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */
  189. kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */
  190. kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag |
  191. kUSDHC_CommandIndexErrorFlag), /*!< Command error */
  192. kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag |
  193. kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */
  194. kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */
  195. kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag |
  196. kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */
  197. kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */
  198. kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */
  199. kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag),
  200. kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag |
  201. kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */
  202. };
  203. /*! @brief Auto CMD12 error status flag mask */
  204. enum _usdhc_auto_command12_error_status_flag
  205. {
  206. kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */
  207. kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */
  208. kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */
  209. kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */
  210. kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */
  211. kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */
  212. };
  213. /*! @brief standard tuning flag */
  214. enum _usdhc_standard_tuning
  215. {
  216. #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
  217. kUSDHC_ExecuteTuning = 0U, /*!< not support */
  218. kUSDHC_TuningSampleClockSel = 0U, /*!< not support */
  219. #else
  220. kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */
  221. kUSDHC_TuningSampleClockSel =
  222. USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this bit is used
  223. select sampleing clock */
  224. #endif
  225. };
  226. /*! @brief ADMA error status flag mask */
  227. enum _usdhc_adma_error_status_flag
  228. {
  229. kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */
  230. kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */
  231. };
  232. /*!
  233. * @brief ADMA error state
  234. *
  235. * This state is the detail state when ADMA error has occurred.
  236. */
  237. enum _usdhc_adma_error_state
  238. {
  239. kUSDHC_AdmaErrorStateStopDma =
  240. 0x00U, /*!< Stop DMA, previous location set in the ADMA system address is error address */
  241. kUSDHC_AdmaErrorStateFetchDescriptor =
  242. 0x01U, /*!< Fetch descriptor, current location set in the ADMA system address is error address */
  243. kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occured */
  244. kUSDHC_AdmaErrorStateTransferData =
  245. 0x03U, /*!< Transfer data, previous location set in the ADMA system address is error address */
  246. kUSDHC_AdmaErrorStateInvalidLength = 0x04U, /*!< Invalid length in ADMA descriptor */
  247. kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, /*!< Invalid descriptor fetched by ADMA */
  248. kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor |
  249. kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */
  250. };
  251. /*! @brief Force event mask */
  252. enum _usdhc_force_event
  253. {
  254. kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */
  255. kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */
  256. kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */
  257. kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */
  258. kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */
  259. kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */
  260. kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */
  261. kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */
  262. kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */
  263. kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */
  264. kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */
  265. kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */
  266. kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */
  267. kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */
  268. kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */
  269. kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */
  270. #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
  271. kUSDHC_ForceEventTuningError = 0U, /*!< not support */
  272. #else
  273. kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */
  274. #endif
  275. kUSDHC_ForceEventsAll =
  276. (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout |
  277. kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError |
  278. kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued |
  279. kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError |
  280. kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError |
  281. kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt |
  282. kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */
  283. };
  284. /*! @brief Data transfer width */
  285. typedef enum _usdhc_data_bus_width
  286. {
  287. kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */
  288. kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */
  289. kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */
  290. } usdhc_data_bus_width_t;
  291. /*! @brief Endian mode */
  292. typedef enum _usdhc_endian_mode
  293. {
  294. kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */
  295. kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */
  296. kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */
  297. } usdhc_endian_mode_t;
  298. /*! @brief DMA mode */
  299. typedef enum _usdhc_dma_mode
  300. {
  301. kUSDHC_DmaModeSimple = 0U, /*!< external DMA */
  302. kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */
  303. kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */
  304. kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */
  305. } usdhc_dma_mode_t;
  306. /*! @brief SDIO control flag mask */
  307. enum _usdhc_sdio_control_flag
  308. {
  309. kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */
  310. kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */
  311. kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */
  312. kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */
  313. kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */
  314. };
  315. /*! @brief MMC card boot mode */
  316. typedef enum _usdhc_boot_mode
  317. {
  318. kUSDHC_BootModeNormal = 0U, /*!< Normal boot */
  319. kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */
  320. } usdhc_boot_mode_t;
  321. /*! @brief The command type */
  322. typedef enum _usdhc_card_command_type
  323. {
  324. kCARD_CommandTypeNormal = 0U, /*!< Normal command */
  325. kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
  326. kCARD_CommandTypeResume = 2U, /*!< Resume command */
  327. kCARD_CommandTypeAbort = 3U, /*!< Abort command */
  328. kCARD_CommandTypeEmpty = 4U, /*!< Empty command */
  329. } usdhc_card_command_type_t;
  330. /*!
  331. * @brief The command response type.
  332. *
  333. * Define the command response type from card to host controller.
  334. */
  335. typedef enum _usdhc_card_response_type
  336. {
  337. kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
  338. kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */
  339. kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */
  340. kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */
  341. kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */
  342. kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */
  343. kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */
  344. kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */
  345. kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */
  346. kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */
  347. } usdhc_card_response_type_t;
  348. /*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */
  349. #define USDHC_ADMA1_ADDRESS_ALIGN (4096U)
  350. /*! @brief The alignment size for LENGTH field in ADMA1's descriptor */
  351. #define USDHC_ADMA1_LENGTH_ALIGN (4096U)
  352. /*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */
  353. #define USDHC_ADMA2_ADDRESS_ALIGN (4U)
  354. /*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */
  355. #define USDHC_ADMA2_LENGTH_ALIGN (4U)
  356. /* ADMA1 descriptor table
  357. * |------------------------|---------|--------------------------|
  358. * | Address/page field |Reserved | Attribute |
  359. * |------------------------|---------|--------------------------|
  360. * |31 12|11 6|05 |04 |03|02 |01 |00 |
  361. * |------------------------|---------|----|----|--|---|---|-----|
  362. * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|
  363. * |------------------------|---------|----|----|--|---|---|-----|
  364. *
  365. *
  366. * |------|------|-----------------|-------|-------------|
  367. * | Act2 | Act1 | Comment | 31-28 | 27 - 12 |
  368. * |------|------|-----------------|---------------------|
  369. * | 0 | 0 | No op | Don't care |
  370. * |------|------|-----------------|-------|-------------|
  371. * | 0 | 1 | Set data length | 0000 | Data Length |
  372. * |------|------|-----------------|-------|-------------|
  373. * | 1 | 0 | Transfer data | Data address |
  374. * |------|------|-----------------|---------------------|
  375. * | 1 | 1 | Link descriptor | Descriptor address |
  376. * |------|------|-----------------|---------------------|
  377. */
  378. /*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */
  379. #define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U)
  380. /*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */
  381. #define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)
  382. /*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */
  383. #define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U)
  384. /*! @brief The mask for LENGTH field in ADMA1's descriptor */
  385. #define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
  386. /*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */
  387. #define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U)
  388. /*! @brief The mask for the control/status field in ADMA1 descriptor */
  389. enum _usdhc_adma1_descriptor_flag
  390. {
  391. kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
  392. kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */
  393. kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */
  394. kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */
  395. kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */
  396. kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */
  397. kUSDHC_Adma1DescriptorTypeTransfer =
  398. (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */
  399. kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag |
  400. kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */
  401. kUSDHC_Adma1DescriptorTypeSetLength =
  402. (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */
  403. };
  404. /* ADMA2 descriptor table
  405. * |----------------|---------------|-------------|--------------------------|
  406. * | Address field | Length | Reserved | Attribute |
  407. * |----------------|---------------|-------------|--------------------------|
  408. * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |
  409. * |----------------|---------------|-------------|----|----|--|---|---|-----|
  410. * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|
  411. * |----------------|---------------|-------------|----|----|--|---|---|-----|
  412. *
  413. *
  414. * | Act2 | Act1 | Comment | Operation |
  415. * |------|------|-----------------|-------------------------------------------------------------------|
  416. * | 0 | 0 | No op | Don't care |
  417. * |------|------|-----------------|-------------------------------------------------------------------|
  418. * | 0 | 1 | Reserved | Read this line and go to next one |
  419. * |------|------|-----------------|-------------------------------------------------------------------|
  420. * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |
  421. * |------|------|-----------------|-------------------------------------------------------------------|
  422. * | 1 | 1 | Link descriptor | Link to another descriptor |
  423. * |------|------|-----------------|-------------------------------------------------------------------|
  424. */
  425. /*! @brief The bit shift for LENGTH field in ADMA2's descriptor */
  426. #define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U)
  427. /*! @brief The bit mask for LENGTH field in ADMA2's descriptor */
  428. #define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
  429. /*! @brief The maximum value of LENGTH field in ADMA2's descriptor */
  430. #define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U)
  431. /*! @brief ADMA1 descriptor control and status mask */
  432. enum _usdhc_adma2_descriptor_flag
  433. {
  434. kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
  435. kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */
  436. kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */
  437. kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */
  438. kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */
  439. kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */
  440. kUSDHC_Adma2DescriptorTypeReserved =
  441. (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */
  442. kUSDHC_Adma2DescriptorTypeTransfer =
  443. (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */
  444. kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag |
  445. kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */
  446. };
  447. /*! @brief ADMA descriptor configuration flag */
  448. enum _usdhc_adma_flag
  449. {
  450. kUSDHC_AdmaDescriptorSingleFlag =
  451. 0U, /*!< try to finish the transfer in a single ADMA descriptor, if transfer size is bigger than one
  452. ADMA descriptor's ability, new another descriptor for data transfer */
  453. kUSDHC_AdmaDescriptorMultipleFlag = 1U, /*!< create multiple ADMA descriptor within the ADMA table, this is used for
  454. mmc boot mode specifically, which need
  455. to modify the ADMA descriptor on the fly, so the flag should be used
  456. combine with stop at block gap feature */
  457. };
  458. /*! @brief dma transfer burst len config. */
  459. typedef enum _usdhc_burst_len
  460. {
  461. kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */
  462. kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */
  463. kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */
  464. } usdhc_burst_len_t;
  465. /*! @brief transfer data type definition. */
  466. enum _usdhc_transfer_data_type
  467. {
  468. kUSDHC_TransferDataNormal = 0U, /*!< transfer normal read/write data */
  469. kUSDHC_TransferDataTuning = 1U, /*!< transfer tuning data */
  470. kUSDHC_TransferDataBoot = 2U, /*!< transfer boot data */
  471. kUSDHC_TransferDataBootcontinous = 3U, /*!< transfer boot data continous */
  472. };
  473. /*! @brief Defines the adma1 descriptor structure. */
  474. typedef uint32_t usdhc_adma1_descriptor_t;
  475. /*! @brief Defines the ADMA2 descriptor structure. */
  476. typedef struct _usdhc_adma2_descriptor
  477. {
  478. uint32_t attribute; /*!< The control and status field */
  479. const uint32_t *address; /*!< The address field */
  480. } usdhc_adma2_descriptor_t;
  481. /*!
  482. * @brief USDHC capability information.
  483. *
  484. * Defines a structure to save the capability information of USDHC.
  485. */
  486. typedef struct _usdhc_capability
  487. {
  488. uint32_t sdVersion; /*!< support SD card/sdio version */
  489. uint32_t mmcVersion; /*!< support emmc card version */
  490. uint32_t maxBlockLength; /*!< Maximum block length united as byte */
  491. uint32_t maxBlockCount; /*!< Maximum block count can be set one time */
  492. uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */
  493. } usdhc_capability_t;
  494. /*! @brief Data structure to configure the MMC boot feature */
  495. typedef struct _usdhc_boot_config
  496. {
  497. uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */
  498. usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */
  499. uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */
  500. size_t blockSize; /*!< Block size */
  501. bool enableBootAck; /*!< Enable or disable boot ACK */
  502. bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */
  503. } usdhc_boot_config_t;
  504. /*! @brief Data structure to initialize the USDHC */
  505. typedef struct _usdhc_config
  506. {
  507. uint32_t dataTimeout; /*!< Data timeout value */
  508. usdhc_endian_mode_t endianMode; /*!< Endian mode */
  509. uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */
  510. uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */
  511. uint8_t readBurstLen; /*!< Read burst len */
  512. uint8_t writeBurstLen; /*!< Write burst len */
  513. } usdhc_config_t;
  514. /*!
  515. * @brief Card data descriptor
  516. *
  517. * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card
  518. * driver
  519. * want to ignore the error event to read/write all the data not to stop read/write immediately when error event
  520. * happen for example bus testing procedure for MMC card.
  521. */
  522. typedef struct _usdhc_data
  523. {
  524. bool enableAutoCommand12; /*!< Enable auto CMD12 */
  525. bool enableAutoCommand23; /*!< Enable auto CMD23 */
  526. bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */
  527. uint8_t dataType; /*!< this is used to distinguish the normal/tuning/boot data */
  528. size_t blockSize; /*!< Block size */
  529. uint32_t blockCount; /*!< Block count */
  530. uint32_t *rxData; /*!< Buffer to save data read */
  531. const uint32_t *txData; /*!< Data buffer to write */
  532. } usdhc_data_t;
  533. /*!
  534. * @brief Card command descriptor
  535. *
  536. * Define card command-related attribute.
  537. */
  538. typedef struct _usdhc_command
  539. {
  540. uint32_t index; /*!< Command index */
  541. uint32_t argument; /*!< Command argument */
  542. usdhc_card_command_type_t type; /*!< Command type */
  543. usdhc_card_response_type_t responseType; /*!< Command response type */
  544. uint32_t response[4U]; /*!< Response for this command */
  545. uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check
  546. the command reponse*/
  547. uint32_t flags; /*!< Cmd flags */
  548. } usdhc_command_t;
  549. /*! @brief ADMA configuration */
  550. typedef struct _usdhc_adma_config
  551. {
  552. usdhc_dma_mode_t dmaMode; /*!< DMA mode */
  553. usdhc_burst_len_t burstLen; /*!< burst len config */
  554. uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */
  555. uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */
  556. } usdhc_adma_config_t;
  557. /*! @brief Transfer state */
  558. typedef struct _usdhc_transfer
  559. {
  560. usdhc_data_t *data; /*!< Data to transfer */
  561. usdhc_command_t *command; /*!< Command to send */
  562. } usdhc_transfer_t;
  563. /*! @brief USDHC handle typedef */
  564. typedef struct _usdhc_handle usdhc_handle_t;
  565. /*! @brief USDHC callback functions. */
  566. typedef struct _usdhc_transfer_callback
  567. {
  568. void (*CardInserted)(USDHC_Type *base,
  569. void *userData); /*!< Card inserted occurs when DAT3/CD pin is for card detect */
  570. void (*CardRemoved)(USDHC_Type *base, void *userData); /*!< Card removed occurs */
  571. void (*SdioInterrupt)(USDHC_Type *base, void *userData); /*!< SDIO card interrupt occurs */
  572. void (*BlockGap)(USDHC_Type *base, void *userData); /*!< stopped at block gap event */
  573. void (*TransferComplete)(USDHC_Type *base,
  574. usdhc_handle_t *handle,
  575. status_t status,
  576. void *userData); /*!< Transfer complete callback */
  577. void (*ReTuning)(USDHC_Type *base, void *userData); /*!< handle the re-tuning */
  578. } usdhc_transfer_callback_t;
  579. /*!
  580. * @brief USDHC handle
  581. *
  582. * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when
  583. * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in
  584. * usdhc_interrupt_flag_t.
  585. *
  586. * @note All the fields except interruptFlags and transferredWords must be allocated by the user.
  587. */
  588. struct _usdhc_handle
  589. {
  590. /* Transfer parameter */
  591. usdhc_data_t *volatile data; /*!< Data to transfer */
  592. usdhc_command_t *volatile command; /*!< Command to send */
  593. /* Transfer status */
  594. volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */
  595. volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */
  596. /* Callback functions */
  597. usdhc_transfer_callback_t callback; /*!< Callback function */
  598. void *userData; /*!< Parameter for transfer complete callback */
  599. };
  600. /*! @brief USDHC transfer function. */
  601. typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content);
  602. /*! @brief USDHC host descriptor */
  603. typedef struct _usdhc_host
  604. {
  605. USDHC_Type *base; /*!< USDHC peripheral base address */
  606. uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */
  607. usdhc_config_t config; /*!< USDHC configuration */
  608. usdhc_capability_t capability; /*!< USDHC capability information */
  609. usdhc_transfer_function_t transfer; /*!< USDHC transfer function */
  610. } usdhc_host_t;
  611. /*************************************************************************************************
  612. * API
  613. ************************************************************************************************/
  614. #if defined(__cplusplus)
  615. extern "C" {
  616. #endif
  617. /*!
  618. * @name Initialization and deinitialization
  619. * @{
  620. */
  621. /*!
  622. * @brief USDHC module initialization function.
  623. *
  624. * Configures the USDHC according to the user configuration.
  625. *
  626. * Example:
  627. @code
  628. usdhc_config_t config;
  629. config.cardDetectDat3 = false;
  630. config.endianMode = kUSDHC_EndianModeLittle;
  631. config.dmaMode = kUSDHC_DmaModeAdma2;
  632. config.readWatermarkLevel = 128U;
  633. config.writeWatermarkLevel = 128U;
  634. USDHC_Init(USDHC, &config);
  635. @endcode
  636. *
  637. * @param base USDHC peripheral base address.
  638. * @param config USDHC configuration information.
  639. * @retval kStatus_Success Operate successfully.
  640. */
  641. void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config);
  642. /*!
  643. * @brief Deinitializes the USDHC.
  644. *
  645. * @param base USDHC peripheral base address.
  646. */
  647. void USDHC_Deinit(USDHC_Type *base);
  648. /*!
  649. * @brief Resets the USDHC.
  650. *
  651. * @param base USDHC peripheral base address.
  652. * @param mask The reset type mask(_usdhc_reset).
  653. * @param timeout Timeout for reset.
  654. * @retval true Reset successfully.
  655. * @retval false Reset failed.
  656. */
  657. bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout);
  658. /* @} */
  659. /*!
  660. * @name DMA Control
  661. * @{
  662. */
  663. /*!
  664. * @brief Sets the DMA descriptor table configuration.
  665. * A high level DMA descriptor configuration function.
  666. * @param base USDHC peripheral base address.
  667. * @param adma configuration
  668. * @param data Data descriptor
  669. * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please
  670. * reference _usdhc_adma_flag
  671. * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
  672. * @retval kStatus_Success Operate successfully.
  673. */
  674. status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,
  675. usdhc_adma_config_t *dmaConfig,
  676. usdhc_data_t *dataConfig,
  677. uint32_t flags);
  678. /*!
  679. * @brief Internal DMA configuration.
  680. * This function is used to config the USDHC DMA related registers.
  681. * @param base USDHC peripheral base address.
  682. * @param adma configuration
  683. * @param dataAddr tranfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL.
  684. * @param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to
  685. * false.
  686. * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
  687. * @retval kStatus_Success Operate successfully.
  688. */
  689. status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
  690. usdhc_adma_config_t *dmaConfig,
  691. const uint32_t *dataAddr,
  692. bool enAutoCmd23);
  693. /*!
  694. * @brief Sets the ADMA2 descriptor table configuration.
  695. *
  696. * @param admaTable Adma table address.
  697. * @param admaTableWords Adma table length.
  698. * @param dataBufferAddr Data buffer address.
  699. * @param dataBytes Data Data length.
  700. * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please
  701. * reference _usdhc_adma_flag.
  702. * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
  703. * @retval kStatus_Success Operate successfully.
  704. */
  705. status_t USDHC_SetADMA2Descriptor(
  706. uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags);
  707. /*!
  708. * @brief Sets the ADMA1 descriptor table configuration.
  709. *
  710. * @param admaTable Adma table address.
  711. * @param admaTableWords Adma table length.
  712. * @param dataBufferAddr Data buffer address.
  713. * @param dataBytes Data length.
  714. * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please
  715. * reference _usdhc_adma_flag.
  716. * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
  717. * @retval kStatus_Success Operate successfully.
  718. */
  719. status_t USDHC_SetADMA1Descriptor(
  720. uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags);
  721. /*!
  722. * @brief enable internal DMA.
  723. *
  724. * @param base USDHC peripheral base address.
  725. * @param enable enable or disable flag
  726. */
  727. static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable)
  728. {
  729. if (enable)
  730. {
  731. base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK;
  732. }
  733. else
  734. {
  735. base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK;
  736. base->PROT_CTRL &= ~USDHC_PROT_CTRL_DMASEL_MASK;
  737. }
  738. }
  739. /* @} */
  740. /*!
  741. * @name Interrupts
  742. * @{
  743. */
  744. /*!
  745. * @brief Enables the interrupt status.
  746. *
  747. * @param base USDHC peripheral base address.
  748. * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag).
  749. */
  750. static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask)
  751. {
  752. base->INT_STATUS_EN |= mask;
  753. }
  754. /*!
  755. * @brief Disables the interrupt status.
  756. *
  757. * @param base USDHC peripheral base address.
  758. * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag).
  759. */
  760. static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask)
  761. {
  762. base->INT_STATUS_EN &= ~mask;
  763. }
  764. /*!
  765. * @brief Enables the interrupt signal corresponding to the interrupt status flag.
  766. *
  767. * @param base USDHC peripheral base address.
  768. * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag).
  769. */
  770. static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask)
  771. {
  772. base->INT_SIGNAL_EN |= mask;
  773. }
  774. /*!
  775. * @brief Disables the interrupt signal corresponding to the interrupt status flag.
  776. *
  777. * @param base USDHC peripheral base address.
  778. * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag).
  779. */
  780. static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask)
  781. {
  782. base->INT_SIGNAL_EN &= ~mask;
  783. }
  784. /* @} */
  785. /*!
  786. * @name Status
  787. * @{
  788. */
  789. /*!
  790. * @brief Gets the current interrupt status.
  791. *
  792. * @param base USDHC peripheral base address.
  793. * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag).
  794. */
  795. static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base)
  796. {
  797. return base->INT_STATUS;
  798. }
  799. /*!
  800. * @brief Clears a specified interrupt status.
  801. * write 1 clears
  802. * @param base USDHC peripheral base address.
  803. * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag).
  804. */
  805. static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask)
  806. {
  807. base->INT_STATUS = mask;
  808. }
  809. /*!
  810. * @brief Gets the status of auto command 12 error.
  811. *
  812. * @param base USDHC peripheral base address.
  813. * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag).
  814. */
  815. static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base)
  816. {
  817. return base->AUTOCMD12_ERR_STATUS;
  818. }
  819. /*!
  820. * @brief Gets the status of the ADMA error.
  821. *
  822. * @param base USDHC peripheral base address.
  823. * @return ADMA error status flags mask(_usdhc_adma_error_status_flag).
  824. */
  825. static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base)
  826. {
  827. return base->ADMA_ERR_STATUS & 0xFU;
  828. }
  829. /*!
  830. * @brief Gets a present status.
  831. *
  832. * This function gets the present USDHC's status except for an interrupt status and an error status.
  833. *
  834. * @param base USDHC peripheral base address.
  835. * @return Present USDHC's status flags mask(_usdhc_present_status_flag).
  836. */
  837. static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base)
  838. {
  839. return base->PRES_STATE;
  840. }
  841. /* @} */
  842. /*!
  843. * @name Bus Operations
  844. * @{
  845. */
  846. /*!
  847. * @brief Gets the capability information.
  848. *
  849. * @param base USDHC peripheral base address.
  850. * @param capability Structure to save capability information.
  851. */
  852. void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability);
  853. /*!
  854. * @brief force the card clock on.
  855. *
  856. * @param base USDHC peripheral base address.
  857. * @param enable/disable flag.
  858. */
  859. static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable)
  860. {
  861. if (enable)
  862. {
  863. base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK;
  864. }
  865. else
  866. {
  867. base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK;
  868. }
  869. }
  870. /*!
  871. * @brief Sets the SD bus clock frequency.
  872. *
  873. * @param base USDHC peripheral base address.
  874. * @param srcClock_Hz USDHC source clock frequency united in Hz.
  875. * @param busClock_Hz SD bus clock frequency united in Hz.
  876. *
  877. * @return The nearest frequency of busClock_Hz configured to SD bus.
  878. */
  879. uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz);
  880. /*!
  881. * @brief Sends 80 clocks to the card to set it to the active state.
  882. *
  883. * This function must be called each time the card is inserted to ensure that the card can receive the command
  884. * correctly.
  885. *
  886. * @param base USDHC peripheral base address.
  887. * @param timeout Timeout to initialize card.
  888. * @retval true Set card active successfully.
  889. * @retval false Set card active failed.
  890. */
  891. bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout);
  892. /*!
  893. * @brief trigger a hardware reset.
  894. *
  895. * @param base USDHC peripheral base address.
  896. * @param 1 or 0 level
  897. */
  898. static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high)
  899. {
  900. if (high)
  901. {
  902. base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK;
  903. }
  904. else
  905. {
  906. base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK;
  907. }
  908. }
  909. /*!
  910. * @brief Sets the data transfer width.
  911. *
  912. * @param base USDHC peripheral base address.
  913. * @param width Data transfer width.
  914. */
  915. static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width)
  916. {
  917. base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width));
  918. }
  919. /*!
  920. * @brief Fills the data port.
  921. *
  922. * This function is used to implement the data transfer by Data Port instead of DMA.
  923. *
  924. * @param base USDHC peripheral base address.
  925. * @param data The data about to be sent.
  926. */
  927. static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data)
  928. {
  929. base->DATA_BUFF_ACC_PORT = data;
  930. }
  931. /*!
  932. * @brief Retrieves the data from the data port.
  933. *
  934. * This function is used to implement the data transfer by Data Port instead of DMA.
  935. *
  936. * @param base USDHC peripheral base address.
  937. * @return The data has been read.
  938. */
  939. static inline uint32_t USDHC_ReadData(USDHC_Type *base)
  940. {
  941. return base->DATA_BUFF_ACC_PORT;
  942. }
  943. /*!
  944. * @brief send command function
  945. *
  946. * @param base USDHC peripheral base address.
  947. * @param command configuration
  948. */
  949. void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command);
  950. /*!
  951. * @brief Enables or disables a wakeup event in low-power mode.
  952. *
  953. * @param base USDHC peripheral base address.
  954. * @param mask Wakeup events mask(_usdhc_wakeup_event).
  955. * @param enable True to enable, false to disable.
  956. */
  957. static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable)
  958. {
  959. if (enable)
  960. {
  961. base->PROT_CTRL |= mask;
  962. }
  963. else
  964. {
  965. base->PROT_CTRL &= ~mask;
  966. }
  967. }
  968. /*!
  969. * @brief detect card insert status.
  970. *
  971. * @param base USDHC peripheral base address.
  972. * @param enable/disable flag
  973. */
  974. static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable)
  975. {
  976. if (enable)
  977. {
  978. base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK;
  979. }
  980. else
  981. {
  982. base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK;
  983. }
  984. }
  985. /*!
  986. * @brief detect card insert status.
  987. *
  988. * @param base USDHC peripheral base address.
  989. */
  990. static inline bool USDHC_DetectCardInsert(USDHC_Type *base)
  991. {
  992. return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false;
  993. }
  994. /*!
  995. * @brief Enables or disables the SDIO card control.
  996. *
  997. * @param base USDHC peripheral base address.
  998. * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag).
  999. * @param enable True to enable, false to disable.
  1000. */
  1001. static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable)
  1002. {
  1003. if (enable)
  1004. {
  1005. base->PROT_CTRL |= mask;
  1006. }
  1007. else
  1008. {
  1009. base->PROT_CTRL &= ~mask;
  1010. }
  1011. }
  1012. /*!
  1013. * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card.
  1014. *
  1015. * @param base USDHC peripheral base address.
  1016. */
  1017. static inline void USDHC_SetContinueRequest(USDHC_Type *base)
  1018. {
  1019. base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK;
  1020. }
  1021. /*!
  1022. * @brief Request stop at block gap function.
  1023. *
  1024. * @param base USDHC peripheral base address.
  1025. * @param enable true to stop at block gap, false to normal transfer
  1026. */
  1027. static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable)
  1028. {
  1029. if (enable)
  1030. {
  1031. base->PROT_CTRL |= USDHC_PROT_CTRL_SABGREQ_MASK;
  1032. }
  1033. else
  1034. {
  1035. base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK;
  1036. }
  1037. }
  1038. /*!
  1039. * @brief Configures the MMC boot feature.
  1040. *
  1041. * Example:
  1042. @code
  1043. usdhc_boot_config_t config;
  1044. config.ackTimeoutCount = 4;
  1045. config.bootMode = kUSDHC_BootModeNormal;
  1046. config.blockCount = 5;
  1047. config.enableBootAck = true;
  1048. config.enableBoot = true;
  1049. config.enableAutoStopAtBlockGap = true;
  1050. USDHC_SetMmcBootConfig(USDHC, &config);
  1051. @endcode
  1052. *
  1053. * @param base USDHC peripheral base address.
  1054. * @param config The MMC boot configuration information.
  1055. */
  1056. void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config);
  1057. /*!
  1058. * @brief Enables or disables the mmc boot mode.
  1059. *
  1060. * @param base USDHC peripheral base address.
  1061. * @param enable True to enable, false to disable.
  1062. */
  1063. static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable)
  1064. {
  1065. if (enable)
  1066. {
  1067. base->MMC_BOOT |= USDHC_MMC_BOOT_BOOT_EN_MASK;
  1068. }
  1069. else
  1070. {
  1071. base->MMC_BOOT &= ~USDHC_MMC_BOOT_BOOT_EN_MASK;
  1072. }
  1073. }
  1074. /*!
  1075. * @brief Forces generating events according to the given mask.
  1076. *
  1077. * @param base USDHC peripheral base address.
  1078. * @param mask The force events mask(_usdhc_force_event).
  1079. */
  1080. static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask)
  1081. {
  1082. base->FORCE_EVENT = mask;
  1083. }
  1084. /*!
  1085. * @brief select the usdhc output voltage
  1086. *
  1087. * @param base USDHC peripheral base address.
  1088. * @param true 1.8V, false 3.0V
  1089. */
  1090. static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v)
  1091. {
  1092. if (en18v)
  1093. {
  1094. base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK;
  1095. }
  1096. else
  1097. {
  1098. base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK;
  1099. }
  1100. }
  1101. #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE)
  1102. /*!
  1103. * @brief check the SDR50 mode request tuning bit
  1104. * When this bit set, user should call USDHC_StandardTuning function
  1105. * @param base USDHC peripheral base address.
  1106. */
  1107. static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base)
  1108. {
  1109. return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false;
  1110. }
  1111. /*!
  1112. * @brief check the request re-tuning bit
  1113. * When this bit is set, user should do manual tuning or standard tuning function
  1114. * @param base USDHC peripheral base address.
  1115. */
  1116. static inline bool USDHC_RequestReTuning(USDHC_Type *base)
  1117. {
  1118. return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false;
  1119. }
  1120. /*!
  1121. * @brief the SDR104 mode auto tuning enable and disable
  1122. * This function should call after tuning function execute pass, auto tuning will handle
  1123. * by hardware
  1124. * @param base USDHC peripheral base address.
  1125. * @param enable/disable flag
  1126. */
  1127. static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable)
  1128. {
  1129. if (enable)
  1130. {
  1131. base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK;
  1132. }
  1133. else
  1134. {
  1135. base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK;
  1136. }
  1137. }
  1138. /*!
  1139. * @brief the config the re-tuning timer for mode 1 and mode 3
  1140. * This timer is used for standard tuning auto re-tuning,
  1141. * @param base USDHC peripheral base address.
  1142. * @param timer counter value
  1143. */
  1144. static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter)
  1145. {
  1146. base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK;
  1147. base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter);
  1148. }
  1149. /*!
  1150. * @brief the auto tuning enbale for CMD/DATA line
  1151. *
  1152. * @param base USDHC peripheral base address.
  1153. */
  1154. void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base);
  1155. /*!
  1156. * @brief manual tuning trigger or abort
  1157. * User should handle the tuning cmd and find the boundary of the delay
  1158. * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS
  1159. * This function should called before USDHC_AdjustDelayforSDR104 function
  1160. * @param base USDHC peripheral base address.
  1161. * @param tuning enable flag
  1162. */
  1163. void USDHC_EnableManualTuning(USDHC_Type *base, bool enable);
  1164. /*!
  1165. * @brief the SDR104 mode delay setting adjust
  1166. * This function should called after USDHC_ManualTuningForSDR104
  1167. * @param base USDHC peripheral base address.
  1168. * @param delay setting configuration
  1169. * @retval kStatus_Fail config the delay setting fail
  1170. * @retval kStatus_Success config the delay setting success
  1171. */
  1172. status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay);
  1173. /*!
  1174. * @brief the enable standard tuning function
  1175. * The standard tuning window and tuning counter use the default config
  1176. * tuning cmd is send by the software, user need to check the tuning result
  1177. * can be used for SDR50,SDR104,HS200 mode tuning
  1178. * @param base USDHC peripheral base address.
  1179. * @param tuning start tap
  1180. * @param tuning step
  1181. * @param enable/disable flag
  1182. */
  1183. void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable);
  1184. /*!
  1185. * @brief Get execute std tuning status
  1186. *
  1187. * @param base USDHC peripheral base address.
  1188. */
  1189. static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base)
  1190. {
  1191. return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK);
  1192. }
  1193. /*!
  1194. * @brief check std tuning result
  1195. *
  1196. * @param base USDHC peripheral base address.
  1197. */
  1198. static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base)
  1199. {
  1200. return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK);
  1201. }
  1202. /*!
  1203. * @brief check tuning error
  1204. *
  1205. * @param base USDHC peripheral base address.
  1206. */
  1207. static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base)
  1208. {
  1209. return (base->CLK_TUNE_CTRL_STATUS &
  1210. (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK));
  1211. }
  1212. #endif
  1213. /*!
  1214. * @brief the enable/disable DDR mode
  1215. *
  1216. * @param base USDHC peripheral base address.
  1217. * @param enable/disable flag
  1218. * @param nibble position
  1219. */
  1220. void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos);
  1221. /*!
  1222. * @brief the enable/disable HS400 mode
  1223. *
  1224. * @param base USDHC peripheral base address.
  1225. * @param enable/disable flag
  1226. */
  1227. #if FSL_FEATURE_USDHC_HAS_HS400_MODE
  1228. static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable)
  1229. {
  1230. if (enable)
  1231. {
  1232. base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK;
  1233. }
  1234. else
  1235. {
  1236. base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK;
  1237. }
  1238. }
  1239. /*!
  1240. * @brief reset the strobe DLL
  1241. *
  1242. * @param base USDHC peripheral base address.
  1243. */
  1244. static inline void USDHC_ResetStrobeDLL(USDHC_Type *base)
  1245. {
  1246. base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK;
  1247. }
  1248. /*!
  1249. * @brief enable/disable the strobe DLL
  1250. *
  1251. * @param base USDHC peripheral base address.
  1252. * @param enable/disable flag
  1253. */
  1254. static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable)
  1255. {
  1256. if (enable)
  1257. {
  1258. base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK;
  1259. }
  1260. else
  1261. {
  1262. base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK;
  1263. }
  1264. }
  1265. /*!
  1266. * @brief config the strobe DLL delay target and update interval
  1267. *
  1268. * @param base USDHC peripheral base address.
  1269. * @param delay target
  1270. * @param update interval
  1271. */
  1272. static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval)
  1273. {
  1274. base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK |
  1275. USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK);
  1276. base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) |
  1277. USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget);
  1278. }
  1279. /*!
  1280. * @brief get the strobe DLL status
  1281. *
  1282. * @param base USDHC peripheral base address.
  1283. */
  1284. static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base)
  1285. {
  1286. return base->STROBE_DLL_STATUS;
  1287. }
  1288. #endif
  1289. /* @} */
  1290. /*!
  1291. * @name Transactional
  1292. * @{
  1293. */
  1294. /*!
  1295. * @brief Transfers the command/data using a blocking method.
  1296. *
  1297. * This function waits until the command response/data is received or the USDHC encounters an error by polling the
  1298. * status
  1299. * flag.
  1300. * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
  1301. * the re-entry mechanism.
  1302. *
  1303. * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API.
  1304. *
  1305. * @param base USDHC peripheral base address.
  1306. * @param adma configuration
  1307. * @param transfer Transfer content.
  1308. * @retval kStatus_InvalidArgument Argument is invalid.
  1309. * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
  1310. * @retval kStatus_USDHC_SendCommandFailed Send command failed.
  1311. * @retval kStatus_USDHC_TransferDataFailed Transfer data failed.
  1312. * @retval kStatus_Success Operate successfully.
  1313. */
  1314. status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer);
  1315. /*!
  1316. * @brief Creates the USDHC handle.
  1317. *
  1318. * @param base USDHC peripheral base address.
  1319. * @param handle USDHC handle pointer.
  1320. * @param callback Structure pointer to contain all callback functions.
  1321. * @param userData Callback function parameter.
  1322. */
  1323. void USDHC_TransferCreateHandle(USDHC_Type *base,
  1324. usdhc_handle_t *handle,
  1325. const usdhc_transfer_callback_t *callback,
  1326. void *userData);
  1327. /*!
  1328. * @brief Transfers the command/data using an interrupt and an asynchronous method.
  1329. *
  1330. * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an
  1331. * error.
  1332. * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
  1333. * the re-entry mechanism.
  1334. *
  1335. * @note Call the API 'USDHC_TransferCreateHandle' when calling this API.
  1336. *
  1337. * @param base USDHC peripheral base address.
  1338. * @param handle USDHC handle.
  1339. * @param adma configuration.
  1340. * @param transfer Transfer content.
  1341. * @retval kStatus_InvalidArgument Argument is invalid.
  1342. * @retval kStatus_USDHC_BusyTransferring Busy transferring.
  1343. * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
  1344. * @retval kStatus_Success Operate successfully.
  1345. */
  1346. status_t USDHC_TransferNonBlocking(USDHC_Type *base,
  1347. usdhc_handle_t *handle,
  1348. usdhc_adma_config_t *dmaConfig,
  1349. usdhc_transfer_t *transfer);
  1350. /*!
  1351. * @brief IRQ handler for the USDHC.
  1352. *
  1353. * This function deals with the IRQs on the given host controller.
  1354. *
  1355. * @param base USDHC peripheral base address.
  1356. * @param handle USDHC handle.
  1357. */
  1358. void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle);
  1359. /* @} */
  1360. #if defined(__cplusplus)
  1361. }
  1362. #endif
  1363. /*! @} */
  1364. #endif /* _FSL_USDHC_H_*/