drv_pwm.c 7.3 KB

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  1. /*
  2. * Copyright (c) 2022-2023 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-05-09 HPMicro First version
  9. * 2023-04-12 HPMicro Adapt hpm_sdk v1.0.0
  10. * 2023-05-13 HPMicro Fix compiling error on HPM6360/HPM6200
  11. */
  12. #include <rtthread.h>
  13. #ifdef BSP_USING_PWM
  14. #include <rthw.h>
  15. #include <rtdevice.h>
  16. #include "board.h"
  17. #include "drv_gpio.h"
  18. #include "hpm_pwm_drv.h"
  19. #include "hpm_clock_drv.h"
  20. #ifdef HPM_PWM3
  21. #define PWM_INSTANCE_NUM 4
  22. #elif defined(HPM_PWM2)
  23. #define PWM_INSTANCE_NUM 3
  24. #elif defined(HPM_PWM1)
  25. #define PWM_INSTANCE_NUM 2
  26. #else
  27. #define PWM_INSTANCE_NUM 1
  28. #endif
  29. static PWM_Type * pwm_base_tbl[PWM_INSTANCE_NUM] = {
  30. HPM_PWM0,
  31. #ifdef HPM_PWM1
  32. HPM_PWM1,
  33. #endif
  34. #ifdef HPM_PWM2
  35. HPM_PWM2,
  36. #endif
  37. #ifdef HPM_PWM3
  38. HPM_PWM3
  39. #endif
  40. };
  41. rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse)
  42. {
  43. uint32_t duty;
  44. pwm_cmp_config_t cmp_config[2] = {0};
  45. pwm_config_t pwm_config = {0};
  46. uint32_t reload = 0;
  47. uint32_t freq;
  48. PWM_Type * pwm_name_index;
  49. pwm_name_index = pwm_base_tbl[pwm_index];
  50. init_pwm_pins(pwm_name_index);
  51. freq = board_init_pwm_clock(pwm_name_index);
  52. if(period != 0) {
  53. reload = (uint64_t)freq * period / 1000000000;
  54. } else {
  55. reload = 0;
  56. }
  57. pwm_stop_counter(pwm_name_index);
  58. pwm_get_default_pwm_config(pwm_name_index, &pwm_config);
  59. /*
  60. * reload and start counter
  61. */
  62. pwm_set_reload(pwm_name_index, 0, reload);
  63. pwm_set_start_count(pwm_name_index, 0, 0);
  64. /*
  65. * config cmp1 and cmp2
  66. */
  67. duty = (uint64_t)freq * pulse / 1000000000;
  68. cmp_config[0].mode = pwm_cmp_mode_output_compare;
  69. cmp_config[0].cmp = (reload - duty) >> 1;
  70. cmp_config[0].update_trigger = pwm_shadow_register_update_on_shlk;
  71. cmp_config[1].mode = pwm_cmp_mode_output_compare;
  72. cmp_config[1].cmp = (reload + duty) >> 1;
  73. cmp_config[1].update_trigger = pwm_shadow_register_update_on_shlk;
  74. pwm_config.enable_output = true;
  75. pwm_config.dead_zone_in_half_cycle = 0;
  76. pwm_config.invert_output = false;
  77. /*
  78. * config pwm
  79. */
  80. if (status_success != pwm_setup_waveform(pwm_name_index, channel, &pwm_config, channel * 2, cmp_config, 2)) {
  81. return -RT_ERROR;
  82. }
  83. pwm_start_counter(pwm_name_index);
  84. pwm_issue_shadow_register_lock_event(pwm_name_index);
  85. return RT_EOK;
  86. }
  87. rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse)
  88. {
  89. uint32_t duty;
  90. pwm_config_t pwm_config = {0};
  91. uint32_t reload = 0;
  92. uint32_t freq;
  93. PWM_Type * pwm_name_index;
  94. pwm_name_index = pwm_base_tbl[pwm_index];
  95. freq = board_init_pwm_clock(pwm_name_index);
  96. if(period != 0) {
  97. reload = (uint64_t)freq * period / 1000000000;
  98. } else {
  99. reload = 0;
  100. }
  101. pwm_get_default_pwm_config(pwm_name_index, &pwm_config);
  102. pwm_set_reload(pwm_name_index, 0, reload);
  103. duty = (uint64_t)freq * pulse / 1000000000;
  104. pwm_update_raw_cmp_central_aligned(pwm_name_index, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1);
  105. pwm_issue_shadow_register_lock_event(pwm_name_index);
  106. return RT_EOK;
  107. }
  108. rt_err_t hpm_disable_pwm(uint8_t pwm_index, uint8_t channel)
  109. {
  110. pwm_disable_output(pwm_base_tbl[pwm_index], channel);
  111. return RT_EOK;
  112. }
  113. rt_err_t hpm_pwm_control(struct rt_device_pwm * device, int cmd, void *arg)
  114. {
  115. uint8_t channel;
  116. uint32_t period;
  117. uint32_t pulse;
  118. rt_err_t sta = RT_EOK;
  119. unsigned char pwm_name;
  120. struct rt_pwm_configuration * configuration;
  121. configuration = (struct rt_pwm_configuration * )arg;
  122. channel = configuration->channel;
  123. period = configuration->period;
  124. pulse = configuration->pulse;
  125. if (strcmp("pwm0", device->parent.parent.name) == 0) {
  126. pwm_name = 0;
  127. } else if (strcmp("pwm1", device->parent.parent.name) == 0) {
  128. pwm_name = 1;
  129. } else if (strcmp("pwm2", device->parent.parent.name) == 0) {
  130. pwm_name = 2;
  131. } else if (strcmp("pwm3", device->parent.parent.name) == 0) {
  132. pwm_name = 3;
  133. } else {
  134. return -RT_ERROR;
  135. }
  136. switch(cmd) {
  137. case PWM_CMD_ENABLE: {
  138. sta = hpm_generate_central_aligned_waveform(pwm_name, channel, period, pulse);
  139. break;
  140. }
  141. case PWM_CMD_DISABLE: {
  142. hpm_disable_pwm(pwm_name, channel);
  143. break;
  144. }
  145. case PWM_CMD_SET: {
  146. sta = hpm_set_central_aligned_waveform(pwm_name, channel, period, pulse);
  147. break;
  148. }
  149. case PWM_CMD_GET: {
  150. sta = RT_EOK;
  151. break;
  152. }
  153. default: {
  154. sta = -RT_ERROR;
  155. break;
  156. }
  157. }
  158. return sta;
  159. }
  160. rt_err_t hpm_pwm_dev_control(rt_device_t device, int cmd, void *arg)
  161. {
  162. uint8_t channel;
  163. uint32_t period;
  164. uint32_t pulse;
  165. rt_err_t sta = RT_EOK;
  166. uint8_t pwm_name;
  167. struct rt_pwm_configuration * configuration;
  168. configuration = (struct rt_pwm_configuration * )arg;
  169. channel = configuration->channel;
  170. period = configuration->period;
  171. pulse = configuration->pulse;
  172. if (strcmp("pwm0", device->parent.name) == 0) {
  173. pwm_name = 0;
  174. } else if (strcmp("pwm1", device->parent.name) == 0) {
  175. pwm_name = 1;
  176. } else if (strcmp("pwm2", device->parent.name) == 0) {
  177. pwm_name = 2;
  178. } else if (strcmp("pwm3", device->parent.name) == 0) {
  179. pwm_name = 3;
  180. } else {
  181. return -RT_ERROR;
  182. }
  183. switch(cmd) {
  184. case PWM_CMD_ENABLE: {
  185. sta = hpm_generate_central_aligned_waveform(pwm_name, channel, period, pulse);
  186. break;
  187. }
  188. case PWM_CMD_DISABLE: {
  189. hpm_disable_pwm(pwm_name, channel);
  190. break;
  191. }
  192. case PWM_CMD_SET: {
  193. sta = hpm_set_central_aligned_waveform(pwm_name, channel, period, pulse);
  194. break;
  195. }
  196. case PWM_CMD_GET: {
  197. sta = RT_EOK;
  198. break;
  199. }
  200. default: {
  201. sta = -RT_ERROR;
  202. break;
  203. }
  204. }
  205. return sta;
  206. }
  207. const static struct rt_pwm_ops hpm_pwm_ops = {
  208. .control = &hpm_pwm_control
  209. };
  210. static struct rt_device hpm_pwm_parent = {
  211. .control = hpm_pwm_dev_control
  212. };
  213. #ifdef HPM_PWM0
  214. static struct rt_device_pwm hpm_dev_pwm0 = {
  215. .ops = &hpm_pwm_ops,
  216. };
  217. #endif
  218. #ifdef HPM_PWM1
  219. static struct rt_device_pwm hpm_dev_pwm1 = {
  220. .ops = &hpm_pwm_ops,
  221. };
  222. #endif
  223. #ifdef HPM_PWM2
  224. static struct rt_device_pwm hpm_dev_pwm2 = {
  225. .ops = &hpm_pwm_ops,
  226. };
  227. #endif
  228. #ifdef HPM_PWM3
  229. static struct rt_device_pwm hpm_dev_pwm3 = {
  230. .ops = &hpm_pwm_ops,
  231. };
  232. #endif
  233. int rt_hw_pwm_init(void)
  234. {
  235. int ret = RT_EOK;
  236. #ifdef HPM_PWM0
  237. hpm_dev_pwm0.parent = hpm_pwm_parent;
  238. ret = rt_device_pwm_register(&hpm_dev_pwm0, "pwm0", &hpm_pwm_ops, RT_NULL);
  239. #endif
  240. #ifdef HPM_PWM1
  241. hpm_dev_pwm1.parent = hpm_pwm_parent;
  242. ret = rt_device_pwm_register(&hpm_dev_pwm1, "pwm1", &hpm_pwm_ops, RT_NULL);
  243. #endif
  244. #ifdef HPM_PWM2
  245. hpm_dev_pwm2.parent = hpm_pwm_parent;
  246. ret = rt_device_pwm_register(&hpm_dev_pwm2, "pwm2", &hpm_pwm_ops, RT_NULL);
  247. #endif
  248. #ifdef HPM_PWM3
  249. hpm_dev_pwm3.parent = hpm_pwm_parent;
  250. ret = rt_device_pwm_register(&hpm_dev_pwm3, "pwm3", &hpm_pwm_ops, RT_NULL);
  251. #endif
  252. return ret;
  253. }
  254. INIT_BOARD_EXPORT(rt_hw_pwm_init);
  255. #endif /* BSP_USING_PWM */