drv_spi.c 34 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-5 SummerGift first version
  9. * 2018-12-11 greedyhao Porting for stm32f7xx
  10. * 2019-01-03 zylx modify DMA initialization and spixfer function
  11. * 2020-01-15 whj4674672 Porting for stm32h7xx
  12. * 2020-06-18 thread-liu Porting for stm32mp1xx
  13. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  14. */
  15. #include <rtthread.h>
  16. #include <rtdevice.h>
  17. #include "board.h"
  18. #ifdef BSP_USING_SPI
  19. #if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
  20. #include "drv_spi.h"
  21. #include "drv_config.h"
  22. #include <string.h>
  23. //#define DRV_DEBUG
  24. #define LOG_TAG "drv.spi"
  25. #include <drv_log.h>
  26. enum
  27. {
  28. #ifdef BSP_USING_SPI1
  29. SPI1_INDEX,
  30. #endif
  31. #ifdef BSP_USING_SPI2
  32. SPI2_INDEX,
  33. #endif
  34. #ifdef BSP_USING_SPI3
  35. SPI3_INDEX,
  36. #endif
  37. #ifdef BSP_USING_SPI4
  38. SPI4_INDEX,
  39. #endif
  40. #ifdef BSP_USING_SPI5
  41. SPI5_INDEX,
  42. #endif
  43. #ifdef BSP_USING_SPI6
  44. SPI6_INDEX,
  45. #endif
  46. };
  47. static struct stm32_spi_config spi_config[] =
  48. {
  49. #ifdef BSP_USING_SPI1
  50. SPI1_BUS_CONFIG,
  51. #endif
  52. #ifdef BSP_USING_SPI2
  53. SPI2_BUS_CONFIG,
  54. #endif
  55. #ifdef BSP_USING_SPI3
  56. SPI3_BUS_CONFIG,
  57. #endif
  58. #ifdef BSP_USING_SPI4
  59. SPI4_BUS_CONFIG,
  60. #endif
  61. #ifdef BSP_USING_SPI5
  62. SPI5_BUS_CONFIG,
  63. #endif
  64. #ifdef BSP_USING_SPI6
  65. SPI6_BUS_CONFIG,
  66. #endif
  67. };
  68. static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
  69. static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
  70. {
  71. RT_ASSERT(spi_drv != RT_NULL);
  72. RT_ASSERT(cfg != RT_NULL);
  73. SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
  74. if (cfg->mode & RT_SPI_SLAVE)
  75. {
  76. spi_handle->Init.Mode = SPI_MODE_SLAVE;
  77. }
  78. else
  79. {
  80. spi_handle->Init.Mode = SPI_MODE_MASTER;
  81. }
  82. if (cfg->mode & RT_SPI_3WIRE)
  83. {
  84. spi_handle->Init.Direction = SPI_DIRECTION_1LINE;
  85. }
  86. else
  87. {
  88. spi_handle->Init.Direction = SPI_DIRECTION_2LINES;
  89. }
  90. if (cfg->data_width == 8)
  91. {
  92. spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;
  93. spi_handle->TxXferSize = 8;
  94. spi_handle->RxXferSize = 8;
  95. }
  96. else if (cfg->data_width == 16)
  97. {
  98. spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;
  99. }
  100. else
  101. {
  102. return -RT_EIO;
  103. }
  104. if (cfg->mode & RT_SPI_CPHA)
  105. {
  106. spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;
  107. }
  108. else
  109. {
  110. spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;
  111. }
  112. if (cfg->mode & RT_SPI_CPOL)
  113. {
  114. spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
  115. }
  116. else
  117. {
  118. spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;
  119. }
  120. spi_handle->Init.NSS = SPI_NSS_SOFT;
  121. uint32_t SPI_CLOCK = 0UL;
  122. /* Some series may only have APBPERIPH_BASE, but don't have HAL_RCC_GetPCLK2Freq */
  123. #if defined(APBPERIPH_BASE)
  124. SPI_CLOCK = HAL_RCC_GetPCLK1Freq();
  125. #elif defined(APB1PERIPH_BASE) || defined(APB2PERIPH_BASE)
  126. /* The SPI clock for H7 cannot be configured with a peripheral bus clock, so it needs to be written separately */
  127. #if defined(SOC_SERIES_STM32H7)
  128. /* When the configuration is generated using CUBEMX, the configuration for the SPI clock is placed in the HAL_SPI_Init function.
  129. Therefore, it is necessary to initialize and configure the SPI clock to automatically configure the frequency division */
  130. HAL_SPI_Init(spi_handle);
  131. SPI_CLOCK = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
  132. #else
  133. if ((rt_uint32_t)spi_drv->config->Instance >= APB2PERIPH_BASE)
  134. {
  135. SPI_CLOCK = HAL_RCC_GetPCLK2Freq();
  136. }
  137. else
  138. {
  139. SPI_CLOCK = HAL_RCC_GetPCLK1Freq();
  140. }
  141. #endif /* SOC_SERIES_STM32H7) */
  142. #endif /* APBPERIPH_BASE */
  143. if (cfg->max_hz >= SPI_CLOCK / 2)
  144. {
  145. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
  146. }
  147. else if (cfg->max_hz >= SPI_CLOCK / 4)
  148. {
  149. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
  150. }
  151. else if (cfg->max_hz >= SPI_CLOCK / 8)
  152. {
  153. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
  154. }
  155. else if (cfg->max_hz >= SPI_CLOCK / 16)
  156. {
  157. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
  158. }
  159. else if (cfg->max_hz >= SPI_CLOCK / 32)
  160. {
  161. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
  162. }
  163. else if (cfg->max_hz >= SPI_CLOCK / 64)
  164. {
  165. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
  166. }
  167. else if (cfg->max_hz >= SPI_CLOCK / 128)
  168. {
  169. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
  170. }
  171. else
  172. {
  173. /* min prescaler 256 */
  174. spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
  175. }
  176. LOG_D("sys freq: %d, pclk freq: %d, SPI limiting freq: %d, SPI usage freq: %d",
  177. #if defined(SOC_SERIES_STM32MP1)
  178. HAL_RCC_GetSystemCoreClockFreq(),
  179. #else
  180. HAL_RCC_GetSysClockFreq(),
  181. #endif
  182. SPI_CLOCK,
  183. cfg->max_hz,
  184. SPI_CLOCK / (rt_size_t)pow(2,(spi_handle->Init.BaudRatePrescaler >> 28) + 1));
  185. if (cfg->mode & RT_SPI_MSB)
  186. {
  187. spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
  188. }
  189. else
  190. {
  191. spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;
  192. }
  193. spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
  194. spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  195. spi_handle->State = HAL_SPI_STATE_RESET;
  196. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32WB)
  197. spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
  198. #elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  199. spi_handle->Init.Mode = SPI_MODE_MASTER;
  200. spi_handle->Init.NSS = SPI_NSS_SOFT;
  201. spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
  202. spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
  203. spi_handle->Init.CRCPolynomial = 7;
  204. spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
  205. spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
  206. spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
  207. spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
  208. spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
  209. spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
  210. spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE;
  211. spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA;
  212. #endif
  213. if (HAL_SPI_Init(spi_handle) != HAL_OK)
  214. {
  215. return -RT_EIO;
  216. }
  217. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
  218. || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32WB)
  219. SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
  220. #endif
  221. /* DMA configuration */
  222. if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
  223. {
  224. HAL_DMA_Init(&spi_drv->dma.handle_rx);
  225. __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
  226. /* NVIC configuration for DMA transfer complete interrupt */
  227. HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);
  228. HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);
  229. }
  230. if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
  231. {
  232. HAL_DMA_Init(&spi_drv->dma.handle_tx);
  233. __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
  234. /* NVIC configuration for DMA transfer complete interrupt */
  235. HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 1, 0);
  236. HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
  237. }
  238. if(spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG || spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
  239. {
  240. HAL_NVIC_SetPriority(spi_drv->config->irq_type, 2, 0);
  241. HAL_NVIC_EnableIRQ(spi_drv->config->irq_type);
  242. }
  243. LOG_D("%s init done", spi_drv->config->bus_name);
  244. return RT_EOK;
  245. }
  246. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  247. {
  248. #define DMA_TRANS_MIN_LEN 10 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */
  249. HAL_StatusTypeDef state = HAL_OK;
  250. rt_size_t message_length, already_send_length;
  251. rt_uint16_t send_length;
  252. rt_uint8_t *recv_buf;
  253. const rt_uint8_t *send_buf;
  254. RT_ASSERT(device != RT_NULL);
  255. RT_ASSERT(device->bus != RT_NULL);
  256. RT_ASSERT(message != RT_NULL);
  257. struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
  258. SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
  259. if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  260. {
  261. if (device->config.mode & RT_SPI_CS_HIGH)
  262. rt_pin_write(device->cs_pin, PIN_HIGH);
  263. else
  264. rt_pin_write(device->cs_pin, PIN_LOW);
  265. }
  266. LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
  267. LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
  268. spi_drv->config->bus_name,
  269. (uint32_t)message->send_buf,
  270. (uint32_t)message->recv_buf, message->length);
  271. message_length = message->length;
  272. recv_buf = message->recv_buf;
  273. send_buf = message->send_buf;
  274. while (message_length)
  275. {
  276. /* the HAL library use uint16 to save the data length */
  277. if (message_length > 65535)
  278. {
  279. send_length = 65535;
  280. message_length = message_length - 65535;
  281. }
  282. else
  283. {
  284. send_length = message_length;
  285. message_length = 0;
  286. }
  287. /* calculate the start address */
  288. already_send_length = message->length - send_length - message_length;
  289. /* avoid null pointer problems */
  290. if (message->send_buf)
  291. {
  292. send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
  293. }
  294. if (message->recv_buf)
  295. {
  296. recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
  297. }
  298. rt_uint32_t* dma_aligned_buffer = RT_NULL;
  299. rt_uint32_t* p_txrx_buffer = RT_NULL;
  300. if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN))
  301. {
  302. #if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
  303. if (RT_IS_ALIGN((rt_uint32_t)send_buf, 32)) /* aligned with 32 bytes? */
  304. {
  305. p_txrx_buffer = (rt_uint32_t *)send_buf; /* send_buf aligns with 32 bytes, no more operations */
  306. }
  307. else
  308. {
  309. /* send_buf doesn't align with 32 bytes, so creat a cache buffer with 32 bytes aligned */
  310. dma_aligned_buffer = (rt_uint32_t *)rt_malloc_align(send_length, 32);
  311. rt_memcpy(dma_aligned_buffer, send_buf, send_length);
  312. p_txrx_buffer = dma_aligned_buffer;
  313. }
  314. rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_aligned_buffer, send_length);
  315. #else
  316. if (RT_IS_ALIGN((rt_uint32_t)send_buf, 4)) /* aligned with 4 bytes? */
  317. {
  318. p_txrx_buffer = (rt_uint32_t *)send_buf; /* send_buf aligns with 4 bytes, no more operations */
  319. }
  320. else
  321. {
  322. /* send_buf doesn't align with 4 bytes, so creat a cache buffer with 4 bytes aligned */
  323. dma_aligned_buffer = (rt_uint32_t *)rt_malloc(send_length); /* aligned with RT_ALIGN_SIZE (8 bytes by default) */
  324. rt_memcpy(dma_aligned_buffer, send_buf, send_length);
  325. p_txrx_buffer = dma_aligned_buffer;
  326. }
  327. #endif /* SOC_SERIES_STM32H7 || SOC_SERIES_STM32F7 */
  328. }
  329. /* start once data exchange in DMA mode */
  330. if (message->send_buf && message->recv_buf)
  331. {
  332. if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN))
  333. {
  334. state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)p_txrx_buffer, (uint8_t *)p_txrx_buffer, send_length);
  335. }
  336. else if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN))
  337. {
  338. /* same as Tx ONLY. It will not receive SPI data any more. */
  339. state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)p_txrx_buffer, send_length);
  340. }
  341. else if ((spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN))
  342. {
  343. state = HAL_ERROR;
  344. LOG_E("It shoule be enabled both BSP_SPIx_TX_USING_DMA and BSP_SPIx_TX_USING_DMA flag, if wants to use SPI DMA Rx singly.");
  345. break;
  346. }
  347. else
  348. {
  349. state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length, 1000);
  350. }
  351. }
  352. else if (message->send_buf)
  353. {
  354. if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN))
  355. {
  356. state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)p_txrx_buffer, send_length);
  357. }
  358. else
  359. {
  360. state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, send_length, 1000);
  361. }
  362. if (message->cs_release && (device->config.mode & RT_SPI_3WIRE))
  363. {
  364. /* release the CS by disable SPI when using 3 wires SPI */
  365. __HAL_SPI_DISABLE(spi_handle);
  366. }
  367. }
  368. else if(message->recv_buf)
  369. {
  370. rt_memset((uint8_t *)recv_buf, 0xff, send_length);
  371. if ((spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN))
  372. {
  373. state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)p_txrx_buffer, send_length);
  374. }
  375. else
  376. {
  377. /* clear the old error flag */
  378. __HAL_SPI_CLEAR_OVRFLAG(spi_handle);
  379. state = HAL_SPI_Receive(spi_handle, (uint8_t *)recv_buf, send_length, 1000);
  380. }
  381. }
  382. else
  383. {
  384. state = HAL_ERROR;
  385. LOG_E("message->send_buf and message->recv_buf are both NULL!");
  386. }
  387. if (state != HAL_OK)
  388. {
  389. LOG_E("SPI transfer error: %d", state);
  390. message->length = 0;
  391. spi_handle->State = HAL_SPI_STATE_READY;
  392. break;
  393. }
  394. else
  395. {
  396. LOG_D("%s transfer done", spi_drv->config->bus_name);
  397. }
  398. /* For simplicity reasons, this example is just waiting till the end of the
  399. transfer, but application may perform other tasks while transfer operation
  400. is ongoing. */
  401. if ((spi_drv->spi_dma_flag & (SPI_USING_TX_DMA_FLAG | SPI_USING_RX_DMA_FLAG)) && (send_length >= DMA_TRANS_MIN_LEN))
  402. {
  403. /* blocking the thread,and the other tasks can run */
  404. if (rt_completion_wait(&spi_drv->cpt, 1000) != RT_EOK)
  405. {
  406. state = HAL_ERROR;
  407. LOG_E("wait for DMA interrupt overtime!");
  408. break;
  409. }
  410. }
  411. else
  412. {
  413. while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
  414. }
  415. if(dma_aligned_buffer != RT_NULL) /* re-aligned, so need to copy the data to recv_buf */
  416. {
  417. if(recv_buf != RT_NULL)
  418. {
  419. #if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
  420. rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, p_txrx_buffer, send_length);
  421. #endif /* SOC_SERIES_STM32H7 || SOC_SERIES_STM32F7 */
  422. rt_memcpy(recv_buf, p_txrx_buffer, send_length);
  423. }
  424. #if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
  425. rt_free_align(dma_aligned_buffer);
  426. #else
  427. rt_free(dma_aligned_buffer);
  428. #endif /* SOC_SERIES_STM32H7 || SOC_SERIES_STM32F7 */
  429. }
  430. }
  431. if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  432. {
  433. if (device->config.mode & RT_SPI_CS_HIGH)
  434. rt_pin_write(device->cs_pin, PIN_LOW);
  435. else
  436. rt_pin_write(device->cs_pin, PIN_HIGH);
  437. }
  438. if(state != HAL_OK)
  439. {
  440. return -RT_ERROR;
  441. }
  442. return message->length;
  443. }
  444. static rt_err_t spi_configure(struct rt_spi_device *device,
  445. struct rt_spi_configuration *configuration)
  446. {
  447. RT_ASSERT(device != RT_NULL);
  448. RT_ASSERT(configuration != RT_NULL);
  449. struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
  450. spi_drv->cfg = configuration;
  451. return stm32_spi_init(spi_drv, configuration);
  452. }
  453. static const struct rt_spi_ops stm_spi_ops =
  454. {
  455. .configure = spi_configure,
  456. .xfer = spixfer,
  457. };
  458. static int rt_hw_spi_bus_init(void)
  459. {
  460. rt_err_t result;
  461. for (rt_size_t i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
  462. {
  463. spi_bus_obj[i].config = &spi_config[i];
  464. spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
  465. spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
  466. if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
  467. {
  468. /* Configure the DMA handler for Transmission process */
  469. spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
  470. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  471. spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
  472. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  473. spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
  474. #endif
  475. #ifndef SOC_SERIES_STM32U5
  476. spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
  477. spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
  478. spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
  479. spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  480. spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  481. spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
  482. spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
  483. #endif
  484. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
  485. spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  486. spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
  487. spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
  488. spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
  489. #endif
  490. {
  491. rt_uint32_t tmpreg = 0x00U;
  492. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
  493. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  494. SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
  495. tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
  496. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  497. SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
  498. /* Delay after an RCC peripheral clock enabling */
  499. tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
  500. #elif defined(SOC_SERIES_STM32MP1)
  501. __HAL_RCC_DMAMUX_CLK_ENABLE();
  502. SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
  503. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
  504. #endif
  505. UNUSED(tmpreg); /* To avoid compiler warnings */
  506. }
  507. }
  508. if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
  509. {
  510. /* Configure the DMA handler for Transmission process */
  511. spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
  512. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  513. spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
  514. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  515. spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
  516. #endif
  517. #ifndef SOC_SERIES_STM32U5
  518. spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
  519. spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  520. spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
  521. spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  522. spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  523. spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
  524. spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
  525. #endif
  526. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
  527. spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  528. spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
  529. spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
  530. spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
  531. #endif
  532. {
  533. rt_uint32_t tmpreg = 0x00U;
  534. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
  535. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  536. SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
  537. tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
  538. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
  539. SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
  540. /* Delay after an RCC peripheral clock enabling */
  541. tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
  542. #elif defined(SOC_SERIES_STM32MP1)
  543. __HAL_RCC_DMAMUX_CLK_ENABLE();
  544. SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
  545. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
  546. #endif
  547. UNUSED(tmpreg); /* To avoid compiler warnings */
  548. }
  549. }
  550. /* initialize completion object */
  551. rt_completion_init(&spi_bus_obj[i].cpt);
  552. result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
  553. RT_ASSERT(result == RT_EOK);
  554. LOG_D("%s bus init done", spi_config[i].bus_name);
  555. }
  556. return result;
  557. }
  558. /**
  559. * Attach the spi device to SPI bus, this function must be used after initialization.
  560. */
  561. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
  562. {
  563. RT_ASSERT(bus_name != RT_NULL);
  564. RT_ASSERT(device_name != RT_NULL);
  565. rt_err_t result;
  566. struct rt_spi_device *spi_device;
  567. /* attach the device to spi bus*/
  568. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  569. RT_ASSERT(spi_device != RT_NULL);
  570. result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
  571. if (result != RT_EOK)
  572. {
  573. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  574. }
  575. RT_ASSERT(result == RT_EOK);
  576. LOG_D("%s attach to %s done", device_name, bus_name);
  577. return result;
  578. }
  579. #if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
  580. void SPI1_IRQHandler(void)
  581. {
  582. /* enter interrupt */
  583. rt_interrupt_enter();
  584. HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
  585. /* leave interrupt */
  586. rt_interrupt_leave();
  587. }
  588. #endif
  589. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
  590. /**
  591. * @brief This function handles DMA Rx interrupt request.
  592. * @param None
  593. * @retval None
  594. */
  595. void SPI1_DMA_RX_IRQHandler(void)
  596. {
  597. /* enter interrupt */
  598. rt_interrupt_enter();
  599. HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
  600. /* leave interrupt */
  601. rt_interrupt_leave();
  602. }
  603. #endif
  604. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
  605. /**
  606. * @brief This function handles DMA Tx interrupt request.
  607. * @param None
  608. * @retval None
  609. */
  610. void SPI1_DMA_TX_IRQHandler(void)
  611. {
  612. /* enter interrupt */
  613. rt_interrupt_enter();
  614. HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_tx);
  615. /* leave interrupt */
  616. rt_interrupt_leave();
  617. }
  618. #endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
  619. #if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
  620. void SPI2_IRQHandler(void)
  621. {
  622. /* enter interrupt */
  623. rt_interrupt_enter();
  624. HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
  625. /* leave interrupt */
  626. rt_interrupt_leave();
  627. }
  628. #endif
  629. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
  630. /**
  631. * @brief This function handles DMA Rx interrupt request.
  632. * @param None
  633. * @retval None
  634. */
  635. void SPI2_DMA_RX_IRQHandler(void)
  636. {
  637. /* enter interrupt */
  638. rt_interrupt_enter();
  639. HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_rx);
  640. /* leave interrupt */
  641. rt_interrupt_leave();
  642. }
  643. #endif
  644. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
  645. /**
  646. * @brief This function handles DMA Tx interrupt request.
  647. * @param None
  648. * @retval None
  649. */
  650. void SPI2_DMA_TX_IRQHandler(void)
  651. {
  652. /* enter interrupt */
  653. rt_interrupt_enter();
  654. HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
  655. /* leave interrupt */
  656. rt_interrupt_leave();
  657. }
  658. #endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
  659. #if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
  660. void SPI3_IRQHandler(void)
  661. {
  662. /* enter interrupt */
  663. rt_interrupt_enter();
  664. HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle);
  665. /* leave interrupt */
  666. rt_interrupt_leave();
  667. }
  668. #endif
  669. #if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
  670. /**
  671. * @brief This function handles DMA Rx interrupt request.
  672. * @param None
  673. * @retval None
  674. */
  675. void SPI3_DMA_RX_IRQHandler(void)
  676. {
  677. /* enter interrupt */
  678. rt_interrupt_enter();
  679. HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_rx);
  680. /* leave interrupt */
  681. rt_interrupt_leave();
  682. }
  683. #endif
  684. #if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
  685. /**
  686. * @brief This function handles DMA Tx interrupt request.
  687. * @param None
  688. * @retval None
  689. */
  690. void SPI3_DMA_TX_IRQHandler(void)
  691. {
  692. /* enter interrupt */
  693. rt_interrupt_enter();
  694. HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_tx);
  695. /* leave interrupt */
  696. rt_interrupt_leave();
  697. }
  698. #endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
  699. #if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA)
  700. void SPI4_IRQHandler(void)
  701. {
  702. /* enter interrupt */
  703. rt_interrupt_enter();
  704. HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle);
  705. /* leave interrupt */
  706. rt_interrupt_leave();
  707. }
  708. #endif
  709. #if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
  710. /**
  711. * @brief This function handles DMA Rx interrupt request.
  712. * @param None
  713. * @retval None
  714. */
  715. void SPI4_DMA_RX_IRQHandler(void)
  716. {
  717. /* enter interrupt */
  718. rt_interrupt_enter();
  719. HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_rx);
  720. /* leave interrupt */
  721. rt_interrupt_leave();
  722. }
  723. #endif
  724. #if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
  725. /**
  726. * @brief This function handles DMA Tx interrupt request.
  727. * @param None
  728. * @retval None
  729. */
  730. void SPI4_DMA_TX_IRQHandler(void)
  731. {
  732. /* enter interrupt */
  733. rt_interrupt_enter();
  734. HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_tx);
  735. /* leave interrupt */
  736. rt_interrupt_leave();
  737. }
  738. #endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
  739. #if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA)
  740. void SPI5_IRQHandler(void)
  741. {
  742. /* enter interrupt */
  743. rt_interrupt_enter();
  744. HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle);
  745. /* leave interrupt */
  746. rt_interrupt_leave();
  747. }
  748. #endif
  749. #if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
  750. /**
  751. * @brief This function handles DMA Rx interrupt request.
  752. * @param None
  753. * @retval None
  754. */
  755. void SPI5_DMA_RX_IRQHandler(void)
  756. {
  757. /* enter interrupt */
  758. rt_interrupt_enter();
  759. HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_rx);
  760. /* leave interrupt */
  761. rt_interrupt_leave();
  762. }
  763. #endif
  764. #if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
  765. /**
  766. * @brief This function handles DMA Tx interrupt request.
  767. * @param None
  768. * @retval None
  769. */
  770. void SPI5_DMA_TX_IRQHandler(void)
  771. {
  772. /* enter interrupt */
  773. rt_interrupt_enter();
  774. HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_tx);
  775. /* leave interrupt */
  776. rt_interrupt_leave();
  777. }
  778. #endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
  779. #if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
  780. /**
  781. * @brief This function handles DMA Rx interrupt request.
  782. * @param None
  783. * @retval None
  784. */
  785. void SPI6_DMA_RX_IRQHandler(void)
  786. {
  787. /* enter interrupt */
  788. rt_interrupt_enter();
  789. HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_rx);
  790. /* leave interrupt */
  791. rt_interrupt_leave();
  792. }
  793. #endif
  794. #if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
  795. /**
  796. * @brief This function handles DMA Tx interrupt request.
  797. * @param None
  798. * @retval None
  799. */
  800. void SPI6_DMA_TX_IRQHandler(void)
  801. {
  802. /* enter interrupt */
  803. rt_interrupt_enter();
  804. HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_tx);
  805. /* leave interrupt */
  806. rt_interrupt_leave();
  807. }
  808. #endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
  809. static void stm32_get_dma_info(void)
  810. {
  811. #ifdef BSP_SPI1_RX_USING_DMA
  812. spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  813. static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
  814. spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
  815. #endif
  816. #ifdef BSP_SPI1_TX_USING_DMA
  817. spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  818. static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
  819. spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
  820. #endif
  821. #ifdef BSP_SPI2_RX_USING_DMA
  822. spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  823. static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
  824. spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
  825. #endif
  826. #ifdef BSP_SPI2_TX_USING_DMA
  827. spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  828. static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
  829. spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
  830. #endif
  831. #ifdef BSP_SPI3_RX_USING_DMA
  832. spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  833. static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
  834. spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
  835. #endif
  836. #ifdef BSP_SPI3_TX_USING_DMA
  837. spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  838. static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
  839. spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
  840. #endif
  841. #ifdef BSP_SPI4_RX_USING_DMA
  842. spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  843. static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
  844. spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
  845. #endif
  846. #ifdef BSP_SPI4_TX_USING_DMA
  847. spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  848. static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
  849. spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
  850. #endif
  851. #ifdef BSP_SPI5_RX_USING_DMA
  852. spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  853. static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
  854. spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
  855. #endif
  856. #ifdef BSP_SPI5_TX_USING_DMA
  857. spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  858. static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
  859. spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
  860. #endif
  861. #ifdef BSP_SPI6_RX_USING_DMA
  862. spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
  863. static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
  864. spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
  865. #endif
  866. #ifdef BSP_SPI6_TX_USING_DMA
  867. spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
  868. static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
  869. spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
  870. #endif
  871. }
  872. void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
  873. {
  874. struct stm32_spi *spi_drv = rt_container_of(hspi, struct stm32_spi, handle);
  875. rt_completion_done(&spi_drv->cpt);
  876. }
  877. void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
  878. {
  879. struct stm32_spi *spi_drv = rt_container_of(hspi, struct stm32_spi, handle);
  880. rt_completion_done(&spi_drv->cpt);
  881. }
  882. void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
  883. {
  884. struct stm32_spi *spi_drv = rt_container_of(hspi, struct stm32_spi, handle);
  885. rt_completion_done(&spi_drv->cpt);
  886. }
  887. #if defined(SOC_SERIES_STM32F0)
  888. void SPI1_DMA_RX_TX_IRQHandler(void)
  889. {
  890. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
  891. SPI1_DMA_TX_IRQHandler();
  892. #endif
  893. #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
  894. SPI1_DMA_RX_IRQHandler();
  895. #endif
  896. }
  897. void SPI2_DMA_RX_TX_IRQHandler(void)
  898. {
  899. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
  900. SPI2_DMA_TX_IRQHandler();
  901. #endif
  902. #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
  903. SPI2_DMA_RX_IRQHandler();
  904. #endif
  905. }
  906. #endif /* SOC_SERIES_STM32F0 */
  907. int rt_hw_spi_init(void)
  908. {
  909. stm32_get_dma_info();
  910. return rt_hw_spi_bus_init();
  911. }
  912. INIT_BOARD_EXPORT(rt_hw_spi_init);
  913. #endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4 || BSP_USING_SPI5 */
  914. #endif /* BSP_USING_SPI */