drv_gpio.h 8.4 KB

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  1. /*
  2. * File : drv_gpio.h
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2017, RT-Thread Development Team
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * Change Logs:
  21. * Date Author Notes
  22. * 2018-02-08 RT-Thread the first version
  23. */
  24. #ifndef __DRV_GPIO_H__
  25. #define __DRV_GPIO_H__
  26. /* IO default function */
  27. #define IO_INPUT (0x00)
  28. #define IO_OUTPUT (0x01)
  29. #define IO_DISABLE (0x07)
  30. #define IO_FUN_1 (0x02)
  31. #define IO_FUN_2 (0x03)
  32. #define IO_FUN_3 (0x04)
  33. #define IO_FUN_4 (0x05)
  34. #define IO_FUN_5 (0x06)
  35. /* IO port */
  36. enum gpio_port
  37. {
  38. GPIO_PORT_A = 0,
  39. GPIO_PORT_B,
  40. GPIO_PORT_C,
  41. GPIO_PORT_D,
  42. GPIO_PORT_E,
  43. GPIO_PORT_F,
  44. GPIO_PORT_NUM,
  45. };
  46. /* IO pin */
  47. enum gpio_pin
  48. {
  49. GPIO_PIN_0 = 0,
  50. GPIO_PIN_1,
  51. GPIO_PIN_2,
  52. GPIO_PIN_3,
  53. GPIO_PIN_4,
  54. GPIO_PIN_5,
  55. GPIO_PIN_6,
  56. GPIO_PIN_7,
  57. GPIO_PIN_8,
  58. GPIO_PIN_9,
  59. GPIO_PIN_10,
  60. GPIO_PIN_11,
  61. GPIO_PIN_12,
  62. GPIO_PIN_13,
  63. GPIO_PIN_14,
  64. GPIO_PIN_15,
  65. GPIO_PIN_16,
  66. GPIO_PIN_17,
  67. GPIO_PIN_18,
  68. GPIO_PIN_19,
  69. GPIO_PIN_20,
  70. GPIO_PIN_21,
  71. GPIO_PIN_22,
  72. GPIO_PIN_23,
  73. GPIO_PIN_NUM,
  74. };
  75. /* Drive level */
  76. enum gpio_drv_level
  77. {
  78. DRV_LEVEL_0 = 0,
  79. DRV_LEVEL_1,
  80. DRV_LEVEL_2,
  81. DRV_LEVEL_3,
  82. };
  83. /* Pull mode */
  84. enum gpio_pull
  85. {
  86. PULL_DISABLE = 0,
  87. PULL_UP,
  88. PULL_DOWN,
  89. };
  90. /* interrupt type */
  91. enum gpio_irq_type
  92. {
  93. POSITIVE = 0,
  94. NEGATIVE,
  95. HIGH,
  96. LOW,
  97. DOUBLE,
  98. };
  99. enum gpio_irq_clock
  100. {
  101. GPIO_IRQ_LOSC_32KHZ = 0,
  102. GPIO_IRQ_HOSC_24MHZ
  103. };
  104. enum gpio_direction_type
  105. {
  106. DEBOUNCE_PRE_SCALE_1 = 0,
  107. DEBOUNCE_PRE_SCALE_2,
  108. DEBOUNCE_PRE_SCALE_4,
  109. DEBOUNCE_PRE_SCALE_8,
  110. DEBOUNCE_PRE_SCALE_16,
  111. DEBOUNCE_PRE_SCALE_32,
  112. DEBOUNCE_PRE_SCALE_64,
  113. DEBOUNCE_PRE_SCALE_128,
  114. };
  115. struct gpio_irq_def
  116. {
  117. void *irq_arg[32];
  118. void (*irq_cb[32])(void *param);
  119. };
  120. #define GPIO_BASE_ADDR (0x01C20800)
  121. #define GPIOn_CFG_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x00)
  122. #define GPIOn_DATA_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x10)
  123. #define GPIOn_DRV_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x14)
  124. #define GPIOn_PUL_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x1C)
  125. #define GPIOn_INT_CFG_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x00)
  126. #define GPIOn_INT_CTRL_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x10)
  127. #define GPIOn_INT_STA_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x14)
  128. #define GPIOn_INT_DEB_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x18)
  129. struct tina_gpio
  130. {
  131. volatile rt_uint32_t pa_cfg0; /* 0x00 */
  132. volatile rt_uint32_t pa_cfg1; /* 0x04 */
  133. volatile rt_uint32_t pa_cfg2; /* 0x08 */
  134. volatile rt_uint32_t pa_cfg3; /* 0x0C */
  135. volatile rt_uint32_t pa_data; /* 0x10 */
  136. volatile rt_uint32_t pa_drv0; /* 0x14 */
  137. volatile rt_uint32_t pa_drv1; /* 0x18 */
  138. volatile rt_uint32_t pa_pul0; /* 0x1C */
  139. volatile rt_uint32_t pa_pul1; /* 0x20 */
  140. volatile rt_uint32_t pb_cfg0; /* 0x24 */
  141. volatile rt_uint32_t pb_cfg1; /* 0x28 */
  142. volatile rt_uint32_t pb_cfg2; /* 0x2C */
  143. volatile rt_uint32_t pb_cfg3; /* 0x30 */
  144. volatile rt_uint32_t pb_data; /* 0x34 */
  145. volatile rt_uint32_t pb_drv0; /* 0x38 */
  146. volatile rt_uint32_t pb_drv1; /* 0x3C */
  147. volatile rt_uint32_t pb_pul0; /* 0x40 */
  148. volatile rt_uint32_t pb_pul1; /* 0x44 */
  149. volatile rt_uint32_t pc_cfg0; /* 0x48 */
  150. volatile rt_uint32_t pc_cfg1; /* 0x4C */
  151. volatile rt_uint32_t pc_cfg2; /* 0x50 */
  152. volatile rt_uint32_t pc_cfg3; /* 0x54 */
  153. volatile rt_uint32_t pc_data; /* 0x58 */
  154. volatile rt_uint32_t pc_drv0; /* 0x5C */
  155. volatile rt_uint32_t pc_drv1; /* 0x60 */
  156. volatile rt_uint32_t pc_pul0; /* 0x64 */
  157. volatile rt_uint32_t pc_pul1; /* 0x68 */
  158. volatile rt_uint32_t pd_cfg0; /* 0x6C */
  159. volatile rt_uint32_t pd_cfg1; /* 0x70 */
  160. volatile rt_uint32_t pd_cfg2; /* 0x74 */
  161. volatile rt_uint32_t pd_cfg3; /* 0x78 */
  162. volatile rt_uint32_t pd_data; /* 0x7C */
  163. volatile rt_uint32_t pd_drv0; /* 0x80 */
  164. volatile rt_uint32_t pd_drv1; /* 0x84 */
  165. volatile rt_uint32_t pd_pul0; /* 0x88 */
  166. volatile rt_uint32_t pd_pul1; /* 0x8C */
  167. volatile rt_uint32_t pe_cfg0; /* 0x90 */
  168. volatile rt_uint32_t pe_cfg1; /* 0x94 */
  169. volatile rt_uint32_t pe_cfg2; /* 0x98 */
  170. volatile rt_uint32_t pe_cfg3; /* 0x9C */
  171. volatile rt_uint32_t pe_data; /* 0xA0 */
  172. volatile rt_uint32_t pe_drv0; /* 0xA4 */
  173. volatile rt_uint32_t pe_drv1; /* 0xA8 */
  174. volatile rt_uint32_t pe_pul0; /* 0xAC */
  175. volatile rt_uint32_t pe_pul1; /* 0xB0 */
  176. volatile rt_uint32_t pf_cfg0; /* 0xB4 */
  177. volatile rt_uint32_t pf_cfg1; /* 0xB8 */
  178. volatile rt_uint32_t pf_cfg2; /* 0xBC */
  179. volatile rt_uint32_t pf_cfg3; /* 0xC0 */
  180. volatile rt_uint32_t pf_data; /* 0xC4 */
  181. volatile rt_uint32_t pf_drv0; /* 0xC8 */
  182. volatile rt_uint32_t pf_drv1; /* 0xCC */
  183. volatile rt_uint32_t pf_pul0; /* 0xD0 */
  184. volatile rt_uint32_t reserved0[76];
  185. volatile rt_uint32_t pd_int_cfg0; /* 0x200 */
  186. volatile rt_uint32_t pd_int_cfg1; /* 0x204 */
  187. volatile rt_uint32_t pd_int_cfg2; /* 0x208 */
  188. volatile rt_uint32_t pd_int_cfg3; /* 0x20C */
  189. volatile rt_uint32_t pd_int_ctrl; /* 0x210 */
  190. volatile rt_uint32_t pd_int_sta; /* 0x214 */
  191. volatile rt_uint32_t pd_int_deb; /* 0x218 */
  192. volatile rt_uint32_t reserved1;
  193. volatile rt_uint32_t pe_int_cfg0; /* 0x220 */
  194. volatile rt_uint32_t pe_int_cfg1; /* 0x224 */
  195. volatile rt_uint32_t pe_int_cfg2; /* 0x228 */
  196. volatile rt_uint32_t pe_int_cfg3; /* 0x22C */
  197. volatile rt_uint32_t pe_int_ctrl; /* 0x230 */
  198. volatile rt_uint32_t pe_int_sta; /* 0x234 */
  199. volatile rt_uint32_t pe_int_deb; /* 0x238 */
  200. volatile rt_uint32_t reserved2;
  201. volatile rt_uint32_t pf_int_cfg0; /* 0x240 */
  202. volatile rt_uint32_t pf_int_cfg1; /* 0x244 */
  203. volatile rt_uint32_t pf_int_cfg2; /* 0x248 */
  204. volatile rt_uint32_t pf_int_cfg3; /* 0x24C */
  205. volatile rt_uint32_t pf_int_ctrl; /* 0x250 */
  206. volatile rt_uint32_t pf_int_sta; /* 0x254 */
  207. volatile rt_uint32_t pf_int_deb; /* 0x258 */
  208. volatile rt_uint32_t reserved3[26];
  209. volatile rt_uint32_t sdr_pad_drv; /* 0x2C0*/
  210. volatile rt_uint32_t sdr_pad_pul; /* 0x2C4 */
  211. };
  212. typedef struct tina_gpio *tina_gpio_t;
  213. #define GPIO ((tina_gpio_t)GPIO_BASE_ADDR)
  214. int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func);
  215. int gpio_set_value(enum gpio_port port, enum gpio_pin pin, rt_uint8_t value);
  216. int gpio_get_value(enum gpio_port port, enum gpio_pin pin);
  217. int gpio_set_pull_mode(enum gpio_port port, enum gpio_pin pin, enum gpio_pull pull);
  218. int gpio_set_drive_level(enum gpio_port port, enum gpio_pin pin, enum gpio_drv_level level);
  219. void gpio_direction_input(enum gpio_port port, enum gpio_pin pin);
  220. void gpio_direction_output(enum gpio_port port, enum gpio_pin pin, int value);
  221. void gpio_irq_enable(enum gpio_port port, enum gpio_pin pin);
  222. void gpio_irq_disable(enum gpio_port port, enum gpio_pin pin);
  223. void gpio_set_irq_type(enum gpio_port port, enum gpio_pin pin, enum gpio_irq_type irq_type);
  224. void gpio_select_irq_clock(enum gpio_port port, enum gpio_irq_clock clock);
  225. void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler);
  226. void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg);
  227. int rt_hw_gpio_init(void);
  228. #endif /* __DRV_GPIO_H__ */