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fh8620
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platform
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plat-v2
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fh_pmu.h

fh_pmu.h 2.3 KB
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  1. /*
    2. 

  2.  *  This file is part of FH8620 BSP for RT-Thread distribution.
    3. 

  3.  *
    4. 

  4.  *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
    5. 

  5.  *	All rights reserved
    6. 

  6.  *
    7. 

  7.  *  This program is free software; you can redistribute it and/or modify
    8. 

  8.  *  it under the terms of the GNU General Public License as published by
    9. 

  9.  *  the Free Software Foundation; either version 2 of the License, or
    10. 

  10.  *  (at your option) any later version.
    11. 

  11.  *
    12. 

  12.  *  This program is distributed in the hope that it will be useful,
    13. 

  13.  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    14. 

  14.  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    15. 

  15.  *  GNU General Public License for more details.
    16. 

  16.  *
    17. 

  17.  *  You should have received a copy of the GNU General Public License along
    18. 

  18.  *  with this program; if not, write to the Free Software Foundation, Inc.,
    19. 

  19.  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
    20. 

  20.  *
    21. 

  21.  *	Visit http://www.fullhan.com to get contact with Fullhan.
    22. 

  22.  *
    23. 

  23.  * Change Logs:
    24. 

  24.  * Date           Author       Notes
    25. 

  25.  */
    26. 

  26.  
    27. 

  27. #ifndef FH_PMU_H_
    28. 

  28. #define FH_PMU_H_
    29. 

  29. 

  30. #include <rtdef.h>
    31. 

  31. 

  32. #define     REG_PMU_CHIP_ID             (0x000)
    33. 

  33. #define     REG_PMU_IP_VER              (0x004)
    34. 

  34. #define     REG_PMU_FW_VER              (0x008)
    35. 

  35. #define     REG_PMU_SYS_CTRL            (0x00c)
    36. 

  36. #define     REG_PMU_PLL0_CTRL           (0x010)
    37. 

  37. #define     REG_PMU_PLL1_CTRL           (0x014)
    38. 

  38. #define     REG_PMU_ARC_CLK_GATE        (0x018)
    39. 

  39. #define     REG_PMU_CLK_GATE        	(0x01c)
    40. 

  40. #define     REG_PMU_CLK_SEL             (0x020)
    41. 

  41. #define     REG_PMU_CLK_DIV0            (0x024)
    42. 

  42. #define     REG_PMU_CLK_DIV1            (0x028)
    43. 

  43. #define     REG_PMU_CLK_DIV2            (0x02c)
    44. 

  44. #define     REG_PMU_CLK_DIV3            (0x030)
    45. 

  45. #define     REG_PMU_CLK_DIV4            (0x034)
    46. 

  46. #define     REG_PMU_CLK_DIV5            (0x038)
    47. 

  47. #define     REG_PMU_CLK_DIV6            (0x03c)
    48. 

  48. #define     REG_PMU_SWRST_MAIN_CTRL     (0x040)
    49. 

  49. #define     REG_PMU_SWRST_AXI_CTRL      (0x044)
    50. 

  50. #define     REG_PMU_SWRST_AHB_CTRL      (0x048)
    51. 

  51. #define     REG_PMU_SWRST_APB_CTRL      (0x04c)
    52. 

  52. #define     REG_PMU_VDAC_CTRL           (0x050)
    53. 

  53. #define     REG_PMU_MAC_REF_CLK_CFG     (0x0a4)
    54. 

  54. 

  55. int fh_pmu_read(rt_uint32_t offset,rt_uint32_t *value);
    56. 

  56. int fh_pmu_write(rt_uint32_t offset, const rt_uint32_t value);
    57. 

  57. int fh_pmu_write_mask(rt_uint32_t offset,const rt_uint32_t value, const rt_uint32_t mask);
    58. 

  58. 

  59. #endif /* FH_PMU_H_ */
    60.