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GD32F30x_standard_peripheral
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gd32f30x_spi.h

gd32f30x_spi.h 22 KB
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  1. /*!
    2. 

  2.     \file  gd32f30x_spi.h
    3. 

  3.     \brief definitions for the SPI
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2017 GigaDevice
    8. 

  8. 

  9.     2017-02-10, V1.0.1, firmware for GD32F30x
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F30X_SPI_H
    13. 

  13. #define GD32F30X_SPI_H
    14. 

  14. 

  15. #include "gd32f30x.h"
    16. 

  16. 

  17. /* SPIx(x=0,1,2) definitions */
    18. 

  18. #define SPI0                            (SPI_BASE + 0x0000F800U)
    19. 

  19. #define SPI1                            SPI_BASE
    20. 

  20. #define SPI2                            (SPI_BASE + 0x00000400U)
    21. 

  21. 

  22. /* SPI registers definitions */
    23. 

  23. #define SPI_CTL0(spix)                  REG32((spix) + 0x00U)                   /*!< SPI control register 0 */
    24. 

  24. #define SPI_CTL1(spix)                  REG32((spix) + 0x04U)                   /*!< SPI control register 1*/
    25. 

  25. #define SPI_STAT(spix)                  REG32((spix) + 0x08U)                   /*!< SPI status register */
    26. 

  26. #define SPI_DATA(spix)                  REG32((spix) + 0x0CU)                   /*!< SPI data register */
    27. 

  27. #define SPI_CRCPOLY(spix)               REG32((spix) + 0x10U)                   /*!< SPI CRC polynomial register */
    28. 

  28. #define SPI_RCRC(spix)                  REG32((spix) + 0x14U)                   /*!< SPI receive CRC register */
    29. 

  29. #define SPI_TCRC(spix)                  REG32((spix) + 0x18U)                   /*!< SPI transmit CRC register */
    30. 

  30. #define SPI_I2SCTL(spix)                REG32((spix) + 0x1CU)                   /*!< SPI I2S control register */
    31. 

  31. #define SPI_I2SPSC(spix)                REG32((spix) + 0x20U)                   /*!< SPI I2S clock prescaler register */
    32. 

  32. #define SPI_QCTL(spix)                  REG32((spix) + 0x80U)                   /*!< SPI quad mode control register(only SPI0) */
    33. 

  33. 

  34. /* bits definitions */
    35. 

  35. /* SPI_CTL0 */
    36. 

  36. #define SPI_CTL0_CKPH                   BIT(0)                                  /*!< clock phase selection*/
    37. 

  37. #define SPI_CTL0_CKPL                   BIT(1)                                  /*!< clock polarity selection */
    38. 

  38. #define SPI_CTL0_MSTMOD                 BIT(2)                                  /*!< master mode enable */
    39. 

  39. #define SPI_CTL0_PSC                    BITS(3,5)                               /*!< master clock prescaler selection */
    40. 

  40. #define SPI_CTL0_SPIEN                  BIT(6)                                  /*!< SPI enable*/
    41. 

  41. #define SPI_CTL0_LF                     BIT(7)                                  /*!< LSB first mode */
    42. 

  42. #define SPI_CTL0_SWNSS                  BIT(8)                                  /*!< NSS pin selection in NSS software mode */
    43. 

  43. #define SPI_CTL0_SWNSSEN                BIT(9)                                  /*!< NSS software mode selection */
    44. 

  44. #define SPI_CTL0_RO                     BIT(10)                                 /*!< receive only */
    45. 

  45. #define SPI_CTL0_FF16                   BIT(11)                                 /*!< data frame size */
    46. 

  46. #define SPI_CTL0_CRCNT                  BIT(12)                                 /*!< CRC next transfer */
    47. 

  47. #define SPI_CTL0_CRCEN                  BIT(13)                                 /*!< CRC calculation enable */
    48. 

  48. #define SPI_CTL0_BDOEN                  BIT(14)                                 /*!< bidirectional transmit output enable*/
    49. 

  49. #define SPI_CTL0_BDEN                   BIT(15)                                 /*!< bidirectional enable */
    50. 

  50. 

  51. /* SPI_CTL1 */
    52. 

  52. #define SPI_CTL1_DMAREN                 BIT(0)                                  /*!< receive buffer dma enable */
    53. 

  53. #define SPI_CTL1_DMATEN                 BIT(1)                                  /*!< transmit buffer dma enable */
    54. 

  54. #define SPI_CTL1_NSSDRV                 BIT(2)                                  /*!< drive NSS output */
    55. 

  55. #define SPI_CTL1_NSSP                   BIT(3)                                  /*!< SPI NSS pulse mode enable */
    56. 

  56. #define SPI_CTL1_TMOD                   BIT(4)                                  /*!< SPI TI mode enable */
    57. 

  57. #define SPI_CTL1_ERRIE                  BIT(5)                                  /*!< errors interrupt enable */
    58. 

  58. #define SPI_CTL1_RBNEIE                 BIT(6)                                  /*!< receive buffer not empty interrupt enable */
    59. 

  59. #define SPI_CTL1_TBEIE                  BIT(7)                                  /*!< transmit buffer empty interrupt enable */
    60. 

  60. 

  61. /* SPI_STAT */
    62. 

  62. #define SPI_STAT_RBNE                   BIT(0)                                  /*!< receive buffer not empty */
    63. 

  63. #define SPI_STAT_TBE                    BIT(1)                                  /*!< transmit buffer empty */
    64. 

  64. #define SPI_STAT_I2SCH                  BIT(2)                                  /*!< I2S channel side */
    65. 

  65. #define SPI_STAT_TXURERR                BIT(3)                                  /*!< I2S transmission underrun error bit */
    66. 

  66. #define SPI_STAT_CRCERR                 BIT(4)                                  /*!< SPI CRC error bit */
    67. 

  67. #define SPI_STAT_CONFERR                BIT(5)                                  /*!< SPI configuration error bit */
    68. 

  68. #define SPI_STAT_RXORERR                BIT(6)                                  /*!< SPI reception overrun error bit */
    69. 

  69. #define SPI_STAT_TRANS                  BIT(7)                                  /*!< transmitting on-going bit */
    70. 

  70. #define SPI_STAT_FERR                   BIT(8)                                  /*!< format error bit */
    71. 

  71. 

  72. /* SPI_DATA */
    73. 

  73. #define SPI_DATA_DATA                   BITS(0,15)                              /*!< data transfer register */
    74. 

  74. 

  75. /* SPI_CRCPOLY */
    76. 

  76. #define SPI_CRCPOLY_CPR                 BITS(0,15)                              /*!< CRC polynomial register */
    77. 

  77. 

  78. /* SPI_RCRC */
    79. 

  79. #define SPI_RCRC_RCR                    BITS(0,15)                              /*!< RX CRC register */
    80. 

  80. 

  81. /* SPI_TCRC */
    82. 

  82. #define SPI_TCRC_TCR                    BITS(0,15)                              /*!< RX CRC register */
    83. 

  83. 

  84. /* SPI_I2SCTL */
    85. 

  85. #define SPI_I2SCTL_CHLEN                BIT(0)                                  /*!< channel length */
    86. 

  86. #define SPI_I2SCTL_DTLEN                BITS(1,2)                               /*!< data length */
    87. 

  87. #define SPI_I2SCTL_CKPL                 BIT(3)                                  /*!< idle state clock polarity */
    88. 

  88. #define SPI_I2SCTL_I2SSTD               BITS(4,5)                               /*!< I2S standard selection */
    89. 

  89. #define SPI_I2SCTL_PCMSMOD              BIT(7)                                  /*!< PCM frame synchronization mode */
    90. 

  90. #define SPI_I2SCTL_I2SOPMOD             BITS(8,9)                               /*!< I2S operation mode */
    91. 

  91. #define SPI_I2SCTL_I2SEN                BIT(10)                                 /*!< I2S enable */
    92. 

  92. #define SPI_I2SCTL_I2SSEL               BIT(11)                                 /*!< I2S mode selection */
    93. 

  93. 

  94. /* SPI_I2SPSC */
    95. 

  95. #define SPI_I2SPSC_DIV                  BITS(0,7)                               /*!< dividing factor for the prescaler */
    96. 

  96. #define SPI_I2SPSC_OF                   BIT(8)                                  /*!< odd factor for the prescaler */
    97. 

  97. #define SPI_I2SPSC_MCKOEN               BIT(9)                                  /*!< I2S MCK output enable */
    98. 

  98. 

  99. /* SPI_QCTL(only for SPI0) */
    100. 

  100. #define SPI_QCTL_QMOD                   BIT(0)                                  /*!< quad-SPI mode enable */
    101. 

  101. #define SPI_QCTL_QRD                    BIT(1)                                  /*!< quad-SPI mode read select */
    102. 

  102. #define SPI_QCTL_IO23_DRV               BIT(2)                                  /*!< drive SPI_IO2 and SPI_IO3 enable */
    103. 

  103. 

  104. /* constants definitions */
    105. 

  105. /* SPI and I2S parameter struct definitions */
    106. 

  106. typedef struct
    107. 

  107. {   
    108. 

  108.     uint32_t device_mode;                                                       /*!< SPI master or slave */
    109. 

  109.     uint32_t trans_mode;                                                        /*!< SPI transtype */
    110. 

  110.     uint32_t frame_size;                                                        /*!< SPI frame size */
    111. 

  111.     uint32_t nss;                                                               /*!< SPI NSS control by handware or software */
    112. 

  112.     uint32_t endian;                                                            /*!< SPI big endian or little endian */
    113. 

  113.     uint32_t clock_polarity_phase;                                              /*!< SPI clock phase and polarity */
    114. 

  114.     uint32_t prescale;                                                          /*!< SPI prescale factor */
    115. 

  115. }spi_parameter_struct;
    116. 

  116. 

  117. /* SPI mode definitions */
    118. 

  118. #define SPI_MASTER                      (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)      /*!< SPI as master */
    119. 

  119. #define SPI_SLAVE                       ((uint32_t)0x00000000U)                 /*!< SPI as slave */
    120. 

  120. 

  121. /* SPI bidirectional transfer direction */
    122. 

  122. #define SPI_BIDIRECTIONAL_TRANSMIT      SPI_CTL0_BDOEN                          /*!< SPI work in transmit-only mode */
    123. 

  123. #define SPI_BIDIRECTIONAL_RECEIVE       ~SPI_CTL0_BDOEN                         /*!< SPI work in receive-only mode */
    124. 

  124. 

  125. /* SPI transmit type */
    126. 

  126. #define SPI_TRANSMODE_FULLDUPLEX        ((uint32_t)0x00000000U)                 /*!< SPI receive and send data at fullduplex communication */
    127. 

  127. #define SPI_TRANSMODE_RECEIVEONLY       SPI_CTL0_RO                             /*!< SPI only receive data */
    128. 

  128. #define SPI_TRANSMODE_BDRECEIVE         SPI_CTL0_BDEN                           /*!< bidirectional receive data */
    129. 

  129. #define SPI_TRANSMODE_BDTRANSMIT        (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)        /*!< bidirectional transmit data*/
    130. 

  130. 

  131. /* SPI frame size */
    132. 

  132. #define SPI_FRAMESIZE_16BIT             SPI_CTL0_FF16                           /*!< SPI frame size is 16 bits */
    133. 

  133. #define SPI_FRAMESIZE_8BIT              ((uint32_t)0x00000000U)                 /*!< SPI frame size is 8 bits */
    134. 

  134. 

  135. /* SPI NSS control mode */
    136. 

  136. #define SPI_NSS_SOFT                    SPI_CTL0_SWNSSEN                        /*!< SPI NSS control by sofrware */
    137. 

  137. #define SPI_NSS_HARD                    ((uint32_t)0x00000000U)                 /*!< SPI NSS control by hardware */
    138. 

  138. 

  139. /* SPI transmit way */
    140. 

  140. #define SPI_ENDIAN_MSB                  ((uint32_t)0x00000000U)                 /*!< SPI transmit way is big endian: transmit MSB first */
    141. 

  141. #define SPI_ENDIAN_LSB                  SPI_CTL0_LF                             /*!< SPI transmit way is little endian: transmit LSB first */
    142. 

  142. 

  143. /* SPI clock phase and polarity */
    144. 

  144. #define SPI_CK_PL_LOW_PH_1EDGE          ((uint32_t)0x00000000U)                 /*!< SPI clock polarity is low level and phase is first edge */
    145. 

  145. #define SPI_CK_PL_HIGH_PH_1EDGE         SPI_CTL0_CKPL                           /*!< SPI clock polarity is high level and phase is first edge */
    146. 

  146. #define SPI_CK_PL_LOW_PH_2EDGE          SPI_CTL0_CKPH                           /*!< SPI clock polarity is low level and phase is second edge */
    147. 

  147. #define SPI_CK_PL_HIGH_PH_2EDGE         (SPI_CTL0_CKPL | SPI_CTL0_CKPH)         /*!< SPI clock polarity is high level and phase is second edge */
    148. 

  148. 

  149. /* SPI clock prescale factor */
    150. 

  150. #define CTL0_PSC(regval)                (BITS(3,5) & ((uint32_t)(regval) << 3))
    151. 

  151. #define SPI_PSC_2                       CTL0_PSC(0)                             /*!< SPI clock prescale factor is 2 */
    152. 

  152. #define SPI_PSC_4                       CTL0_PSC(1)                             /*!< SPI clock prescale factor is 4 */
    153. 

  153. #define SPI_PSC_8                       CTL0_PSC(2)                             /*!< SPI clock prescale factor is 8 */
    154. 

  154. #define SPI_PSC_16                      CTL0_PSC(3)                             /*!< SPI clock prescale factor is 16 */
    155. 

  155. #define SPI_PSC_32                      CTL0_PSC(4)                             /*!< SPI clock prescale factor is 32 */
    156. 

  156. #define SPI_PSC_64                      CTL0_PSC(5)                             /*!< SPI clock prescale factor is 64 */
    157. 

  157. #define SPI_PSC_128                     CTL0_PSC(6)                             /*!< SPI clock prescale factor is 128 */
    158. 

  158. #define SPI_PSC_256                     CTL0_PSC(7)                             /*!< SPI clock prescale factor is 256 */
    159. 

  159. 

  160. /* I2S audio sample rate */
    161. 

  161. #define I2S_AUDIOSAMPLE_8K              ((uint32_t)8000U)                       /*!< I2S audio sample rate is 8KHz */
    162. 

  162. #define I2S_AUDIOSAMPLE_11K             ((uint32_t)11025U)                      /*!< I2S audio sample rate is 11KHz */
    163. 

  163. #define I2S_AUDIOSAMPLE_16K             ((uint32_t)16000U)                      /*!< I2S audio sample rate is 16KHz */
    164. 

  164. #define I2S_AUDIOSAMPLE_22K             ((uint32_t)22050U)                      /*!< I2S audio sample rate is 22KHz */
    165. 

  165. #define I2S_AUDIOSAMPLE_32K             ((uint32_t)32000U)                      /*!< I2S audio sample rate is 32KHz */
    166. 

  166. #define I2S_AUDIOSAMPLE_44K             ((uint32_t)44100U)                      /*!< I2S audio sample rate is 44KHz */
    167. 

  167. #define I2S_AUDIOSAMPLE_48K             ((uint32_t)48000U)                      /*!< I2S audio sample rate is 48KHz */
    168. 

  168. #define I2S_AUDIOSAMPLE_96K             ((uint32_t)96000U)                      /*!< I2S audio sample rate is 96KHz */
    169. 

  169. #define I2S_AUDIOSAMPLE_192K            ((uint32_t)192000U)                     /*!< I2S audio sample rate is 192KHz */
    170. 

  170. 

  171. /* I2S frame format */
    172. 

  172. #define I2SCTL_DTLEN(regval)            (BITS(1,2) & ((uint32_t)(regval) << 1))
    173. 

  173. #define I2S_FRAMEFORMAT_DT16B_CH16B     I2SCTL_DTLEN(0)                         /*!< I2S data length is 16 bit and channel length is 16 bit */
    174. 

  174. #define I2S_FRAMEFORMAT_DT16B_CH32B     (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 16 bit and channel length is 32 bit */
    175. 

  175. #define I2S_FRAMEFORMAT_DT24B_CH32B     (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 24 bit and channel length is 32 bit */
    176. 

  176. #define I2S_FRAMEFORMAT_DT32B_CH32B     (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 32 bit and channel length is 32 bit */
    177. 

  177. 

  178. /* I2S master clock output */
    179. 

  179. #define I2S_MCKOUT_DISABLE              ((uint32_t)0x00000000U)                 /*!< I2S master clock output disable */
    180. 

  180. #define I2S_MCKOUT_ENABLE               SPI_I2SPSC_MCKOEN                       /*!< I2S master clock output enable */
    181. 

  181. 

  182. /* I2S operation mode */
    183. 

  183. #define I2SCTL_I2SOPMOD(regval)         (BITS(8,9) & ((uint32_t)(regval) << 8))
    184. 

  184. #define I2S_MODE_SLAVETX                I2SCTL_I2SOPMOD(0)                      /*!< I2S slave transmit mode */
    185. 

  185. #define I2S_MODE_SLAVERX                I2SCTL_I2SOPMOD(1)                      /*!< I2S slave receive mode */
    186. 

  186. #define I2S_MODE_MASTERTX               I2SCTL_I2SOPMOD(2)                      /*!< I2S master transmit mode */
    187. 

  187. #define I2S_MODE_MASTERRX               I2SCTL_I2SOPMOD(3)                      /*!< I2S master receive mode */
    188. 

  188. 

  189. /* I2S standard */
    190. 

  190. #define I2SCTL_I2SSTD(regval)           (BITS(4,5) & ((uint32_t)(regval) << 4))
    191. 

  191. #define I2S_STD_PHILLIPS                I2SCTL_I2SSTD(0)                        /*!< I2S phillips standard */
    192. 

  192. #define I2S_STD_MSB                     I2SCTL_I2SSTD(1)                        /*!< I2S MSB standard */
    193. 

  193. #define I2S_STD_LSB                     I2SCTL_I2SSTD(2)                        /*!< I2S LSB standard */
    194. 

  194. #define I2S_STD_PCMSHORT                I2SCTL_I2SSTD(3)                        /*!< I2S PCM short standard */
    195. 

  195. #define I2S_STD_PCMLONG                 (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
    196. 

  196. 

  197. /* I2S clock polarity */
    198. 

  198. #define I2S_CKPL_LOW                    ((uint32_t)0x00000000U)                 /*!< I2S clock polarity low level */
    199. 

  199. #define I2S_CKPL_HIGH                   SPI_I2SCTL_CKPL                         /*!< I2S clock polarity high level */
    200. 

  200. 

  201. /* SPI DMA constants definitions */                                    
    202. 

  202. #define SPI_DMA_TRANSMIT                ((uint8_t)0x00U)                        /*!< SPI transmit data use DMA */
    203. 

  203. #define SPI_DMA_RECEIVE                 ((uint8_t)0x01U)                        /*!< SPI receive data use DMA */
    204. 

  204. 

  205. /* SPI CRC constants definitions */
    206. 

  206. #define SPI_CRC_TX                      ((uint8_t)0x00U)                        /*!< SPI transmit CRC value */
    207. 

  207. #define SPI_CRC_RX                      ((uint8_t)0x01U)                        /*!< SPI receive CRC value */
    208. 

  208. 

  209. /* SPI/I2S interrupt enable/disable constants definitions */
    210. 

  210. #define SPI_I2S_INT_TBE                 ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt */
    211. 

  211. #define SPI_I2S_INT_RBNE                ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt */
    212. 

  212. #define SPI_I2S_INT_ERR                 ((uint8_t)0x02U)                        /*!< error interrupt */
    213. 

  213. 

  214. /* SPI/I2S interrupt flag constants definitions */
    215. 

  215. #define SPI_I2S_INT_FLAG_TBE            ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt flag */
    216. 

  216. #define SPI_I2S_INT_FLAG_RBNE           ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt flag */
    217. 

  217. #define SPI_I2S_INT_FLAG_RXORERR        ((uint8_t)0x02U)                        /*!< overrun interrupt flag */
    218. 

  218. #define SPI_INT_FLAG_CONFERR            ((uint8_t)0x03U)                        /*!< config error interrupt flag */
    219. 

  219. #define SPI_INT_FLAG_CRCERR             ((uint8_t)0x04U)                        /*!< CRC error interrupt flag */
    220. 

  220. #define I2S_INT_FLAG_TXURERR            ((uint8_t)0x05U)                        /*!< underrun error interrupt flag */
    221. 

  221. #define SPI_I2S_INT_FLAG_FERR           ((uint8_t)0x06U)                        /*!< format error interrupt flag */
    222. 

  222. 

  223. /* SPI/I2S flag definitions */                                                  
    224. 

  224. #define SPI_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
    225. 

  225. #define SPI_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
    226. 

  226. #define SPI_FLAG_CRCERR                 SPI_STAT_CRCERR                         /*!< CRC error flag */
    227. 

  227. #define SPI_FLAG_CONFERR                SPI_STAT_CONFERR                        /*!< mode config error flag */
    228. 

  228. #define SPI_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< receive overrun error flag */
    229. 

  229. #define SPI_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
    230. 

  230. #define SPI_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
    231. 

  231. #define I2S_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
    232. 

  232. #define I2S_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
    233. 

  233. #define I2S_FLAG_CH                     SPI_STAT_I2SCH                          /*!< channel side flag */
    234. 

  234. #define I2S_FLAG_TXURERR                SPI_STAT_TXURERR                        /*!< underrun error flag */
    235. 

  235. #define I2S_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< overrun error flag */
    236. 

  236. #define I2S_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
    237. 

  237. #define I2S_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
    238. 

  238. 

  239. /* function declarations */
    240. 

  240. /* reset SPI and I2S */
    241. 

  241. void spi_i2s_deinit(uint32_t spi_periph);
    242. 

  242. /* initialize SPI parameter */
    243. 

  243. void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
    244. 

  244. /* enable SPI */
    245. 

  245. void spi_enable(uint32_t spi_periph);
    246. 

  246. /* disable SPI */
    247. 

  247. void spi_disable(uint32_t spi_periph);
    248. 

  248. 

  249. /* initialize I2S parameter */
    250. 

  250. void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
    251. 

  251. /* configure I2S prescaler */
    252. 

  252. void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
    253. 

  253. /* enable I2S */
    254. 

  254. void i2s_enable(uint32_t spi_periph);
    255. 

  255. /* disable I2S */
    256. 

  256. void i2s_disable(uint32_t spi_periph);
    257. 

  257. 

  258. /* enable SPI NSS output */
    259. 

  259. void spi_nss_output_enable(uint32_t spi_periph);
    260. 

  260. /* disable SPI NSS output */
    261. 

  261. void spi_nss_output_disable(uint32_t spi_periph);
    262. 

  262. /* SPI NSS pin high level in software mode */
    263. 

  263. void spi_nss_internal_high(uint32_t spi_periph);
    264. 

  264. /* SPI NSS pin low level in software mode */
    265. 

  265. void spi_nss_internal_low(uint32_t spi_periph);
    266. 

  266. 

  267. /* enable SPI DMA */
    268. 

  268. void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
    269. 

  269. /* disable SPI DMA */
    270. 

  270. void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
    271. 

  271. 

  272. /* configure SPI/I2S data frame format */
    273. 

  273. void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
    274. 

  274. /* SPI transmit data */
    275. 

  275. void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
    276. 

  276. /* SPI receive data */
    277. 

  277. uint16_t spi_i2s_data_receive(uint32_t spi_periph);
    278. 

  278. /* configure SPI bidirectional transfer direction */
    279. 

  279. void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
    280. 

  280. 

  281. /* enable SPI and I2S interrupt */
    282. 

  282. void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
    283. 

  283. /* disable SPI and I2S interrupt */
    284. 

  284. void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
    285. 

  285. /* get SPI and I2S interrupt status */
    286. 

  286. FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
    287. 

  287. /* get SPI and I2S flag status */
    288. 

  288. FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
    289. 

  289. /* clear SPI CRC error flag status */
    290. 

  290. void spi_crc_error_clear(uint32_t spi_periph);
    291. 

  291. 

  292. /* set SPI CRC polynomial */
    293. 

  293. void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
    294. 

  294. /* get SPI CRC polynomial */
    295. 

  295. uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
    296. 

  296. /* turn on SPI CRC function */
    297. 

  297. void spi_crc_on(uint32_t spi_periph);
    298. 

  298. /* turn off SPI CRC function */
    299. 

  299. void spi_crc_off(uint32_t spi_periph);
    300. 

  300. /* SPI next data is CRC value */
    301. 

  301. void spi_crc_next(uint32_t spi_periph);
    302. 

  302. /* get SPI CRC send value or receive value */
    303. 

  303. uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
    304. 

  304. 

  305. /* enable SPI TI mode */
    306. 

  306. void spi_ti_mode_enable(uint32_t spi_periph);
    307. 

  307. /* disable SPI TI mode */
    308. 

  308. void spi_ti_mode_disable(uint32_t spi_periph);
    309. 

  309. 

  310. /* enable SPI NSS pulse mode */
    311. 

  311. void spi_nssp_mode_enable(uint32_t spi_periph);
    312. 

  312. /* disable SPI NSS pulse mode */
    313. 

  313. void spi_nssp_mode_disable(uint32_t spi_periph);
    314. 

  314. 

  315. /* enable quad wire SPI */
    316. 

  316. void qspi_enable(uint32_t spi_periph);
    317. 

  317. /* disable quad wire SPI */
    318. 

  318. void qspi_disable(uint32_t spi_periph);
    319. 

  319. /* enable quad wire SPI write */
    320. 

  320. void qspi_write_enable(uint32_t spi_periph);
    321. 

  321. /* enable quad wire SPI read */
    322. 

  322. void qspi_read_enable(uint32_t spi_periph);
    323. 

  323. /* enable quad wire SPI_IO2 and SPI_IO3 pin output */
    324. 

  324. void qspi_io23_output_enable(uint32_t spi_periph);
    325. 

  325. /* disable quad wire SPI_IO2 and SPI_IO3 pin output */
    326. 

  326. void qspi_io23_output_disable(uint32_t spi_periph);
    327. 

  327. 

  328. #endif /* GD32F30X_SPI_H */
    329.