gd32f4xx_adc.h 36 KB

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  1. /*!
  2. \file gd32f4xx_adc.h
  3. \brief definitions for the ADC
  4. */
  5. /*
  6. Copyright (C) 2016 GigaDevice
  7. 2016-08-15, V1.0.0, firmware for GD32F4xx
  8. */
  9. #ifndef GD32F4XX_ADC_H
  10. #define GD32F4XX_ADC_H
  11. #include "gd32f4xx.h"
  12. /* ADC definitions */
  13. #define ADC0 ADC_BASE
  14. #define ADC1 (ADC_BASE + 0x100U)
  15. #define ADC2 (ADC_BASE + 0x200U)
  16. /* registers definitions */
  17. #define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
  18. #define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
  19. #define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
  20. #define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
  21. #define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
  22. #define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
  23. #define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
  24. #define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
  25. #define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
  26. #define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
  27. #define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
  28. #define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
  29. #define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
  30. #define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
  31. #define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
  32. #define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
  33. #define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
  34. #define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
  35. #define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
  36. #define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
  37. #define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */
  38. #define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */
  39. #define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */
  40. #define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization regular data register */
  41. /* bits definitions */
  42. /* ADC_STAT */
  43. #define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
  44. #define ADC_STAT_EOC BIT(1) /*!< end of conversion */
  45. #define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
  46. #define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
  47. #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
  48. #define ADC_STAT_ROVF BIT(5) /*!< regular data register overflow */
  49. /* ADC_CTL0 */
  50. #define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
  51. #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
  52. #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
  53. #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
  54. #define ADC_CTL0_SM BIT(8) /*!< scan mode */
  55. #define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
  56. #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
  57. #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
  58. #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
  59. #define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
  60. #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
  61. #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
  62. #define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
  63. #define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */
  64. /* ADC_CTL1 */
  65. #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
  66. #define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
  67. #define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
  68. #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
  69. #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
  70. #define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */
  71. #define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */
  72. #define ADC_CTL1_DAL BIT(11) /*!< data alignment */
  73. #define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted group */
  74. #define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */
  75. #define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */
  76. #define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for regular group */
  77. #define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for regular channels */
  78. #define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of regular channels */
  79. /* ADC_SAMPTx x=0..1 */
  80. #define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
  81. /* ADC_IOFFx x=0..3 */
  82. #define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
  83. /* ADC_WDHT */
  84. #define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
  85. /* ADC_WDLT */
  86. #define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
  87. /* ADC_RSQx */
  88. #define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */
  89. #define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
  90. /* ADC_ISQ */
  91. #define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */
  92. #define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
  93. /* ADC_IDATAx x=0..3*/
  94. #define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */
  95. /* ADC_RDATA */
  96. #define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
  97. /* ADC_OVSAMPCTL */
  98. #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
  99. #define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
  100. #define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
  101. #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
  102. /* ADC_SSTAT */
  103. #define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */
  104. #define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */
  105. #define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */
  106. #define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */
  107. #define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */
  108. #define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */
  109. #define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */
  110. #define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */
  111. #define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */
  112. #define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */
  113. #define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */
  114. #define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */
  115. #define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */
  116. #define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */
  117. #define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */
  118. #define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */
  119. #define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */
  120. #define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */
  121. /* ADC_SYNCCTL */
  122. #define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */
  123. #define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */
  124. #define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */
  125. #define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */
  126. #define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */
  127. #define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */
  128. #define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */
  129. /* ADC_SYNCDATA */
  130. #define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< regular data1 in ADC synchronization mode */
  131. #define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */
  132. /* constants definitions */
  133. /* ADC channel group definitions */
  134. #define ADC_REGULAR_CHANNEL ((uint8_t)0x00U) /*!< adc regular channel group */
  135. #define ADC_INSERTED_CHANNEL ((uint8_t)0x01U) /*!< adc inserted channel group */
  136. #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< both regular and inserted channel group */
  137. /* external trigger mode for regular and inserted channel */
  138. #define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */
  139. #define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */
  140. #define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */
  141. #define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */
  142. /* ADC inserted channel definitions */
  143. #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
  144. #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
  145. #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
  146. #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
  147. /* ADC special function definitions */
  148. #define ADC_SCAN_MODE ((uint8_t)0x00U) /*!< scan mode */
  149. #define ADC_INSERTED_CHANNEL_AUTO ((uint8_t)0x01U) /*!< inserted channel group convert automatically */
  150. #define ADC_VBAT_CHANNEL_SWITCH ((uint8_t)0x02U) /*!< VBAT channel */
  151. #define ADC_TEMP_VREF_CHANNEL_SWITCH ((uint8_t)0x03U) /*!< Vref and Vtemp channel */
  152. #define ADC_CONTINUOUS_MODE ((uint8_t)0x04U) /*!< continuous mode */
  153. /* ADC channel definitions */
  154. #define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
  155. #define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
  156. #define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
  157. #define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
  158. #define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
  159. #define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
  160. #define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
  161. #define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
  162. #define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
  163. #define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
  164. #define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
  165. #define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
  166. #define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
  167. #define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
  168. #define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
  169. #define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
  170. #define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
  171. #define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
  172. #define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */
  173. /* ADC channel sample time */
  174. #define ADC_SAMPLETIME_3 ((uint8_t)0x00U) /*!< 3 sampling cycles */
  175. #define ADC_SAMPLETIME_15 ((uint8_t)0x01U) /*!< 15 sampling cycles */
  176. #define ADC_SAMPLETIME_28 ((uint8_t)0x02U) /*!< 28 sampling cycles */
  177. #define ADC_SAMPLETIME_56 ((uint8_t)0x03U) /*!< 56 sampling cycles */
  178. #define ADC_SAMPLETIME_84 ((uint8_t)0x04U) /*!< 84 sampling cycles */
  179. #define ADC_SAMPLETIME_112 ((uint8_t)0x05U) /*!< 112 sampling cycles */
  180. #define ADC_SAMPLETIME_144 ((uint8_t)0x06U) /*!< 144 sampling cycles */
  181. #define ADC_SAMPLETIME_480 ((uint8_t)0x07U) /*!< 480 sampling cycles */
  182. /* ADC data alignment */
  183. #define ADC_DATAALIGN_RIGHT ((uint8_t)0x00U) /*!< LSB alignment */
  184. #define ADC_DATAALIGN_LEFT ((uint8_t)0x01U) /*!< MSB alignment */
  185. /* ADC status flag */
  186. #define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
  187. #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
  188. #define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
  189. #define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
  190. #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
  191. #define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */
  192. /* ADC interrupt flag */
  193. #define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
  194. #define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
  195. #define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
  196. #define ADC_INT_ROVF ADC_STAT_ROVF /*!< regular data register overflow */
  197. /* ADC resolution definitions */
  198. #define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
  199. #define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
  200. #define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
  201. #define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
  202. #define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
  203. /* ADC external trigger select for regular channel */
  204. #define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
  205. #define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */
  206. #define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */
  207. #define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
  208. #define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */
  209. #define ADC_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */
  210. #define ADC_EXTTRIG_REGULAR_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */
  211. #define ADC_EXTTRIG_REGULAR_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */
  212. #define ADC_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */
  213. #define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */
  214. #define ADC_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */
  215. #define ADC_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */
  216. #define ADC_EXTTRIG_REGULAR_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */
  217. #define ADC_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */
  218. #define ADC_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */
  219. #define ADC_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */
  220. #define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */
  221. /* ADC external trigger select for inserted channel */
  222. #define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
  223. #define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */
  224. #define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */
  225. #define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */
  226. #define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */
  227. #define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */
  228. #define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */
  229. #define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */
  230. #define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */
  231. #define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */
  232. #define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */
  233. #define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */
  234. #define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */
  235. #define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */
  236. #define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */
  237. #define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */
  238. #define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */
  239. /* ADC oversampling mode */
  240. #define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */
  241. #define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */
  242. /* ADC oversampling shift */
  243. #define OVCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
  244. #define ADC_OVERSAMPLING_SHIFT_NONE OVCTL_OVSS(0) /*!< no oversampling shift */
  245. #define ADC_OVERSAMPLING_SHIFT_1B OVCTL_OVSS(1) /*!< 1-bit oversampling shift */
  246. #define ADC_OVERSAMPLING_SHIFT_2B OVCTL_OVSS(2) /*!< 2-bit oversampling shift */
  247. #define ADC_OVERSAMPLING_SHIFT_3B OVCTL_OVSS(3) /*!< 3-bit oversampling shift */
  248. #define ADC_OVERSAMPLING_SHIFT_4B OVCTL_OVSS(4) /*!< 4-bit oversampling shift */
  249. #define ADC_OVERSAMPLING_SHIFT_5B OVCTL_OVSS(5) /*!< 5-bit oversampling shift */
  250. #define ADC_OVERSAMPLING_SHIFT_6B OVCTL_OVSS(6) /*!< 6-bit oversampling shift */
  251. #define ADC_OVERSAMPLING_SHIFT_7B OVCTL_OVSS(7) /*!< 7-bit oversampling shift */
  252. #define ADC_OVERSAMPLING_SHIFT_8B OVCTL_OVSS(8) /*!< 8-bit oversampling shift */
  253. /* ADC oversampling ratio */
  254. #define OVCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
  255. #define ADC_OVERSAMPLING_RATIO_MUL2 OVCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
  256. #define ADC_OVERSAMPLING_RATIO_MUL4 OVCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
  257. #define ADC_OVERSAMPLING_RATIO_MUL8 OVCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
  258. #define ADC_OVERSAMPLING_RATIO_MUL16 OVCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
  259. #define ADC_OVERSAMPLING_RATIO_MUL32 OVCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
  260. #define ADC_OVERSAMPLING_RATIO_MUL64 OVCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
  261. #define ADC_OVERSAMPLING_RATIO_MUL128 OVCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
  262. #define ADC_OVERSAMPLING_RATIO_MUL256 OVCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
  263. /* configure the ADC clock for all the ADCs */
  264. #define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
  265. #define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */
  266. #define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */
  267. #define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */
  268. #define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */
  269. #define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */
  270. #define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */
  271. #define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */
  272. #define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */
  273. /* ADC synchronization mode */
  274. #define ADC_SYNC_MODE_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC synchronization mode disabled.All the ADCs work independently */
  275. #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL ((uint32_t)0x00000001U) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */
  276. #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION ((uint32_t)0x00000002U) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */
  277. #define ADC_DAUL_INSERTED_PARALLEL ((uint32_t)0x00000005U) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */
  278. #define ADC_DAUL_REGULAL_PARALLEL ((uint32_t)0x00000006U) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */
  279. #define ADC_DAUL_REGULAL_FOLLOW_UP ((uint32_t)0x00000007U) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */
  280. #define ADC_DAUL_INSERTED_TRRIGGER_ROTATION ((uint32_t)0x00000009U) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */
  281. #define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL ((uint32_t)0x00000011U) /*!< all ADCs work in combined regular parallel & inserted parallel mode */
  282. #define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION ((uint32_t)0x00000012U) /*!< all ADCs work in combined regular parallel & trigger rotation mode */
  283. #define ADC_ALL_INSERTED_PARALLEL ((uint32_t)0x00000015U) /*!< all ADCs work in inserted parallel mode */
  284. #define ADC_ALL_REGULAL_PARALLEL ((uint32_t)0x00000016U) /*!< all ADCs work in regular parallel mode */
  285. #define ADC_ALL_REGULAL_FOLLOW_UP ((uint32_t)0x00000017U) /*!< all ADCs work in follow-up mode */
  286. #define ADC_ALL_INSERTED_TRRIGGER_ROTATION ((uint32_t)0x00000019U) /*!< all ADCs work in trigger rotation mode */
  287. /* ADC synchronization delay */
  288. #define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */
  289. #define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */
  290. #define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */
  291. #define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */
  292. #define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */
  293. #define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */
  294. #define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */
  295. #define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */
  296. #define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */
  297. #define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */
  298. #define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */
  299. #define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */
  300. #define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */
  301. #define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */
  302. #define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */
  303. #define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */
  304. /* ADC synchronization DMA mode selection */
  305. #define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */
  306. #define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */
  307. #define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */
  308. /* end of conversion mode */
  309. #define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of regular conversions, the EOC bit is set */
  310. #define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */
  311. /* function declarations */
  312. /* ADC reset */
  313. void adc_deinit(void);
  314. /* enable ADC interface */
  315. void adc_enable(uint32_t adc_periph);
  316. /* disable ADC interface */
  317. void adc_disable(uint32_t adc_periph);
  318. /* ADC data alignment config */
  319. void adc_data_alignment_config(uint32_t adc_periph , uint8_t data_alignment);
  320. /* ADC resolution config */
  321. void adc_resolution_config(uint32_t adc_periph , uint32_t resolution);
  322. /* ADC calibration and reset calibration */
  323. void adc_calibration_enable(uint32_t adc_periph);
  324. /* ADC discontinuous mode config */
  325. void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length);
  326. /* config end of conversion mode */
  327. void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection);
  328. /* ADC special function enable or disable */
  329. void adc_special_function_config(uint32_t adc_periph , uint8_t function , ControlStatus newvalue);
  330. /* configure the ADC clock for all the ADCs */
  331. void adc_clock_config(uint32_t prescaler);
  332. /* ADC channel */
  333. /* configure the ADC clock for all the ADCs */
  334. void adc_channel_16_to_18(uint8_t function,ControlStatus newvalue);
  335. /* config the length of regular channel group or inserted channel group */
  336. void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length);
  337. /* ADC trigger */
  338. /* ADC external trigger enable */
  339. void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode);
  340. /* ADC external trigger source config */
  341. void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source);
  342. /* ADC software trigger enable */
  343. void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group);
  344. /* ADC flag and interrupt */
  345. /* get the ADC flag bits */
  346. FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag);
  347. /* clear the ADC flag bits */
  348. void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
  349. /* get the ADC interrupt bits */
  350. FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt);
  351. /* clear the ADC flag */
  352. void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt);
  353. /* ADC interrupt enable */
  354. void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt);
  355. /* ADC interrupt disable */
  356. void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt);
  357. /* ADC analog watchdog */
  358. /* ADC analog watchdog single channel disable */
  359. void adc_watchdog_single_channel_disable(uint32_t adc_periph );
  360. /* ADC analog watchdog single channel enable */
  361. void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel);
  362. /* adc analog watchdog group channel config */
  363. void adc_watchdog_enable(uint32_t adc_periph , uint8_t adc_channel_group);
  364. /* ADC analog watchdog disable */
  365. void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group);
  366. /* ADC analog watchdog threshold config */
  367. void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
  368. /* regular channel */
  369. /* ADC regular channel config */
  370. void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
  371. /* ADC regular group data register read */
  372. uint16_t adc_regular_data_read(uint32_t adc_periph);
  373. /* inserted channel */
  374. /* ADC inserted channel config */
  375. void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint8_t sample_time);
  376. /* ADC inserted channel offset config */
  377. void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
  378. /* ADC inserted group data register read */
  379. uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
  380. /* ADC DMA */
  381. /* DMA request enable */
  382. void adc_dma_mode_enable(uint32_t adc_periph);
  383. /* DMA request disable */
  384. void adc_dma_mode_disable(uint32_t adc_periph);
  385. /* when DMA=1, the DMA engine issues a request at end of each regular conversion */
  386. void adc_dma_request_after_last_enable(uint32_t adc_periph);
  387. /* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */
  388. void adc_dma_request_after_last_disable(uint32_t adc_periph);
  389. /* ADC oversample */
  390. /* ADC oversample mode config */
  391. void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio);
  392. /* ADC oversample mode enable */
  393. void adc_oversample_mode_enable(uint32_t adc_periph );
  394. /* ADC oversample mode disable */
  395. void adc_oversample_mode_disable(uint32_t adc_periph );
  396. /* ADC synchronization */
  397. /* configure the ADC sync mode */
  398. void adc_sync_mode_config(uint32_t sync_mode);
  399. /* configure the delay between 2 sampling phases in ADC sync modes */
  400. void adc_sync_delay_config(uint32_t sample_delay);
  401. /* configure ADC sync DMA mode selection */
  402. void adc_sync_dma_config(uint32_t dma_mode );
  403. /* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */
  404. void adc_sync_dma_request_after_last_enable(void);
  405. /* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */
  406. void adc_sync_dma_request_after_last_disable(void);
  407. /* ADC sync regular data register read */
  408. uint32_t adc_sync_regular_data_read(void);
  409. #endif /* GD32F4XX_ADC_H */