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GD32F4xx_standard_peripheral
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gd32f4xx_dac.h

gd32f4xx_dac.h 13 KB
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  1. /*!
    2. 

  2.     \file  gd32f4xx_dac.h
    3. 

  3.     \brief definitions for the DAC
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2016 GigaDevice
    8. 

  8. 

  9.     2016-08-15, V1.0.0, firmware for GD32F4xx
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F4XX_DAC_H
    13. 

  13. #define GD32F4XX_DAC_H
    14. 

  14. 

  15. #include "gd32f4xx.h"
    16. 

  16. 

  17. /* DACx(x=0,1) definitions */
    18. 

  18. #define DAC                     DAC_BASE
    19. 

  19. #define DAC0                    0U
    20. 

  20. #define DAC1                    1U
    21. 

  21. 

  22. /* registers definitions */
    23. 

  23. #define DAC_CTL                 REG32(DAC + 0x00U)   /*!< DAC control register */
    24. 

  24. #define DAC_SWT                 REG32(DAC + 0x04U)   /*!< DAC software trigger register */
    25. 

  25. #define DAC0_R12DH              REG32(DAC + 0x08U)   /*!< DAC0 12-bit right-aligned data holding register */
    26. 

  26. #define DAC0_L12DH              REG32(DAC + 0x0CU)   /*!< DAC0 12-bit left-aligned data holding register */
    27. 

  27. #define DAC0_R8DH               REG32(DAC + 0x10U)   /*!< DAC0 8-bit right-aligned data holding register */
    28. 

  28. #define DAC1_R12DH              REG32(DAC + 0x14U)   /*!< DAC1 12-bit right-aligned data holding register */
    29. 

  29. #define DAC1_L12DH              REG32(DAC + 0x18U)   /*!< DAC1 12-bit left-aligned data holding register */
    30. 

  30. #define DAC1_R8DH               REG32(DAC + 0x1CU)   /*!< DAC1 8-bit right-aligned data holding register */
    31. 

  31. #define DACC_R12DH              REG32(DAC + 0x20U)   /*!< DAC concurrent mode 12-bit right-aligned data holding register */
    32. 

  32. #define DACC_L12DH              REG32(DAC + 0x24U)   /*!< DAC concurrent mode 12-bit left-aligned data holding register */
    33. 

  33. #define DACC_R8DH               REG32(DAC + 0x28U)   /*!< DAC concurrent mode 8-bit right-aligned data holding register */
    34. 

  34. #define DAC0_DO                 REG32(DAC + 0x2CU)   /*!< DAC0 data output register */
    35. 

  35. #define DAC1_DO                 REG32(DAC + 0x30U)   /*!< DAC1 data output register */
    36. 

  36. #define DAC_STAT                REG32(DAC + 0x34U)   /*!< DAC status register */
    37. 

  37. 

  38. /* bits definitions */
    39. 

  39. /* DAC_CLT */
    40. 

  40. #define DAC_CTL_DEN0            BIT(0)               /*!< DAC0 enable/disable bit */
    41. 

  41. #define DAC_CTL_DBOFF0          BIT(1)               /*!< DAC0 output buffer turn on/turn off bit */
    42. 

  42. #define DAC_CTL_DTEN0           BIT(2)               /*!< DAC0 trigger enable/disable bit */
    43. 

  43. #define DAC_CTL_DTSEL0          BITS(3,5)            /*!< DAC0 trigger source selection enable/disable bits */
    44. 

  44. #define DAC_CTL_DWM0            BITS(6,7)            /*!< DAC0 noise wave mode */
    45. 

  45. #define DAC_CTL_DWBW0           BITS(8,11)           /*!< DAC0 noise wave bit width */
    46. 

  46. #define DAC_CTL_DDMAEN0         BIT(12)              /*!< DAC0 DMA enable/disanle bit */
    47. 

  47. #define DAC_CTL_DDUDRIE0        BIT(13)              /*!< DAC0 DMA underrun interrupt enable/disable bit */
    48. 

  48. #define DAC_CTL_DEN1            BIT(16)              /*!< DAC1 enable/disable bit */ 
    49. 

  49. #define DAC_CTL_DBOFF1          BIT(17)              /*!< DAC1 output buffer turn on/turn off bit */
    50. 

  50. #define DAC_CTL_DTEN1           BIT(18)              /*!< DAC1 trigger enable/disable bit */
    51. 

  51. #define DAC_CTL_DTSEL1          BITS(19,21)          /*!< DAC1 trigger source selection enable/disable bits */
    52. 

  52. #define DAC_CTL_DWM1            BITS(22,23)          /*!< DAC1 noise wave mode */
    53. 

  53. #define DAC_CTL_DWBW1           BITS(24,27)          /*!< DAC1 noise wave bit width */
    54. 

  54. #define DAC_CTL_DDMAEN1         BIT(28)              /*!< DAC1 DMA enable/disanle bit */
    55. 

  55. #define DAC_CTL_DDUDRIE1        BIT(29)              /*!< DAC1 DMA underrun interrupt enable/disable bit */
    56. 

  56. 

  57. /* DAC_SWT */
    58. 

  58. #define DAC_SWT_SWTR0           BIT(0)               /*!< DAC0 software trigger bit, cleared by hardware */
    59. 

  59. #define DAC_SWT_SWTR1           BIT(1)               /*!< DAC1 software trigger bit, cleared by hardware */
    60. 

  60. 

  61. /* DAC0_R12DH */
    62. 

  62. #define DAC0_R12DH_DAC0_DH      BITS(0,11)           /*!< DAC0 12-bit right-aligned data bits */
    63. 

  63. 

  64. /* DAC0_L12DH */
    65. 

  65. #define DAC0_L12DH_DAC0_DH      BITS(4,15)           /*!< DAC0 12-bit left-aligned data bits */
    66. 

  66. 

  67. /* DAC0_R8DH */
    68. 

  68. #define DAC0_R8DH_DAC0_DH       BITS(0,7)            /*!< DAC0 8-bit right-aligned data bits */
    69. 

  69. 

  70. /* DAC1_R12DH */
    71. 

  71. #define DAC1_R12DH_DAC1_DH      BITS(0,11)           /*!< DAC1 12-bit right-aligned data bits */
    72. 

  72. 

  73. /* DAC1_L12DH */
    74. 

  74. #define DAC1_L12DH_DAC1_DH      BITS(4,15)           /*!< DAC1 12-bit left-aligned data bits */
    75. 

  75. 

  76. /* DAC1_R8DH */
    77. 

  77. #define DAC1_R8DH_DAC1_DH       BITS(0,7)            /*!< DAC1 8-bit right-aligned data bits */
    78. 

  78. 

  79. /* DACC_R12DH */
    80. 

  80. #define DACC_R12DH_DAC0_DH      BITS(0,11)           /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
    81. 

  81. #define DACC_R12DH_DAC1_DH      BITS(16,27)          /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
    82. 

  82. 

  83. /* DACC_L12DH */
    84. 

  84. #define DACC_L12DH_DAC0_DH      BITS(4,15)           /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
    85. 

  85. #define DACC_L12DH_DAC1_DH      BITS(20,31)          /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
    86. 

  86. 

  87. /* DACC_R8DH */
    88. 

  88. #define DACC_R8DH_DAC0_DH       BITS(0,7)            /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
    89. 

  89. #define DACC_R8DH_DAC1_DH       BITS(16,23)          /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
    90. 

  90. 

  91. /* DAC0_DO */
    92. 

  92. #define DAC0_DO_DAC0_DO         BITS(0,11)           /*!< DAC0 12-bit output data bits */
    93. 

  93. 

  94. /* DAC1_DO */
    95. 

  95. #define DAC1_DO_DAC1_DO         BITS(0,11)           /*!< DAC1 12-bit output data bits */
    96. 

  96. 

  97. /* DAC_STAT */
    98. 

  98. #define DAC_STAT_DDUDR0         BIT(13)              /*!< DAC0 DMA underrun flag */
    99. 

  99. #define DAC_STAT_DDUDR1         BIT(29)              /*!< DAC1 DMA underrun flag */
    100. 

  100. 

  101. /* constants definitions */
    102. 

  102. /* DAC trigger source */
    103. 

  103. #define CTL_DTSEL(regval)       (BITS(3,5) & ((uint32_t)(regval) << 3))
    104. 

  104. #define DAC_TRIGGER_T5_TRGO     CTL_DTSEL(0)         /*!< TIMER5 TRGO */
    105. 

  105. #define DAC_TRIGGER_T7_TRGO     CTL_DTSEL(1)         /*!< TIMER7 TRGO */
    106. 

  106. #define DAC_TRIGGER_T6_TRGO     CTL_DTSEL(2)         /*!< TIMER6 TRGO */
    107. 

  107. #define DAC_TRIGGER_T4_TRGO     CTL_DTSEL(3)         /*!< TIMER4 TRGO */
    108. 

  108. #define DAC_TRIGGER_T1_TRGO     CTL_DTSEL(4)         /*!< TIMER1 TRGO */
    109. 

  109. #define DAC_TRIGGER_T3_TRGO     CTL_DTSEL(5)         /*!< TIMER3 TRGO */
    110. 

  110. #define DAC_TRIGGER_EXTI_9      CTL_DTSEL(6)         /*!< EXTI interrupt line9 event */
    111. 

  111. #define DAC_TRIGGER_SOFTWARE    CTL_DTSEL(7)         /*!< software trigger */
    112. 

  112. 

  113. /* DAC noise wave mode */
    114. 

  114. #define CTL_DWM(regval)         (BITS(6,7) & ((uint32_t)(regval) << 6))
    115. 

  115. #define DAC_WAVE_DISABLE        CTL_DWM(0)           /*!< wave disable */
    116. 

  116. #define DAC_WAVE_MODE_LFSR      CTL_DWM(1)           /*!< LFSR noise mode */
    117. 

  117. #define DAC_WAVE_MODE_TRIANGLE  CTL_DWM(2)           /*!< triangle noise mode */
    118. 

  118. 

  119. /* DAC noise wave bit width */
    120. 

  120. #define DWBW(regval)            (BITS(8,11) & ((uint32_t)(regval) << 8))
    121. 

  121. #define DAC_WAVE_BIT_WIDTH_1    DWBW(0)              /*!< bit width of the wave signal is 1 */
    122. 

  122. #define DAC_WAVE_BIT_WIDTH_2    DWBW(1)              /*!< bit width of the wave signal is 2 */
    123. 

  123. #define DAC_WAVE_BIT_WIDTH_3    DWBW(2)              /*!< bit width of the wave signal is 3 */
    124. 

  124. #define DAC_WAVE_BIT_WIDTH_4    DWBW(3)              /*!< bit width of the wave signal is 4 */
    125. 

  125. #define DAC_WAVE_BIT_WIDTH_5    DWBW(4)              /*!< bit width of the wave signal is 5 */
    126. 

  126. #define DAC_WAVE_BIT_WIDTH_6    DWBW(5)              /*!< bit width of the wave signal is 6 */
    127. 

  127. #define DAC_WAVE_BIT_WIDTH_7    DWBW(6)              /*!< bit width of the wave signal is 7 */
    128. 

  128. #define DAC_WAVE_BIT_WIDTH_8    DWBW(7)              /*!< bit width of the wave signal is 8 */
    129. 

  129. #define DAC_WAVE_BIT_WIDTH_9    DWBW(8)              /*!< bit width of the wave signal is 9 */
    130. 

  130. #define DAC_WAVE_BIT_WIDTH_10   DWBW(9)              /*!< bit width of the wave signal is 10 */
    131. 

  131. #define DAC_WAVE_BIT_WIDTH_11   DWBW(10)             /*!< bit width of the wave signal is 11 */
    132. 

  132. #define DAC_WAVE_BIT_WIDTH_12   DWBW(11)             /*!< bit width of the wave signal is 12 */
    133. 

  133. 

  134. /* unmask LFSR bits in DAC LFSR noise mode */
    135. 

  135. #define DAC_LFSR_BIT0           DAC_WAVE_BIT_WIDTH_1  /*!< unmask the LFSR bit0 */
    136. 

  136. #define DAC_LFSR_BITS1_0        DAC_WAVE_BIT_WIDTH_2  /*!< unmask the LFSR bits[1:0] */
    137. 

  137. #define DAC_LFSR_BITS2_0        DAC_WAVE_BIT_WIDTH_3  /*!< unmask the LFSR bits[2:0] */
    138. 

  138. #define DAC_LFSR_BITS3_0        DAC_WAVE_BIT_WIDTH_4  /*!< unmask the LFSR bits[3:0] */
    139. 

  139. #define DAC_LFSR_BITS4_0        DAC_WAVE_BIT_WIDTH_5  /*!< unmask the LFSR bits[4:0] */
    140. 

  140. #define DAC_LFSR_BITS5_0        DAC_WAVE_BIT_WIDTH_6  /*!< unmask the LFSR bits[5:0] */
    141. 

  141. #define DAC_LFSR_BITS6_0        DAC_WAVE_BIT_WIDTH_7  /*!< unmask the LFSR bits[6:0] */
    142. 

  142. #define DAC_LFSR_BITS7_0        DAC_WAVE_BIT_WIDTH_8  /*!< unmask the LFSR bits[7:0] */
    143. 

  143. #define DAC_LFSR_BITS8_0        DAC_WAVE_BIT_WIDTH_9  /*!< unmask the LFSR bits[8:0] */
    144. 

  144. #define DAC_LFSR_BITS9_0        DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
    145. 

  145. #define DAC_LFSR_BITS10_0       DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
    146. 

  146. #define DAC_LFSR_BITS11_0       DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
    147. 

  147. 

  148. /* triangle amplitude in DAC triangle noise mode */
    149. 

  149. #define DAC_TRIANGLE_AMPLITUDE_1    DAC_WAVE_BIT_WIDTH_1  /*!< triangle amplitude is 1 */
    150. 

  150. #define DAC_TRIANGLE_AMPLITUDE_3    DAC_WAVE_BIT_WIDTH_2  /*!< triangle amplitude is 3 */
    151. 

  151. #define DAC_TRIANGLE_AMPLITUDE_7    DAC_WAVE_BIT_WIDTH_3  /*!< triangle amplitude is 7 */
    152. 

  152. #define DAC_TRIANGLE_AMPLITUDE_15   DAC_WAVE_BIT_WIDTH_4  /*!< triangle amplitude is 15 */
    153. 

  153. #define DAC_TRIANGLE_AMPLITUDE_31   DAC_WAVE_BIT_WIDTH_5  /*!< triangle amplitude is 31 */
    154. 

  154. #define DAC_TRIANGLE_AMPLITUDE_63   DAC_WAVE_BIT_WIDTH_6  /*!< triangle amplitude is 63 */
    155. 

  155. #define DAC_TRIANGLE_AMPLITUDE_127  DAC_WAVE_BIT_WIDTH_7  /*!< triangle amplitude is 127 */
    156. 

  156. #define DAC_TRIANGLE_AMPLITUDE_255  DAC_WAVE_BIT_WIDTH_8  /*!< triangle amplitude is 255 */
    157. 

  157. #define DAC_TRIANGLE_AMPLITUDE_511  DAC_WAVE_BIT_WIDTH_9  /*!< triangle amplitude is 511 */
    158. 

  158. #define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
    159. 

  159. #define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
    160. 

  160. #define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
    161. 

  161. 

  162. /* DAC data alignment */
    163. 

  163. #define DATA_ALIGN(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
    164. 

  164. #define DAC_ALIGN_12B_R         DATA_ALIGN(0)        /*!< data right 12b alignment */
    165. 

  165. #define DAC_ALIGN_12B_L         DATA_ALIGN(1)        /*!< data left 12b alignment */
    166. 

  166. #define DAC_ALIGN_8B_R          DATA_ALIGN(2)        /*!< data right 8b alignment */
    167. 

  167. 

  168. /* function declarations */
    169. 

  169. /* deinitialize DAC */
    170. 

  170. void dac_deinit(void);
    171. 

  171. /* enable DAC */
    172. 

  172. void dac_enable(uint32_t dac_periph);
    173. 

  173. /* disable DAC */
    174. 

  174. void dac_disable(uint32_t dac_periph);
    175. 

  175. /* enable DAC DMA */
    176. 

  176. void dac_dma_enable(uint32_t dac_periph);
    177. 

  177. /* disable DAC DMA */
    178. 

  178. void dac_dma_disable(uint32_t dac_periph); 
    179. 

  179. /* enable DAC output buffer */
    180. 

  180. void dac_output_buffer_enable(uint32_t dac_periph);
    181. 

  181. /* disable DAC output buffer */
    182. 

  182. void dac_output_buffer_disable(uint32_t dac_periph);
    183. 

  183. /* enable DAC trigger */
    184. 

  184. void dac_trigger_enable(uint32_t dac_periph);
    185. 

  185. /* disable DAC trigger */
    186. 

  186. void dac_trigger_disable(uint32_t dac_periph);
    187. 

  187. /* enable DAC software trigger */
    188. 

  188. void dac_software_trigger_enable(uint32_t dac_periph);
    189. 

  189. /* disable DAC software trigger */
    190. 

  190. void dac_software_trigger_disable(uint32_t dac_periph);
    191. 

  191. /* enable DAC interrupt(DAC0 DMA underrun interrupt) */
    192. 

  192. void dac_interrupt_enable(uint32_t dac_periph);
    193. 

  193. /* disable DAC interrupt(DAC0 DMA underrun interrupt) */
    194. 

  194. void dac_interrupt_disable(uint32_t dac_periph);
    195. 

  195. 

  196. /* configure DAC trigger source */
    197. 

  197. void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
    198. 

  198. /* configure DAC wave mode */
    199. 

  199. void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
    200. 

  200. /* configure DAC wave bit width */
    201. 

  201. void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
    202. 

  202. /* configure DAC LFSR noise mode */
    203. 

  203. void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
    204. 

  204. /* configure DAC triangle noise mode */
    205. 

  205. void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
    206. 

  206. /* get the last data output value */
    207. 

  207. uint16_t dac_output_value_get(uint32_t dac_periph);
    208. 

  208. 

  209. /* set DAC data holding register value */
    210. 

  210. void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
    211. 

  211. /* set DAC concurrent mode data holding register value */
    212. 

  212. void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); 
    213. 

  213. 

  214. /* enable DAC concurrent mode */
    215. 

  215. void dac_concurrent_enable(void);
    216. 

  216. /* disable DAC concurrent mode */
    217. 

  217. void dac_concurrent_disable(void);
    218. 

  218. /* enable DAC concurrent software trigger */
    219. 

  219. void dac_concurrent_software_trigger_enable(void);
    220. 

  220. /* disable DAC concurrent software trigger */
    221. 

  221. void dac_concurrent_software_trigger_disable(void);
    222. 

  222. /* enable DAC concurrent buffer function */
    223. 

  223. void dac_concurrent_output_buffer_enable(void);
    224. 

  224. /* disable DAC concurrent buffer function */
    225. 

  225. void dac_concurrent_output_buffer_disable(void);
    226. 

  226. /* enable DAC concurrent interrupt */
    227. 

  227. void dac_concurrent_interrupt_enable(void);
    228. 

  228. /* disable DAC concurrent interrupt */
    229. 

  229. void dac_concurrent_interrupt_disable(void);
    230. 

  230. 

  231. /* get the specified DAC flag(DAC DMA underrun flag) */
    232. 

  232. FlagStatus dac_flag_get(uint32_t dac_periph);
    233. 

  233. /* clear the specified DAC flag(DAC DMA underrun flag) */
    234. 

  234. void dac_flag_clear(uint32_t dac_periph);
    235. 

  235. /* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
    236. 

  236. FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
    237. 

  237. /* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
    238. 

  238. void dac_interrupt_flag_clear(uint32_t dac_periph);
    239. 

  239. 

  240. #endif /* GD32F4XX_DAC_H */
    241.