Home Explore Help
Register Sign In
lqb
/
rt-thread
mirror of https://gitee.com/rtthread/rt-thread.git
1
0
Fork 0
Files Issues 0 Wiki
Tree: a8d27156a3
Branches Tags
rt-thread
/
bsp
/
gd32450z-eval
/
Libraries
/
GD32F4xx_standard_peripheral
/
Include
/
gd32f4xx_dma.h

gd32f4xx_dma.h 27 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380 
  1. /*!
    2. 

  2.     \file  gd32f4xx_dma.h
    3. 

  3.     \brief definitions for the DMA
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2016 GigaDevice
    8. 

  8. 

  9.     2016-08-15, V1.0.0, firmware for GD32F4xx
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F4XX_DMA_H
    13. 

  13. #define GD32F4XX_DMA_H
    14. 

  14. 

  15. #include "gd32f4xx.h"
    16. 

  16. 

  17. /* DMA definitions */
    18. 

  18. #define DMA0                              (DMA_BASE)                    /*!< DMA0 base address */
    19. 

  19. #define DMA1                              (DMA_BASE + 0x0400U)          /*!< DMA1 base address */
    20. 

  20. 

  21. /* registers definitions */
    22. 

  22. #define DMA_INTF0(dmax)                    REG32((dmax) + 0x00U)        /*!< DMA interrupt flag register 0 */
    23. 

  23. #define DMA_INTF1(dmax)                    REG32((dmax) + 0x04U)        /*!< DMA interrupt flag register 1 */
    24. 

  24. #define DMA_INTC0(dmax)                    REG32((dmax) + 0x08U)        /*!< DMA interrupt flag clear register 0 */
    25. 

  25. #define DMA_INTC1(dmax)                    REG32((dmax) + 0x0CU)        /*!< DMA interrupt flag clear register 1 */
    26. 

  26. 

  27. #define DMA_CH0CTL(dmax)                   REG32((dmax) + 0x10U)        /*!< DMA channel 0 control register */
    28. 

  28. #define DMA_CH0CNT(dmax)                   REG32((dmax) + 0x14U)        /*!< DMA channel 0 counter register */
    29. 

  29. #define DMA_CH0PADDR(dmax)                 REG32((dmax) + 0x18U)        /*!< DMA channel 0 peripheral base address register */
    30. 

  30. #define DMA_CH0M0ADDR(dmax)                REG32((dmax) + 0x1CU)        /*!< DMA channel 0 memory 0 base address register */
    31. 

  31. #define DMA_CH0M1ADDR(dmax)                REG32((dmax) + 0x20U)        /*!< DMA channel 0 memory 1 base address register */
    32. 

  32. #define DMA_CH0FCTL(dmax)                  REG32((dmax) + 0x24U)        /*!< DMA channel 0 FIFO control register */
    33. 

  33. 

  34. #define DMA_CH1CTL(dmax)                   REG32((dmax) + 0x28U)        /*!< DMA channel 1 control register */
    35. 

  35. #define DMA_CH1CNT(dmax)                   REG32((dmax) + 0x2CU)        /*!< DMA channel 1 counter register */
    36. 

  36. #define DMA_CH1PADDR(dmax)                 REG32((dmax) + 0x30U)        /*!< DMA channel 1 peripheral base address register */
    37. 

  37. #define DMA_CH1M0ADDR(dmax)                REG32((dmax) + 0x34U)        /*!< DMA channel 1 memory 0 base address register */
    38. 

  38. #define DMA_CH1M1ADDR(dmax)                REG32((dmax) + 0x38U)        /*!< DMA channel 1 memory 1 base address register */
    39. 

  39. #define DMA_CH1FCTL(dmax)                  REG32((dmax) + 0x3CU)        /*!< DMA channel 1 FIFO control register */
    40. 

  40. 

  41. #define DMA_CH2CTL(dmax)                   REG32((dmax) + 0x40U)        /*!< DMA channel 2 control register */
    42. 

  42. #define DMA_CH2CNT(dmax)                   REG32((dmax) + 0x44U)        /*!< DMA channel 2 counter register */
    43. 

  43. #define DMA_CH2PADDR(dmax)                 REG32((dmax) + 0x48U)        /*!< DMA channel 2 peripheral base address register */
    44. 

  44. #define DMA_CH2M0ADDR(dmax)                REG32((dmax) + 0x4CU)        /*!< DMA channel 2 memory 0 base address register */
    45. 

  45. #define DMA_CH2M1ADDR(dmax)                REG32((dmax) + 0x50U)        /*!< DMA channel 2 memory 1 base address register */
    46. 

  46. #define DMA_CH2FCTL(dmax)                  REG32((dmax) + 0x54U)        /*!< DMA channel 2 FIFO control register */
    47. 

  47. 

  48. #define DMA_CH3CTL(dmax)                   REG32((dmax) + 0x58U)        /*!< DMA channel 3 control register */
    49. 

  49. #define DMA_CH3CNT(dmax)                   REG32((dmax) + 0x5CU)        /*!< DMA channel 3 counter register */
    50. 

  50. #define DMA_CH3PADDR(dmax)                 REG32((dmax) + 0x60U)        /*!< DMA channel 3 peripheral base address register */
    51. 

  51. #define DMA_CH3M0ADDR(dmax)                REG32((dmax) + 0x64U)        /*!< DMA channel 3 memory 0 base address register */
    52. 

  52. #define DMA_CH3M1ADDR(dmax)                REG32((dmax) + 0x68U)        /*!< DMA channel 3 memory 1 base address register */
    53. 

  53. #define DMA_CH3FCTL(dmax)                  REG32((dmax) + 0x6CU)        /*!< DMA channel 3 FIFO control register */
    54. 

  54. 

  55. #define DMA_CH4CTL(dmax)                   REG32((dmax) + 0x70U)        /*!< DMA channel 4 control register */
    56. 

  56. #define DMA_CH4CNT(dmax)                   REG32((dmax) + 0x74U)        /*!< DMA channel 4 counter register */
    57. 

  57. #define DMA_CH4PADDR(dmax)                 REG32((dmax) + 0x78U)        /*!< DMA channel 4 peripheral base address register */
    58. 

  58. #define DMA_CH4M0ADDR(dmax)                REG32((dmax) + 0x7CU)        /*!< DMA channel 4 memory 0 base address register */
    59. 

  59. #define DMA_CH4M1ADDR(dmax)                REG32((dmax) + 0x80U)        /*!< DMA channel 4 memory 1 base address register */
    60. 

  60. #define DMA_CH4FCTL(dmax)                  REG32((dmax) + 0x84U)        /*!< DMA channel 4 FIFO control register */
    61. 

  61. 

  62. #define DMA_CH5CTL(dmax)                   REG32((dmax) + 0x88U)        /*!< DMA channel 5 control register */
    63. 

  63. #define DMA_CH5CNT(dmax)                   REG32((dmax) + 0x8CU)        /*!< DMA channel 5 counter register */
    64. 

  64. #define DMA_CH5PADDR(dmax)                 REG32((dmax) + 0x90U)        /*!< DMA channel 5 peripheral base address register */
    65. 

  65. #define DMA_CH5M0ADDR(dmax)                REG32((dmax) + 0x94U)        /*!< DMA channel 5 memory 0 base address register */
    66. 

  66. #define DMA_CH5M1ADDR(dmax)                REG32((dmax) + 0x98U)        /*!< DMA channel 5 memory 1 base address register */
    67. 

  67. #define DMA_CH5FCTL(dmax)                  REG32((dmax) + 0x9CU)        /*!< DMA channel 5 FIFO control register */
    68. 

  68. 

  69. #define DMA_CH6CTL(dmax)                   REG32((dmax) + 0xA0U)        /*!< DMA channel 6 control register */
    70. 

  70. #define DMA_CH6CNT(dmax)                   REG32((dmax) + 0xA4U)        /*!< DMA channel 6 counter register */
    71. 

  71. #define DMA_CH6PADDR(dmax)                 REG32((dmax) + 0xA8U)        /*!< DMA channel 6 peripheral base address register */
    72. 

  72. #define DMA_CH6M0ADDR(dmax)                REG32((dmax) + 0xACU)        /*!< DMA channel 6 memory 0 base address register */
    73. 

  73. #define DMA_CH6M1ADDR(dmax)                REG32((dmax) + 0xB0U)        /*!< DMA channel 6 memory 1 base address register */
    74. 

  74. #define DMA_CH6FCTL(dmax)                  REG32((dmax) + 0xB4U)        /*!< DMA channel 6 FIFO control register */
    75. 

  75. 

  76. #define DMA_CH7CTL(dmax)                   REG32((dmax) + 0xB8U)        /*!< DMA channel 7 control register */
    77. 

  77. #define DMA_CH7CNT(dmax)                   REG32((dmax) + 0xBCU)        /*!< DMA channel 7 counter register */
    78. 

  78. #define DMA_CH7PADDR(dmax)                 REG32((dmax) + 0xC0U)        /*!< DMA channel 7 peripheral base address register */
    79. 

  79. #define DMA_CH7M0ADDR(dmax)                REG32((dmax) + 0xC4U)        /*!< DMA channel 7 memory 0 base address register */
    80. 

  80. #define DMA_CH7M1ADDR(dmax)                REG32((dmax) + 0xC8U)        /*!< DMA channel 7 memory 1 base address register */
    81. 

  81. #define DMA_CH7FCTL(dmax)                  REG32((dmax) + 0xCCU)        /*!< DMA channel 7 FIFO control register */
    82. 

  82. 

  83. /* bits definitions */
    84. 

  84. /* DMA_INTF */
    85. 

  85. #define DMA_INTF_FEEIF                    BIT(0)                        /*!< FIFO error and exception flag */
    86. 

  86. #define DMA_INTF_SDEIF                    BIT(2)                        /*!< single data mode exception flag */
    87. 

  87. #define DMA_INTF_TAEIF                    BIT(3)                        /*!< transfer access error flag */
    88. 

  88. #define DMA_INTF_HTFIF                    BIT(4)                        /*!< half transfer finish flag */
    89. 

  89. #define DMA_INTF_FTFIF                    BIT(5)                        /*!< full transger finish flag */
    90. 

  90. 

  91. /* DMA_INTC */
    92. 

  92. #define DMA_INTC_FEEIFC                   BIT(0)                        /*!< clear FIFO error and exception flag */
    93. 

  93. #define DMA_INTC_SDEIFC                   BIT(2)                        /*!< clear single data mode exception flag */
    94. 

  94. #define DMA_INTC_TAEIFC                   BIT(3)                        /*!< clear single data mode exception flag */
    95. 

  95. #define DMA_INTC_HTFIFC                   BIT(4)                        /*!< clear half transfer finish flag */
    96. 

  96. #define DMA_INTC_FTFIFC                   BIT(5)                        /*!< clear full transger finish flag */
    97. 

  97. 

  98. /* DMA_CHxCTL,x=0..7 */
    99. 

  99. #define DMA_CHXCTL_CHEN                   BIT(0)                        /*!< channel x enable */
    100. 

  100. #define DMA_CHXCTL_SDEIE                  BIT(1)                        /*!< enable bit for channel x single data mode exception interrupt */
    101. 

  101. #define DMA_CHXCTL_TAEIE                  BIT(2)                        /*!< enable bit for channel x tranfer access error interrupt */
    102. 

  102. #define DMA_CHXCTL_HTFIE                  BIT(3)                        /*!< enable bit for channel x half transfer finish interrupt */
    103. 

  103. #define DMA_CHXCTL_FTFIE                  BIT(4)                        /*!< enable bit for channel x full transfer finish interrupt */
    104. 

  104. #define DMA_CHXCTL_TFCS                   BIT(5)                        /*!< transfer flow controller select */
    105. 

  105. #define DMA_CHXCTL_TM                     BITS(6,7)                     /*!< transfer mode */
    106. 

  106. #define DMA_CHXCTL_CMEN                   BIT(8)                        /*!< circulation mode */
    107. 

  107. #define DMA_CHXCTL_PNAGA                  BIT(9)                        /*!< next address generation algorithm of peripheral */
    108. 

  108. #define DMA_CHXCTL_MNAGA                  BIT(10)                       /*!< next address generation algorithm of memory */
    109. 

  109. #define DMA_CHXCTL_PWIDTH                 BITS(11,12)                   /*!< transfer width of peipheral */
    110. 

  110. #define DMA_CHXCTL_MWIDTH                 BITS(13,14)                   /*!< transfer width of memory */
    111. 

  111. #define DMA_CHXCTL_PAIF                   BIT(15)                       /*!< peripheral address increment fixed */
    112. 

  112. #define DMA_CHXCTL_PRIO                   BITS(16,17)                   /*!< priority level */
    113. 

  113. #define DMA_CHXCTL_SBMEN                  BIT(18)                       /*!< switch-buffer mode enable */
    114. 

  114. #define DMA_CHXCTL_MBS                    BIT(19)                       /*!< memory buffer select */
    115. 

  115. #define DMA_CHXCTL_PBURST                 BITS(21,22)                   /*!< transfer burst type of peripheral */
    116. 

  116. #define DMA_CHXCTL_MBURST                 BITS(23,24)                   /*!< transfer burst type of memory */
    117. 

  117. #define DMA_CHXCTL_PERIEN                 BITS(25,27)                   /*!< peripheral enable */
    118. 

  118. 

  119. /* DMA_CHxCNT,x=0..7 */
    120. 

  120. #define DMA_CHXCNT_CNT                    BITS(0,15)                    /*!< transfer counter */
    121. 

  121. 

  122. /* DMA_CHxPADDR,x=0..7 */
    123. 

  123. #define DMA_CHXPADDR_PADDR                BITS(0,31)                    /*!< peripheral base address */
    124. 

  124. 

  125. /* DMA_CHxM0ADDR,x=0..7 */
    126. 

  126. #define DMA_CHXM0ADDR_PADDR               BITS(0,31)                    /*!< memory 0 base address */
    127. 

  127. 

  128. /* DMA_CHxM1ADDR,x=0..7 */
    129. 

  129. #define DMA_CHXM1ADDR_PADDR               BITS(0,31)                    /*!< memory 1 base address */
    130. 

  130. 

  131. /* DMA_CHxFCTL,x=0..7 */
    132. 

  132. #define DMA_CHXFCTL_FCCV                  BITS(0,1)                     /*!< FIFO counter critical value */
    133. 

  133. #define DMA_CHXFCTL_MDMEN                 BIT(2)                        /*!< multi-data mode enable */
    134. 

  134. #define DMA_CHXFCTL_FCNT                  BITS(3,5)                     /*!< FIFO counter */
    135. 

  135. #define DMA_CHXFCTL_FEEIE                 BIT(7)                        /*!< FIFO exception interrupt enable */
    136. 

  136. 

  137. /* constants definitions */
    138. 

  138. /* DMA channel select */
    139. 

  139. typedef enum 
    140. 

  140. {
    141. 

  141.     DMA_CH0 = 0,                                    /*!< DMA Channel 0 */
    142. 

  142.     DMA_CH1,                                        /*!< DMA Channel 1 */
    143. 

  143.     DMA_CH2,                                        /*!< DMA Channel 2 */
    144. 

  144.     DMA_CH3,                                        /*!< DMA Channel 3 */
    145. 

  145.     DMA_CH4,                                        /*!< DMA Channel 4 */
    146. 

  146.     DMA_CH5,                                        /*!< DMA Channel 5 */
    147. 

  147.     DMA_CH6,                                        /*!< DMA Channel 6 */
    148. 

  148.     DMA_CH7                                         /*!< DMA Channel 7 */
    149. 

  149. } dma_channel_enum;
    150. 

  150. 

  151. /* DMA peripheral select */
    152. 

  152. typedef enum 
    153. 

  153. {
    154. 

  154.     DMA_SUBPERI0 = 0,                               /*!< DMA Peripheral 0 */
    155. 

  155.     DMA_SUBPERI1,                                   /*!< DMA Peripheral 1 */
    156. 

  156.     DMA_SUBPERI2,                                   /*!< DMA Peripheral 2 */
    157. 

  157.     DMA_SUBPERI3,                                   /*!< DMA Peripheral 3 */
    158. 

  158.     DMA_SUBPERI4,                                   /*!< DMA Peripheral 4 */
    159. 

  159.     DMA_SUBPERI5,                                   /*!< DMA Peripheral 5 */
    160. 

  160.     DMA_SUBPERI6,                                   /*!< DMA Peripheral 6 */
    161. 

  161.     DMA_SUBPERI7                                    /*!< DMA Peripheral 7 */
    162. 

  162. } dma_subperipheral_enum;
    163. 

  163. 

  164. /* DMA multidata mode initialize struct */
    165. 

  165. typedef struct
    166. 

  166. {
    167. 

  167.     uint32_t periph_addr;                           /*!< peripheral base address */
    168. 

  168.     uint32_t periph_width;                          /*!< transfer data size of peripheral */
    169. 

  169.     uint32_t periph_inc;                            /*!< peripheral increasing mode */  
    170. 

  170. 

  171.     uint32_t memory0_addr;                          /*!< memory 0 base address */
    172. 

  172.     uint32_t memory_width;                          /*!< transfer data size of memory */
    173. 

  173.     uint32_t memory_inc;                            /*!< memory increasing mode */
    174. 

  174. 

  175.     uint32_t memory_burst_width;                    /*!< multi data mode enable */
    176. 

  176.     uint32_t periph_burst_width;                    /*!< multi data mode enable */
    177. 

  177.     uint32_t critical_value;                        /*!< FIFO critical */
    178. 

  178. 

  179.     uint32_t circular_mode;
    180. 

  180.     uint32_t direction;                             /*!< channel data transfer direction */
    181. 

  181.     uint32_t number;                                /*!< channel transfer number */
    182. 

  182.     uint32_t priority;                              /*!< channel priority level */
    183. 

  183. }dma_multi_data_parameter_struct;
    184. 

  184. 

  185. /* DMA singledata mode initialize struct */
    186. 

  186. typedef struct
    187. 

  187. {
    188. 

  188.     uint32_t periph_addr;                           /*!< peripheral base address */
    189. 

  189.     uint32_t periph_inc;                            /*!< peripheral increasing mode */  
    190. 

  190. 

  191.     uint32_t memory0_addr;                          /*!< memory 0 base address */
    192. 

  192.     uint32_t memory_inc;                            /*!< memory increasing mode */
    193. 

  193. 

  194.     uint32_t periph_memory_width;                   /*!< transfer data size of peripheral */
    195. 

  195. 

  196.     uint32_t circular_mode;                         /*!< DMA circular mode */
    197. 

  197.     uint32_t direction;                             /*!< channel data transfer direction */
    198. 

  198.     uint32_t number;                                /*!< channel transfer number */
    199. 

  199.     uint32_t priority;                              /*!< channel priority level */
    200. 

  200. } dma_single_data_parameter_struct;
    201. 

  201. 

  202. #define DMA_FLAG_ADD(flag,channel)        ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U)))   /*!< DMA channel flag shift */
    203. 

  203. 

  204. /* DMA_register address */
    205. 

  205. #define DMA_CHCTL(dma,channel)            REG32(((dma) + 0x10U) + 0x18U*(channel))  /*!< the address of DMA channel CHXCTL register  */
    206. 

  206. #define DMA_CHCNT(dma,channel)            REG32(((dma) + 0x14U) + 0x18U*(channel))  /*!< the address of DMA channel CHXCNT register */
    207. 

  207. #define DMA_CHPADDR(dma,channel)          REG32(((dma) + 0x18U) + 0x18U*(channel))  /*!< the address of DMA channel CHXPADDR register */
    208. 

  208. #define DMA_CHM0ADDR(dma,channel)         REG32(((dma) + 0x1CU) + 0x18U*(channel))  /*!< the address of DMA channel CHXM0ADDR register */
    209. 

  209. #define DMA_CHM1ADDR(dma,channel)         REG32(((dma) + 0x20U) + 0x18U*(channel))  /*!< the address of DMA channel CHXM1ADDR register */
    210. 

  210. #define DMA_CHFCTL(dma,channel)           REG32(((dma) + 0x24U) + 0x18U*(channel))  /*!< the address of DMA channel CHXMADDR register */
    211. 

  211. 

  212. /* peripheral select */
    213. 

  213. #define CHCTL_PERIEN(regval)              (BITS(25,27) & ((uint32_t)(regval) << 25))
    214. 

  214. #define DMA_PERIPH_0_SELECT               CHCTL_PERIEN(0)                           /*!< peripheral 0 select */
    215. 

  215. #define DMA_PERIPH_1_SELECT               CHCTL_PERIEN(1)                           /*!< peripheral 1 select */
    216. 

  216. #define DMA_PERIPH_2_SELECT               CHCTL_PERIEN(2)                           /*!< peripheral 2 select */
    217. 

  217. #define DMA_PERIPH_3_SELECT               CHCTL_PERIEN(3)                           /*!< peripheral 3 select */
    218. 

  218. #define DMA_PERIPH_4_SELECT               CHCTL_PERIEN(4)                           /*!< peripheral 4 select */
    219. 

  219. #define DMA_PERIPH_5_SELECT               CHCTL_PERIEN(5)                           /*!< peripheral 5 select */
    220. 

  220. #define DMA_PERIPH_6_SELECT               CHCTL_PERIEN(6)                           /*!< peripheral 6 select */
    221. 

  221. #define DMA_PERIPH_7_SELECT               CHCTL_PERIEN(7)                           /*!< peripheral 7 select */
    222. 

  222. 

  223. /* burst type of memory */
    224. 

  224. #define CHCTL_MBURST(regval)              (BITS(23,24) & ((uint32_t)(regval) << 23))
    225. 

  225. #define DMA_MEMORY_BURST_SINGLE           CHCTL_MBURST(0)                           /*!< single burst */
    226. 

  226. #define DMA_MEMORY_BURST_4_BEAT           CHCTL_MBURST(1)                           /*!< 4-beat burst */
    227. 

  227. #define DMA_MEMORY_BURST_8_BEAT           CHCTL_MBURST(2)                           /*!< 8-beat burst */
    228. 

  228. #define DMA_MEMORY_BURST_16_BEAT          CHCTL_MBURST(3)                           /*!< 16-beat burst */
    229. 

  229. 

  230. /* burst type of peripheral */
    231. 

  231. #define CHCTL_PBURST(regval)              (BITS(21,22) & ((uint32_t)(regval) << 21))
    232. 

  232. #define DMA_PERIPH_BURST_SINGLE           CHCTL_PBURST(0)                           /*!< single burst */
    233. 

  233. #define DMA_PERIPH_BURST_4_BEAT           CHCTL_PBURST(1)                           /*!< 4-beat burst */
    234. 

  234. #define DMA_PERIPH_BURST_8_BEAT           CHCTL_PBURST(2)                           /*!< 8-beat burst */
    235. 

  235. #define DMA_PERIPH_BURST_16_BEAT          CHCTL_PBURST(3)                           /*!< 16-beat burst */
    236. 

  236. 

  237. /* channel priority level */
    238. 

  238. #define CHCTL_PRIO(regval)                (BITS(16,17) & ((uint32_t)(regval) << 16))
    239. 

  239. #define DMA_PRIORITY_LOW                  CHCTL_PRIO(0)                             /*!< low priority */
    240. 

  240. #define DMA_PRIORITY_MEDIUM               CHCTL_PRIO(1)                             /*!< medium priority */
    241. 

  241. #define DMA_PRIORITY_HIGH                 CHCTL_PRIO(2)                             /*!< high priority */
    242. 

  242. #define DMA_PRIORITY_ULTRA_HIGH           CHCTL_PRIO(3)                             /*!< ultra high priority */
    243. 

  243. 

  244. /* transfer data width of memory */
    245. 

  245. #define CHCTL_MWIDTH(regval)              (BITS(13,14) & ((uint32_t)(regval) << 13))
    246. 

  246. #define DMA_MEMORY_WIDTH_8BIT             CHCTL_MWIDTH(0)                           /*!< transfer data width of memory is 8-bit */
    247. 

  247. #define DMA_MEMORY_WIDTH_16BIT            CHCTL_MWIDTH(1)                           /*!< transfer data width of memory is 16-bit */
    248. 

  248. #define DMA_MEMORY_WIDTH_32BIT            CHCTL_MWIDTH(2)                           /*!< transfer data width of memory is 32-bit */
    249. 

  249. 

  250. /* transfer data width of peripheral */
    251. 

  251. #define CHCTL_PWIDTH(regval)              (BITS(11,12) & ((uint32_t)(regval) << 11))
    252. 

  252. #define DMA_PERIPH_WIDTH_8BIT             CHCTL_PWIDTH(0)                           /*!< transfer data width of peripheral is 8-bit */
    253. 

  253. #define DMA_PERIPH_WIDTH_16BIT            CHCTL_PWIDTH(1)                           /*!< transfer data width of peripheral is 16-bit */
    254. 

  254. #define DMA_PERIPH_WIDTH_32BIT            CHCTL_PWIDTH(2)                           /*!< transfer data width of peripheral is 32-bit */
    255. 

  255. 

  256. /* channel transfer mode */
    257. 

  257. #define CHCTL_TM(regval)                  (BITS(6,7) & ((uint32_t)(regval) << 6))
    258. 

  258. #define DMA_PERIPH_TO_MEMORY              CHCTL_TM(0)                               /*!< read from peripheral and write to memory */
    259. 

  259. #define DMA_MEMORY_TO_PERIPH              CHCTL_TM(1)                               /*!< read from memory and write to peripheral */
    260. 

  260. #define DMA_MEMORY_TO_MEMORY              CHCTL_TM(2)                               /*!< read from memory and write to memory */
    261. 

  261. 

  262. /* FIFO counter critical value */
    263. 

  263. #define CHFCTL_FCCV(regval)               (BITS(0,1) & ((uint32_t)(regval) << 0))
    264. 

  264. #define DMA_FIFO_1_WORD                   CHFCTL_FCCV(0)                            /*!< critical value 1 word */
    265. 

  265. #define DMA_FIFO_2_WORD                   CHFCTL_FCCV(1)                            /*!< critical value 2 word */
    266. 

  266. #define DMA_FIFO_3_WORD                   CHFCTL_FCCV(2)                            /*!< critical value 3 word */
    267. 

  267. #define DMA_FIFO_4_WORD                   CHFCTL_FCCV(3)                            /*!< critical value 4 word */
    268. 

  268. 

  269. /* memory select */
    270. 

  270. #define DMA_MEMORY_0                      ((uint32_t)0x00000000U)                   /*!< select memory 0 */
    271. 

  271. #define DMA_MEMORY_1                      ((uint32_t)0x00000001U)                   /*!< select memory 1 */
    272. 

  272. 

  273. /* DMA circular mode */
    274. 

  274. #define DMA_CIRCULAR_MODE_ENABLE          ((uint32_t)0x00000000U)                   /*!< circular mode enable */
    275. 

  275. #define DMA_CIRCULAR_MODE_DISABLE         ((uint32_t)0x00000001U)                   /*!< circular mode disable */
    276. 

  276. 

  277. /* DMA flow controller select */
    278. 

  278. #define DMA_FLOW_CONTROLLER_DMA           ((uint32_t)0x00000000U)                   /*!< DMA is the flow controler */
    279. 

  279. #define DMA_FLOW_CONTROLLER_PERI          ((uint32_t)0x00000001U)                   /*!< peripheral is the flow controler */
    280. 

  280. 

  281. /* peripheral increasing mode */
    282. 

  282. #define DMA_PERIPH_INCREASE_ENABLE        ((uint32_t)0x00000000U)                   /*!< next address of peripheral is increasing address mode */
    283. 

  283. #define DMA_PERIPH_INCREASE_DISABLE       ((uint32_t)0x00000001U)                   /*!< next address of peripheral is fixed address mode */
    284. 

  284. #define DMA_PERIPH_INCREASE_FIX           ((uint32_t)0x00000002U)                   /*!< next address of peripheral is increasing fixed */
    285. 

  285. 

  286. /* memory increasing mode */
    287. 

  287. #define DMA_MEMORY_INCREASE_ENABLE        ((uint32_t)0x00000000U)                   /*!< next address of memory is increasing address mode */
    288. 

  288. #define DMA_MEMORY_INCREASE_DISABLE       ((uint32_t)0x00000001U)                   /*!< next address of memory is fixed address mode */
    289. 

  289. 

  290. /* FIFO status */
    291. 

  291. #define DMA_FIFO_STATUS_NODATA            ((uint32_t)0x00000000U)                   /*!< the data in the FIFO less than 1 word */
    292. 

  292. #define DMA_FIFO_STATUS_1_WORD            ((uint32_t)0x00000001U)                   /*!< the data in the FIFO more than 1 word, less than 2 words */
    293. 

  293. #define DMA_FIFO_STATUS_2_WORD            ((uint32_t)0x00000002U)                   /*!< the data in the FIFO more than 2 word, less than 3 words */
    294. 

  294. #define DMA_FIFO_STATUS_3_WORD            ((uint32_t)0x00000003U)                   /*!< the data in the FIFO more than 3 word, less than 4 words */
    295. 

  295. #define DMA_FIFO_STATUS_EMPTY             ((uint32_t)0x00000004U)                   /*!< the data in the FIFO is empty */
    296. 

  296. #define DMA_FIFO_STATUS_FULL              ((uint32_t)0x00000005U)                   /*!< the data in the FIFO is full */
    297. 

  297. 

  298. /* DMA reset value */
    299. 

  299. #define DMA_CHCTL_RESET_VALUE             ((uint32_t)0x00000000U)                   /*!< the reset value of DMA channel CHXCTL register  */
    300. 

  300. #define DMA_CHCNT_RESET_VALUE             ((uint32_t)0x00000000U)                   /*!< the reset value of DMA channel CHXCNT register  */
    301. 

  301. #define DMA_CHPADDR_RESET_VALUE           ((uint32_t)0x00000000U)                   /*!< the reset value of DMA channel CHXPADDR register  */
    302. 

  302. #define DMA_CHMADDR_RESET_VALUE           ((uint32_t)0x00000000U)                   /*!< the reset value of DMA channel CHXMADDR register  */
    303. 

  303. #define DMA_CHINTF_RESET_VALUE            ((uint32_t)0x0000003DU)                   /*!< clear DMA channel CHXINTFS register  */
    304. 

  304. #define DMA_CHFCTL_RESET_VALUE            ((uint32_t)0x00000000U)                   /*!< the reset value of DMA channel CHXFCTL register  */
    305. 

  305. 

  306. /* function declarations */
    307. 

  307. /* deinitialize DMA a channel registers */
    308. 

  308. void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx);
    309. 

  309. /* DMA single data mode initialize */
    310. 

  310. void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct);
    311. 

  311. /* DMA multi data mode initialize */
    312. 

  312. void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_multi_data_parameter_struct init_struct);
    313. 

  313. 

  314. /* set DMA peripheral base address */
    315. 

  315. void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address);
    316. 

  316. /* set DMA Memory base address */
    317. 

  317. void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t memory_flag,uint32_t address);
    318. 

  318. 

  319. /* set the number of remaining data to be transferred by the DMA */
    320. 

  320. void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number);
    321. 

  321. /* get the number of remaining data to be transferred by the DMA */
    322. 

  322. uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx);
    323. 

  323. 

  324. /* configure priority level of DMA channel */
    325. 

  325. void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority);
    326. 

  326. 

  327. /* configure transfer burst beats of memory */
    328. 

  328. void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t mbeat);
    329. 

  329. /* configure transfer burst beats of peripheral */
    330. 

  330. void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat);
    331. 

  331. /* configure transfer data size of memory */
    332. 

  332. void dma_memory_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t msize);
    333. 

  333. /* configure transfer data size of peripheral */
    334. 

  334. void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize);
    335. 

  335. 

  336. /* configure next address increasement algorithm of memory */
    337. 

  337. void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm);
    338. 

  338. /* configure next address increasement algorithm of peripheral */
    339. 

  339. void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm);
    340. 

  340. 

  341. /* enable DMA circulation mode */
    342. 

  342. void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx);
    343. 

  343. /* disable DMA circulation mode */
    344. 

  344. void dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx);
    345. 

  345. /* enable DMA channel */
    346. 

  346. void dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx);
    347. 

  347. /* disable DMA channel */
    348. 

  348. void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx);
    349. 

  349. 

  350. /* configure the direction of data transfer on the channel */
    351. 

  351. void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction);
    352. 

  352. 

  353. /* DMA switch buffer mode config */
    354. 

  354. void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select);
    355. 

  355. /* DMA using memory get */
    356. 

  356. uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx);
    357. 

  357. 

  358. /* DMA channel peripheral select */
    359. 

  359. void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph);
    360. 

  360. /* DMA flow controller configure */
    361. 

  361. void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller);
    362. 

  362. /* DMA flow controller enable */
    363. 

  363. void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue);
    364. 

  364. /* DMA FIFO status get */
    365. 

  365. uint32_t dma_fifo_status_get(uint32_t dma_periph,dma_channel_enum channelx);
    366. 

  366. 

  367. /* check DMA flag is set or not */
    368. 

  368. FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag);
    369. 

  369. /* clear DMA a channel flag */
    370. 

  370. void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag);
    371. 

  371. /* check DMA flag is set or not */
    372. 

  372. FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt);
    373. 

  373. /* clear DMA a channel flag */
    374. 

  374. void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt);
    375. 

  375. /* enable DMA interrupt */
    376. 

  376. void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source);
    377. 

  377. /* disable DMA interrupt */
    378. 

  378. void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source);
    379. 

  379. 

  380. #endif /* GD32F4XX_DMA_H */
    381.