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gd32f4xx_fmc.h

gd32f4xx_fmc.h 25 KB
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  1. /*!
    2. 

  2.     \file  gd32f4xx_fmc.h
    3. 

  3.     \brief definitions for the FMC
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2016 GigaDevice
    8. 

  8. 

  9.     2016-08-15, V1.0.0, firmware for GD32F4xx
    10. 

  10. */
    11. 

  11. #ifndef GD32F4XX_FMC_H
    12. 

  12. #define GD32F4XX_FMC_H
    13. 

  13. 

  14. #include "gd32f4xx.h"
    15. 

  15. 

  16. /* FMC and option byte definition */
    17. 

  17. #define FMC                        FMC_BASE                       /*!< FMC register base address */
    18. 

  18. #define OB                         OB_BASE                        /*!< option byte base address */
    19. 

  19. 

  20. /* registers definitions */
    21. 

  21. #define FMC_WS                     REG32((FMC) + 0x00U)           /*!< FMC wait state register */
    22. 

  22. #define FMC_KEY                    REG32((FMC) + 0x04U)           /*!< FMC unlock key register */
    23. 

  23. #define FMC_OBKEY                  REG32((FMC) + 0x08U)           /*!< FMC option byte unlock key register */
    24. 

  24. #define FMC_STAT                   REG32((FMC) + 0x0CU)           /*!< FMC status register */
    25. 

  25. #define FMC_CTL                    REG32((FMC) + 0x10U)           /*!< FMC control register */
    26. 

  26. #define FMC_OBCTL0                 REG32((FMC) + 0x14U)           /*!< FMC option byte control register 0 */
    27. 

  27. #define FMC_OBCTL1                 REG32((FMC) + 0x18U)           /*!< FMC option byte control register 1 */
    28. 

  28. #define FMC_WSEN                   REG32((FMC) + 0xFCU)           /*!< FMC wait state enable register */
    29. 

  29. #define FMC_PID                    REG32((FMC) + 0x100U)          /*!< FMC product ID register */
    30. 

  30. 

  31. #define OB_WP1                     REG32((OB) + 0x00000008U)      /*!< option byte write protection 1 */
    32. 

  32. #define OB_USER                    REG32((OB) + 0x00010000U)      /*!< option byte user value*/
    33. 

  33. #define OB_SPC                     REG32((OB) + 0x00010001U)      /*!< option byte security protection value */
    34. 

  34. #define OB_WP0                     REG32((OB) + 0x00010008U)      /*!< option byte write protection 0 */
    35. 

  35. 

  36. /* bits definitions */
    37. 

  37. /* FMC_WS */
    38. 

  38. #define FMC_WC_WSCNT               BITS(0,3)                      /*!< wait state counter */
    39. 

  39. 

  40. /* FMC_KEY */
    41. 

  41. #define FMC_KEY_KEY                BITS(0,31)                     /*!< FMC main flash key bits */
    42. 

  42. 

  43. /* FMC_OBKEY */
    44. 

  44. #define FMC_OBKEY_OBKEY            BITS(0,31)                     /*!< option byte key bits */
    45. 

  45. 

  46. /* FMC_STAT */
    47. 

  47. #define FMC_STAT_END               BIT(0)                         /*!< end of operation flag bit */
    48. 

  48. #define FMC_STAT_OPERR             BIT(1)                         /*!< flash operation error flag bit */
    49. 

  49. #define FMC_STAT_WPERR             BIT(4)                         /*!< erase/Program protection error flag bit */
    50. 

  50. #define FMC_STAT_PGMERR            BIT(6)                         /*!< program size not match error flag bit */
    51. 

  51. #define FMC_STAT_PGSERR            BIT(7)                         /*!< program sequence error flag bit */
    52. 

  52. #define FMC_STAT_RDDERR            BIT(8)                         /*!< read D-bus protection error flag bit */
    53. 

  53. #define FMC_STAT_BUSY              BIT(16)                        /*!< flash busy flag bit */
    54. 

  54. 

  55. /* FMC_CTL */
    56. 

  56. #define FMC_CTL_PG                 BIT(0)                         /*!< main flash program command bit */
    57. 

  57. #define FMC_CTL_SER                BIT(1)                         /*!< main flash sector erase command bit */
    58. 

  58. #define FMC_CTL_MER0               BIT(2)                         /*!< main flash mass erase for bank0 command bit */
    59. 

  59. #define FMC_CTL_SN                 BITS(3,7)                      /*!< select which sector number to be erased */
    60. 

  60. #define FMC_CTL_PSZ                BITS(8,9)                      /*!< program size bit */
    61. 

  61. #define FMC_CTL_MER1               BIT(15)                        /*!< main flash mass erase for bank1 command bit */
    62. 

  62. #define FMC_CTL_START              BIT(16)                        /*!< send erase command to FMC bit */
    63. 

  63. #define FMC_CTL_ENDIE              BIT(24)                        /*!< end of operation interrupt enable bit */
    64. 

  64. #define FMC_CTL_ERRIE              BIT(25)                        /*!< error interrupt enable bit */
    65. 

  65. #define FMC_CTL_LK                 BIT(31)                        /*!< FMC_CTL lock bit */
    66. 

  66. 

  67. /* FMC_OBCTL0 */
    68. 

  68. #define FMC_OBCTL0_OB_LK           BIT(0)                         /*!< FMC_OBCTL0 lock bit */
    69. 

  69. #define FMC_OBCTL0_OB_START        BIT(1)                         /*!< send option byte change command to FMC bit */
    70. 

  70. #define FMC_OBCTL0_BOR_TH          BITS(2,3)                      /*!< option byte BOR threshold value */
    71. 

  71. #define FMC_OBCTL0_BB              BIT(4)                         /*!< option byte boot bank value */
    72. 

  72. #define FMC_OBCTL0_NWDG_HW         BIT(5)                         /*!< option byte watchdog value */
    73. 

  73. #define FMC_OBCTL0_NRST_DPSLP      BIT(6)                         /*!< option byte deepsleep reset value */
    74. 

  74. #define FMC_OBCTL0_NRST_STDBY      BIT(7)                         /*!< option byte standby reset value */
    75. 

  75. #define FMC_OBCTL0_SPC             BITS(8,15)                     /*!< option byte Security Protection code */
    76. 

  76. #define FMC_OBCTL0_WP0             BITS(16,27)                    /*!< erase/program protection of each sector when DRP is 0 */
    77. 

  77. #define FMC_OBCTL0_DBS             BIT(30)                        /*!< double banks or single bank selection when flash size is 1M bytes */
    78. 

  78. #define FMC_OBCTL0_DRP             BIT(31)                        /*!< D-bus read protection bit */
    79. 

  79. 

  80. /* FMC_OBCTL1 */
    81. 

  81. #define FMC_OBCTL1_WP1             BITS(16,27)                    /*!< erase/program protection of each sector when DRP is 0 */
    82. 

  82. 

  83. /* FMC_WSEN */
    84. 

  84. #define FMC_WSEN_WSEN              BIT(0)                         /*!< FMC wait state enable bit */
    85. 

  85. 

  86. /* FMC_PID */
    87. 

  87. #define FMC_PID_PID                BITS(0,31)                     /*!< product ID bits */
    88. 

  88. 

  89. /* constants definitions */
    90. 

  90. /* fmc state */
    91. 

  91. typedef enum
    92. 

  92. {
    93. 

  93.     FMC_READY,                                                    /*!< the operation has been completed */
    94. 

  94.     FMC_BUSY,                                                     /*!< the operation is in progress */
    95. 

  95.     FMC_RDDERR,                                                   /*!< read D-bus protection error */
    96. 

  96.     FMC_PGSERR,                                                   /*!< program sequence error */
    97. 

  97.     FMC_PGMERR,                                                   /*!< program size not match error */
    98. 

  98.     FMC_WPERR,                                                    /*!< erase/program protection error */
    99. 

  99.     FMC_OPERR,                                                    /*!< operation error */
    100. 

  100.     FMC_PGERR,                                                    /*!< program error */
    101. 

  101.     FMC_TOERR                                                     /*!< timeout error */
    102. 

  102. }fmc_state_enum;
    103. 

  103. 

  104. /* unlock key */
    105. 

  105. #define UNLOCK_KEY0                ((uint32_t)0x45670123U)        /*!< unlock key 0 */
    106. 

  106. #define UNLOCK_KEY1                ((uint32_t)0xCDEF89ABU)        /*!< unlock key 1 */
    107. 

  107. 

  108. #define OB_UNLOCK_KEY0             ((uint32_t)0x08192A3BU)        /*!< ob unlock key 0 */
    109. 

  109. #define OB_UNLOCK_KEY1             ((uint32_t)0x4C5D6E7FU)        /*!< ob unlock key 1 */
    110. 

  110. 

  111. /* FMC time out */
    112. 

  112. #define FMC_TIMEOUT_COUNT          ((uint32_t)0x000F0000)         /*!< enable FMC error timeout */
    113. 

  113. 

  114. /* option byte write protection */
    115. 

  115. #define OB_LWP                     ((uint32_t)0x000000FFU)        /*!< write protection low bits */
    116. 

  116. #define OB_HWP                     ((uint32_t)0x0000FF00U)        /*!< write protection high bits */
    117. 

  117. 

  118. /* FMC wait state counter */
    119. 

  119. #define WC_WSCNT(regval)           (BITS(0,3) & ((uint32_t)(regval)))
    120. 

  120. #define WS_WSCNT_0                 WC_WSCNT(0)                    /*!< FMC 0 wait */
    121. 

  121. #define WS_WSCNT_1                 WC_WSCNT(1)                    /*!< FMC 1 wait */
    122. 

  122. #define WS_WSCNT_2                 WC_WSCNT(2)                    /*!< FMC 2 wait */
    123. 

  123. #define WS_WSCNT_3                 WC_WSCNT(3)                    /*!< FMC 3 wait */
    124. 

  124. #define WS_WSCNT_4                 WC_WSCNT(4)                    /*!< FMC 4 wait */
    125. 

  125. #define WS_WSCNT_5                 WC_WSCNT(5)                    /*!< FMC 5 wait */
    126. 

  126. #define WS_WSCNT_6                 WC_WSCNT(6)                    /*!< FMC 6 wait */
    127. 

  127. #define WS_WSCNT_7                 WC_WSCNT(7)                    /*!< FMC 7 wait */
    128. 

  128. #define WS_WSCNT_8                 WC_WSCNT(8)                    /*!< FMC 8 wait */
    129. 

  129. #define WS_WSCNT_9                 WC_WSCNT(9)                    /*!< FMC 9 wait */
    130. 

  130. #define WS_WSCNT_10                WC_WSCNT(10)                   /*!< FMC 10 wait */
    131. 

  131. #define WS_WSCNT_11                WC_WSCNT(11)                   /*!< FMC 11 wait */
    132. 

  132. #define WS_WSCNT_12                WC_WSCNT(12)                   /*!< FMC 12 wait */
    133. 

  133. #define WS_WSCNT_13                WC_WSCNT(13)                   /*!< FMC 13 wait */
    134. 

  134. #define WS_WSCNT_14                WC_WSCNT(14)                   /*!< FMC 14 wait */
    135. 

  135. #define WS_WSCNT_15                WC_WSCNT(15)                   /*!< FMC 15 wait */
    136. 

  136. 

  137. /* option byte BOR threshold value */
    138. 

  138. #define OBCTL0_BOR_TH(regval)      (BITS(2,3) & ((uint32_t)(regval))<< 2)
    139. 

  139. #define OB_BOR_TH_VALUE3           OBCTL0_BOR_TH(0)               /*!< BOR threshold value 3 */
    140. 

  140. #define OB_BOR_TH_VALUE2           OBCTL0_BOR_TH(1)               /*!< BOR threshold value 2 */
    141. 

  141. #define OB_BOR_TH_VALUE1           OBCTL0_BOR_TH(2)               /*!< BOR threshold value 1 */
    142. 

  142. #define OB_BOR_TH_OFF              OBCTL0_BOR_TH(3)               /*!< no BOR function */
    143. 

  143. 

  144. /* option byte boot bank value */
    145. 

  145. #define OBCTL0_BB(regval)          (BIT(4) & ((uint32_t)(regval)<<4))
    146. 

  146. #define OB_BB_DISABLE              OBCTL0_BB(0)                   /*!< boot from bank0 */
    147. 

  147. #define OB_BB_ENABLE               OBCTL0_BB(1)                   /*!< boot from bank1 or bank0 if bank1 is void */
    148. 

  148. 

  149. /* option byte software/hardware free watch dog timer */  
    150. 

  150. #define OBCTL0_NWDG_HW(regval)     (BIT(5) & ((uint32_t)(regval))<< 5)
    151. 

  151. #define OB_FWDGT_SW                OBCTL0_NWDG_HW(1)              /*!< software free watchdog */
    152. 

  152. #define OB_FWDGT_HW                OBCTL0_NWDG_HW(0)              /*!< hardware free watchdog */
    153. 

  153. 

  154. /* option byte reset or not entering deep sleep mode */
    155. 

  155. #define OBCTL0_NRST_DPSLP(regval)  (BIT(6) & ((uint32_t)(regval))<< 6)
    156. 

  156. #define OB_DEEPSLEEP_NRST          OBCTL0_NRST_DPSLP(1)           /*!< no reset when entering deepsleep mode */
    157. 

  157. #define OB_DEEPSLEEP_RST           OBCTL0_NRST_DPSLP(0)           /*!< generate a reset instead of entering deepsleep mode */
    158. 

  158. 

  159. /* option byte reset or not entering standby mode */
    160. 

  160. #define OBCTL0_NRST_STDBY(regval)  (BIT(7) & ((uint32_t)(regval))<< 7)
    161. 

  161. #define OB_STDBY_NRST              OBCTL0_NRST_STDBY(1)           /*!< no reset when entering deepsleep mode */
    162. 

  162. #define OB_STDBY_RST               OBCTL0_NRST_STDBY(0)           /*!< generate a reset instead of entering standby mode */
    163. 

  163. 

  164. /* read protect configure */
    165. 

  165. #define FMC_NSPC                   ((uint8_t)0xAAU)               /*!< no security protection */
    166. 

  166. #define FMC_LSPC                   ((uint8_t)0xABU)               /*!< low security protection */
    167. 

  167. #define FMC_HSPC                   ((uint8_t)0xCCU)               /*!< high security protection */
    168. 

  168. 

  169. /* option bytes write protection */
    170. 

  170. #define OB_WP_0                    ((uint32_t)0x00000001U)        /*!< erase/program protection of sector 0  */
    171. 

  171. #define OB_WP_1                    ((uint32_t)0x00000002U)        /*!< erase/program protection of sector 1  */
    172. 

  172. #define OB_WP_2                    ((uint32_t)0x00000004U)        /*!< erase/program protection of sector 2  */
    173. 

  173. #define OB_WP_3                    ((uint32_t)0x00000008U)        /*!< erase/program protection of sector 3  */
    174. 

  174. #define OB_WP_4                    ((uint32_t)0x00000010U)        /*!< erase/program protection of sector 4  */
    175. 

  175. #define OB_WP_5                    ((uint32_t)0x00000020U)        /*!< erase/program protection of sector 5  */
    176. 

  176. #define OB_WP_6                    ((uint32_t)0x00000040U)        /*!< erase/program protection of sector 6  */
    177. 

  177. #define OB_WP_7                    ((uint32_t)0x00000080U)        /*!< erase/program protection of sector 7  */
    178. 

  178. #define OB_WP_8                    ((uint32_t)0x00000100U)        /*!< erase/program protection of sector 8  */
    179. 

  179. #define OB_WP_9                    ((uint32_t)0x00000200U)        /*!< erase/program protection of sector 9  */
    180. 

  180. #define OB_WP_10                   ((uint32_t)0x00000400U)        /*!< erase/program protection of sector 10 */
    181. 

  181. #define OB_WP_11                   ((uint32_t)0x00000800U)        /*!< erase/program protection of sector 11 */
    182. 

  182. #define OB_WP_12                   ((uint32_t)0x00000001U)        /*!< erase/program protection of sector 12 */
    183. 

  183. #define OB_WP_13                   ((uint32_t)0x00000002U)        /*!< erase/program protection of sector 13 */
    184. 

  184. #define OB_WP_14                   ((uint32_t)0x00000004U)        /*!< erase/program protection of sector 14 */
    185. 

  185. #define OB_WP_15                   ((uint32_t)0x00000008U)        /*!< erase/program protection of sector 15 */
    186. 

  186. #define OB_WP_16                   ((uint32_t)0x00000010U)        /*!< erase/program protection of sector 16 */
    187. 

  187. #define OB_WP_17                   ((uint32_t)0x00000020U)        /*!< erase/program protection of sector 17 */
    188. 

  188. #define OB_WP_18                   ((uint32_t)0x00000040U)        /*!< erase/program protection of sector 18 */
    189. 

  189. #define OB_WP_19                   ((uint32_t)0x00000080U)        /*!< erase/program protection of sector 19 */
    190. 

  190. #define OB_WP_20                   ((uint32_t)0x00000100U)        /*!< erase/program protection of sector 20 */
    191. 

  191. #define OB_WP_21                   ((uint32_t)0x00000200U)        /*!< erase/program protection of sector 21 */
    192. 

  192. #define OB_WP_22                   ((uint32_t)0x00000400U)        /*!< erase/program protection of sector 22 */
    193. 

  193. #define OB_WP_23_30                ((uint32_t)0x00000800U)        /*!< erase/program protection of sector 23~30 */
    194. 

  194. #define OB_WP_ALL                  ((uint32_t)0x00000FFFU)        /*!< erase/program protection of all sectors */
    195. 

  195. 

  196. /* option bytes D-bus read protection */
    197. 

  197. #define OB_DRP_0                   ((uint32_t)0x00000001U)        /*!< D-bus read protection protection of sector 0  */
    198. 

  198. #define OB_DRP_1                   ((uint32_t)0x00000002U)        /*!< D-bus read protection protection of sector 1  */
    199. 

  199. #define OB_DRP_2                   ((uint32_t)0x00000004U)        /*!< D-bus read protection protection of sector 2  */
    200. 

  200. #define OB_DRP_3                   ((uint32_t)0x00000008U)        /*!< D-bus read protection protection of sector 3  */
    201. 

  201. #define OB_DRP_4                   ((uint32_t)0x00000010U)        /*!< D-bus read protection protection of sector 4  */
    202. 

  202. #define OB_DRP_5                   ((uint32_t)0x00000020U)        /*!< D-bus read protection protection of sector 5  */
    203. 

  203. #define OB_DRP_6                   ((uint32_t)0x00000040U)        /*!< D-bus read protection protection of sector 6  */
    204. 

  204. #define OB_DRP_7                   ((uint32_t)0x00000080U)        /*!< D-bus read protection protection of sector 7  */
    205. 

  205. #define OB_DRP_8                   ((uint32_t)0x00000100U)        /*!< D-bus read protection protection of sector 8  */
    206. 

  206. #define OB_DRP_9                   ((uint32_t)0x00000200U)        /*!< D-bus read protection protection of sector 9  */
    207. 

  207. #define OB_DRP_10                  ((uint32_t)0x00000400U)        /*!< D-bus read protection protection of sector 10 */
    208. 

  208. #define OB_DRP_11                  ((uint32_t)0x00000800U)        /*!< D-bus read protection protection of sector 11 */
    209. 

  209. #define OB_DRP_12                  ((uint32_t)0x00000001U)        /*!< D-bus read protection protection of sector 12 */
    210. 

  210. #define OB_DRP_13                  ((uint32_t)0x00000002U)        /*!< D-bus read protection protection of sector 13 */
    211. 

  211. #define OB_DRP_14                  ((uint32_t)0x00000004U)        /*!< D-bus read protection protection of sector 14 */
    212. 

  212. #define OB_DRP_15                  ((uint32_t)0x00000008U)        /*!< D-bus read protection protection of sector 15 */
    213. 

  213. #define OB_DRP_16                  ((uint32_t)0x00000010U)        /*!< D-bus read protection protection of sector 16 */
    214. 

  214. #define OB_DRP_17                  ((uint32_t)0x00000020U)        /*!< D-bus read protection protection of sector 17 */
    215. 

  215. #define OB_DRP_18                  ((uint32_t)0x00000040U)        /*!< D-bus read protection protection of sector 18 */
    216. 

  216. #define OB_DRP_19                  ((uint32_t)0x00000080U)        /*!< D-bus read protection protection of sector 19 */
    217. 

  217. #define OB_DRP_20                  ((uint32_t)0x00000100U)        /*!< D-bus read protection protection of sector 20 */
    218. 

  218. #define OB_DRP_21                  ((uint32_t)0x00000200U)        /*!< D-bus read protection protection of sector 21 */
    219. 

  219. #define OB_DRP_22                  ((uint32_t)0x00000400U)        /*!< D-bus read protection protection of sector 22 */
    220. 

  220. #define OB_DRP_23_30               ((uint32_t)0x00000800U)        /*!< D-bus read protection protection of sector 23~30 */
    221. 

  221. #define OB_DRP_ALL                 ((uint32_t)0x00000FFFU)        /*!< D-bus read protection protection of all sectors */
    222. 

  222. 

  223. /* double banks or single bank selection when flash size is 1M bytes */  
    224. 

  224. #define OBCTL0_DBS(regval)         (BIT(30) & ((uint32_t)(regval)<<30))
    225. 

  225. #define OB_DBS_DISABLE             OBCTL0_DBS(0)                  /*!< single bank when flash size is 1M bytes */
    226. 

  226. #define OB_DBS_ENABLE              OBCTL0_DBS(1)                  /*!< double bank when flash size is 1M bytes */
    227. 

  227. 

  228. /* option bytes D-bus read protection mode */  
    229. 

  229. #define OBCTL0_DRP(regval)         (BIT(31) & ((uint32_t)(regval)<<31))
    230. 

  230. #define OB_DRP_DISABLE             OBCTL0_DRP(0)                  /*!< the WPx bits used as erase/program protection of each sector */
    231. 

  231. #define OB_DRP_ENABLE              OBCTL0_DRP(1)                  /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */
    232. 

  232. 

  233. /* FMC sectors */
    234. 

  234. #define CTL_SN(regval)             (BITS(3,7) & ((uint32_t)(regval))<< 3)
    235. 

  235. #define CTL_SECTOR_NUMBER_0        CTL_SN(0)                      /*!< sector 0   */
    236. 

  236. #define CTL_SECTOR_NUMBER_1        CTL_SN(1)                      /*!< sector 1   */
    237. 

  237. #define CTL_SECTOR_NUMBER_2        CTL_SN(2)                      /*!< sector 2   */
    238. 

  238. #define CTL_SECTOR_NUMBER_3        CTL_SN(3)                      /*!< sector 3   */
    239. 

  239. #define CTL_SECTOR_NUMBER_4        CTL_SN(4)                      /*!< sector 4   */
    240. 

  240. #define CTL_SECTOR_NUMBER_5        CTL_SN(5)                      /*!< sector 5   */
    241. 

  241. #define CTL_SECTOR_NUMBER_6        CTL_SN(6)                      /*!< sector 6   */
    242. 

  242. #define CTL_SECTOR_NUMBER_7        CTL_SN(7)                      /*!< sector 7   */
    243. 

  243. #define CTL_SECTOR_NUMBER_8        CTL_SN(8)                      /*!< sector 8   */
    244. 

  244. #define CTL_SECTOR_NUMBER_9        CTL_SN(9)                      /*!< sector 9   */
    245. 

  245. #define CTL_SECTOR_NUMBER_10       CTL_SN(10)                     /*!< sector 10  */
    246. 

  246. #define CTL_SECTOR_NUMBER_11       CTL_SN(11)                     /*!< sector 11  */
    247. 

  247. #define CTL_SECTOR_NUMBER_24       CTL_SN(12)                     /*!< sector 24  */
    248. 

  248. #define CTL_SECTOR_NUMBER_25       CTL_SN(13)                     /*!< sector 25  */
    249. 

  249. #define CTL_SECTOR_NUMBER_26       CTL_SN(14)                     /*!< sector 26  */
    250. 

  250. #define CTL_SECTOR_NUMBER_27       CTL_SN(15)                     /*!< sector 27  */
    251. 

  251. #define CTL_SECTOR_NUMBER_12       CTL_SN(16)                     /*!< sector 12  */
    252. 

  252. #define CTL_SECTOR_NUMBER_13       CTL_SN(17)                     /*!< sector 13  */
    253. 

  253. #define CTL_SECTOR_NUMBER_14       CTL_SN(18)                     /*!< sector 14  */
    254. 

  254. #define CTL_SECTOR_NUMBER_15       CTL_SN(19)                     /*!< sector 15  */
    255. 

  255. #define CTL_SECTOR_NUMBER_16       CTL_SN(20)                     /*!< sector 16  */
    256. 

  256. #define CTL_SECTOR_NUMBER_17       CTL_SN(21)                     /*!< sector 17  */
    257. 

  257. #define CTL_SECTOR_NUMBER_18       CTL_SN(22)                     /*!< sector 18  */
    258. 

  258. #define CTL_SECTOR_NUMBER_19       CTL_SN(23)                     /*!< sector 19  */
    259. 

  259. #define CTL_SECTOR_NUMBER_20       CTL_SN(24)                     /*!< sector 20  */
    260. 

  260. #define CTL_SECTOR_NUMBER_21       CTL_SN(25)                     /*!< sector 21  */
    261. 

  261. #define CTL_SECTOR_NUMBER_22       CTL_SN(26)                     /*!< sector 22  */
    262. 

  262. #define CTL_SECTOR_NUMBER_23       CTL_SN(27)                     /*!< sector 23  */
    263. 

  263. #define CTL_SECTOR_NUMBER_28       CTL_SN(28)                     /*!< sector 28  */
    264. 

  264. #define CTL_SECTOR_NUMBER_29       CTL_SN(29)                     /*!< sector 29  */
    265. 

  265. #define CTL_SECTOR_NUMBER_30       CTL_SN(30)                     /*!< sector 30  */
    266. 

  266. 

  267. /* FMC program size */ 
    268. 

  268. #define CTL_PSZ(regval)            (BITS(8,9) & ((uint32_t)(regval))<< 8)
    269. 

  269. #define CTL_PSZ_BYTE               CTL_PSZ(0)                     /*!< FMC program by byte access */
    270. 

  270. #define CTL_PSZ_HALF_WORD          CTL_PSZ(1)                     /*!< FMC program by half-word access */
    271. 

  271. #define CTL_PSZ_WORD               CTL_PSZ(2)                     /*!< FMC program by word access */
    272. 

  272. 

  273. /* FMC interrupt enable */
    274. 

  274. #define FMC_INTEN_END              ((uint32_t)0x01000000U)        /*!< enable FMC end of program interrupt */
    275. 

  275. #define FMC_INTEN_ERR              ((uint32_t)0x02000000U)        /*!< enable FMC error interrupt */
    276. 

  276. 

  277. /* FMC flags */
    278. 

  278. #define FMC_FLAG_END               ((uint32_t)0x00000001U)        /*!< FMC end of operation flag bit */
    279. 

  279. #define FMC_FLAG_OPERR             ((uint32_t)0x00000002U)        /*!< FMC operation error flag bit */
    280. 

  280. #define FMC_FLAG_WPERR             ((uint32_t)0x00000010U)        /*!< FMC erase/program protection error flag bit */
    281. 

  281. #define FMC_FLAG_PGMERR            ((uint32_t)0x00000040U)        /*!< FMC program size not match error flag bit */
    282. 

  282. #define FMC_FLAG_PGSERR            ((uint32_t)0x00000080U)        /*!< FMC program sequence error flag bit */
    283. 

  283. #define FMC_FLAG_RDDERR            ((uint32_t)0x00000100U)        /*!< FMC read D-bus protection error flag bit */
    284. 

  284. #define FMC_FLAG_BUSY              ((uint32_t)0x00010000U)        /*!< FMC busy flag */ 
    285. 

  285. 

  286. /* function declarations */
    287. 

  287. /* FMC main memory programming functions */
    288. 

  288. /* set the FMC wait state counter */
    289. 

  289. void fmc_wscnt_set(uint32_t wscnt);
    290. 

  290. /* unlock the main FMC operation */
    291. 

  291. void fmc_unlock(void);
    292. 

  292. /* lock the main FMC operation */
    293. 

  293. void fmc_lock(void);
    294. 

  294. /* FMC erase sector */
    295. 

  295. fmc_state_enum fmc_sector_erase(uint32_t fmc_sector);
    296. 

  296. /* FMC erase whole chip */
    297. 

  297. fmc_state_enum fmc_mass_erase(void);
    298. 

  298. /* FMC erase whole bank0 */
    299. 

  299. fmc_state_enum fmc_bank0_erase(void);
    300. 

  300. /* FMC erase whole bank1 */
    301. 

  301. fmc_state_enum fmc_bank1_erase(void);
    302. 

  302. /* FMC program a word at the corresponding address */
    303. 

  303. fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
    304. 

  304. /* FMC program a half word at the corresponding address */
    305. 

  305. fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
    306. 

  306. /* FMC program a byte at the corresponding address */
    307. 

  307. fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data);
    308. 

  308. 

  309. /* FMC option bytes programming functions */
    310. 

  310. /* unlock the option byte operation */
    311. 

  311. void ob_unlock(void);
    312. 

  312. /* lock the option byte operation */
    313. 

  313. void ob_lock(void);
    314. 

  314. /* send option byte change command */
    315. 

  315. void ob_start(void);
    316. 

  316. /* enable write protect */
    317. 

  317. void ob_write_protection0_enable(uint32_t ob_wp);
    318. 

  318. /* disable write protect */
    319. 

  319. void ob_write_protection0_disable(uint32_t ob_wp);
    320. 

  320. /* enable write protect */
    321. 

  321. void ob_write_protection1_enable(uint32_t ob_wp);
    322. 

  322. /* disable write protect */
    323. 

  323. void ob_write_protection1_disable(uint32_t ob_wp);
    324. 

  324. /* configure the erase/program protection mode */
    325. 

  325. void ob_drp_config(uint32_t ob_drp);
    326. 

  326. /* enable the erase/program protection mode */
    327. 

  327. void ob_drp0_enable(uint32_t ob_drp);
    328. 

  328. /* disable the erase/program protection mode */
    329. 

  329. void ob_drp0_disable(uint32_t ob_drp);
    330. 

  330. /* enable the erase/program protection mode */
    331. 

  331. void ob_drp1_enable(uint32_t ob_drp);
    332. 

  332. /* disable the erase/program protection mode */
    333. 

  333. void ob_drp1_disable(uint32_t ob_drp);
    334. 

  334. /* set the option byte security protection level  */
    335. 

  335. void ob_security_protection_config(uint8_t ob_spc);
    336. 

  336. /* write the FMC option byte user */
    337. 

  337. void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby);
    338. 

  338. /* option byte BOR threshold value */
    339. 

  339. void ob_user_bor_threshold(uint32_t ob_bor_th);
    340. 

  340. /* configure the boot mode */
    341. 

  341. void ob_boot_mode_config(uint32_t boot_mode);
    342. 

  342. /* get the FMC option byte user */
    343. 

  343. uint8_t ob_user_get(void);
    344. 

  344. /* get the FMC option byte write protection */
    345. 

  345. uint16_t ob_write_protection0_get(void);
    346. 

  346. /* get the FMC option byte write protection */
    347. 

  347. uint16_t ob_write_protection1_get(void);
    348. 

  348. /* get the FMC erase/program protection and D-bus read protection option bytes value */
    349. 

  349. uint16_t ob_drp0_get(void);
    350. 

  350. /* get the FMC erase/program protection and D-bus read protection option bytes value */
    351. 

  351. uint16_t ob_drp1_get(void);
    352. 

  352. /* get option byte security protection code value */
    353. 

  353. FlagStatus ob_spc_get(void);
    354. 

  354. /* get the FMC threshold value */
    355. 

  355. uint8_t ob_user_bor_threshold_get(void);
    356. 

  356. 

  357. /* FMC interrupts and flags management functions */
    358. 

  358. /* enable FMC interrupt */
    359. 

  359. void fmc_interrupt_enable(uint32_t fmc_int);
    360. 

  360. /* disable FMC interrupt */
    361. 

  361. void fmc_interrupt_disable(uint32_t fmc_int);
    362. 

  362. /* get flag set or reset */
    363. 

  363. FlagStatus fmc_flag_get(uint32_t fmc_flag);
    364. 

  364. /* clear the FMC pending flag */
    365. 

  365. void fmc_flag_clear(uint32_t fmc_flag);
    366. 

  366. /* return the FMC state */
    367. 

  367. fmc_state_enum fmc_state_get(void);
    368. 

  368. /* check FMC ready or not */
    369. 

  369. fmc_state_enum fmc_ready_wait(uint32_t count);
    370. 

  370. 

  371. #endif /* GD32F4XX_FMC_H */
    372.