gh_pmu_irt.h 62 KB

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  1. /*!
  2. *******************************************************************************
  3. **
  4. ** \file gh_pmu_irt.h
  5. **
  6. ** \brief Infrared Transmitter.
  7. **
  8. ** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
  9. **
  10. ** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
  11. ** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
  12. ** OMMISSIONS.
  13. **
  14. ** \note Do not modify this file as it is generated automatically.
  15. **
  16. ******************************************************************************/
  17. #ifndef _GH_PMU_IRT_H
  18. #define _GH_PMU_IRT_H
  19. #ifdef __LINUX__
  20. #include "reg4linux.h"
  21. #else
  22. #define FIO_ADDRESS(block,address) (address)
  23. #define FIO_MOFFSET(block,moffset) (moffset)
  24. #endif
  25. #ifndef __LINUX__
  26. #include "gtypes.h" /* global type definitions */
  27. #include "gh_lib_cfg.h" /* configuration */
  28. #endif
  29. #define GH_PMU_IRT_ENABLE_DEBUG_PRINT 0
  30. #ifdef __LINUX__
  31. #define GH_PMU_IRT_DEBUG_PRINT_FUNCTION printk
  32. #else
  33. #define GH_PMU_IRT_DEBUG_PRINT_FUNCTION printf
  34. #endif
  35. #ifndef __LINUX__
  36. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  37. #include <stdio.h>
  38. #endif
  39. #endif
  40. /* check configuration */
  41. #ifndef GH_INLINE_LEVEL
  42. #error "GH_INLINE_LEVEL is not defined!"
  43. #endif
  44. #if GH_INLINE_LEVEL > 2
  45. #error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
  46. #endif
  47. #ifndef GH_INLINE
  48. #error "GH_INLINE is not defined!"
  49. #endif
  50. /* disable inlining for debugging */
  51. #ifdef DEBUG
  52. #undef GH_INLINE_LEVEL
  53. #define GH_INLINE_LEVEL 0
  54. #endif
  55. /*----------------------------------------------------------------------------*/
  56. /* registers */
  57. /*----------------------------------------------------------------------------*/
  58. #define REG_PMU_IRT_READ FIO_ADDRESS(PMU_IRT,0x90082010) /* read/clear */
  59. #define REG_PMU_IRT_TRANSMIT0_0 FIO_ADDRESS(PMU_IRT,0x90082020) /* write */
  60. #define REG_PMU_IRT_TRANSMIT0_1 FIO_ADDRESS(PMU_IRT,0x90082024) /* write */
  61. #define REG_PMU_IRT_TRANSMIT0_2 FIO_ADDRESS(PMU_IRT,0x90082028) /* write */
  62. #define REG_PMU_IRT_TRANSMIT0_3 FIO_ADDRESS(PMU_IRT,0x9008202C) /* write */
  63. #define REG_PMU_IRT_TRANSMIT1_0 FIO_ADDRESS(PMU_IRT,0x90082030) /* write */
  64. #define REG_PMU_IRT_TRANSMIT1_1 FIO_ADDRESS(PMU_IRT,0x90082034) /* write */
  65. #define REG_PMU_IRT_TRANSMIT1_2 FIO_ADDRESS(PMU_IRT,0x90082038) /* write */
  66. #define REG_PMU_IRT_TRANSMIT1_3 FIO_ADDRESS(PMU_IRT,0x9008203C) /* write */
  67. #define REG_PMU_IRT_TRANSMIT2_0 FIO_ADDRESS(PMU_IRT,0x90082040) /* write */
  68. #define REG_PMU_IRT_TRANSMIT2_1 FIO_ADDRESS(PMU_IRT,0x90082044) /* write */
  69. #define REG_PMU_IRT_TRANSMIT2_2 FIO_ADDRESS(PMU_IRT,0x90082048) /* write */
  70. #define REG_PMU_IRT_TRANSMIT2_3 FIO_ADDRESS(PMU_IRT,0x9008204C) /* write */
  71. #define REG_PMU_IRT_TRANSMIT3_0 FIO_ADDRESS(PMU_IRT,0x90082050) /* write */
  72. #define REG_PMU_IRT_TRANSMIT3_1 FIO_ADDRESS(PMU_IRT,0x90082054) /* write */
  73. #define REG_PMU_IRT_TRANSMIT3_2 FIO_ADDRESS(PMU_IRT,0x90082058) /* write */
  74. #define REG_PMU_IRT_TRANSMIT3_3 FIO_ADDRESS(PMU_IRT,0x9008205C) /* write */
  75. #define REG_PMU_IRT_SENT_CLOCK_L FIO_ADDRESS(PMU_IRT,0x90082060) /* write */
  76. #define REG_PMU_IRT_SENT_CLOCK_H FIO_ADDRESS(PMU_IRT,0x90082064) /* write */
  77. #define REG_PMU_IRT_SHIFT_CLOCK FIO_ADDRESS(PMU_IRT,0x90082068) /* write */
  78. #define REG_PMU_IRT_SENT_CONF FIO_ADDRESS(PMU_IRT,0x9008206C) /* write */
  79. #define REG_PMU_IRT_COMPVALUE FIO_ADDRESS(PMU_IRT,0x90082070) /* write */
  80. #define REG_PMU_IRT_START FIO_ADDRESS(PMU_IRT,0x90082074) /* write */
  81. /*----------------------------------------------------------------------------*/
  82. /* bit group structures */
  83. /*----------------------------------------------------------------------------*/
  84. typedef union { /* PMU_IRT_Read */
  85. U32 all;
  86. struct {
  87. U32 irr_pulse01 : 2;
  88. U32 no_used : 4;
  89. U32 irt_transmit0 : 1;
  90. U32 irt_transmit1 : 1;
  91. U32 : 24;
  92. } bitc;
  93. } GH_PMU_IRT_READ_S;
  94. typedef union { /* PMU_IRT_Transmit0_0 */
  95. U32 all;
  96. struct {
  97. U32 value : 8;
  98. U32 : 24;
  99. } bitc;
  100. } GH_PMU_IRT_TRANSMIT0_0_S;
  101. typedef union { /* PMU_IRT_Transmit0_1 */
  102. U32 all;
  103. struct {
  104. U32 value : 8;
  105. U32 : 24;
  106. } bitc;
  107. } GH_PMU_IRT_TRANSMIT0_1_S;
  108. typedef union { /* PMU_IRT_Transmit0_2 */
  109. U32 all;
  110. struct {
  111. U32 value : 8;
  112. U32 : 24;
  113. } bitc;
  114. } GH_PMU_IRT_TRANSMIT0_2_S;
  115. typedef union { /* PMU_IRT_Transmit0_3 */
  116. U32 all;
  117. struct {
  118. U32 value : 8;
  119. U32 : 24;
  120. } bitc;
  121. } GH_PMU_IRT_TRANSMIT0_3_S;
  122. typedef union { /* PMU_IRT_Transmit1_0 */
  123. U32 all;
  124. struct {
  125. U32 value : 8;
  126. U32 : 24;
  127. } bitc;
  128. } GH_PMU_IRT_TRANSMIT1_0_S;
  129. typedef union { /* PMU_IRT_Transmit1_1 */
  130. U32 all;
  131. struct {
  132. U32 value : 8;
  133. U32 : 24;
  134. } bitc;
  135. } GH_PMU_IRT_TRANSMIT1_1_S;
  136. typedef union { /* PMU_IRT_Transmit1_2 */
  137. U32 all;
  138. struct {
  139. U32 value : 8;
  140. U32 : 24;
  141. } bitc;
  142. } GH_PMU_IRT_TRANSMIT1_2_S;
  143. typedef union { /* PMU_IRT_Transmit1_3 */
  144. U32 all;
  145. struct {
  146. U32 value : 8;
  147. U32 : 24;
  148. } bitc;
  149. } GH_PMU_IRT_TRANSMIT1_3_S;
  150. typedef union { /* PMU_IRT_Transmit2_0 */
  151. U32 all;
  152. struct {
  153. U32 value : 8;
  154. U32 : 24;
  155. } bitc;
  156. } GH_PMU_IRT_TRANSMIT2_0_S;
  157. typedef union { /* PMU_IRT_Transmit2_1 */
  158. U32 all;
  159. struct {
  160. U32 value : 8;
  161. U32 : 24;
  162. } bitc;
  163. } GH_PMU_IRT_TRANSMIT2_1_S;
  164. typedef union { /* PMU_IRT_Transmit2_2 */
  165. U32 all;
  166. struct {
  167. U32 value : 8;
  168. U32 : 24;
  169. } bitc;
  170. } GH_PMU_IRT_TRANSMIT2_2_S;
  171. typedef union { /* PMU_IRT_Transmit2_3 */
  172. U32 all;
  173. struct {
  174. U32 value : 8;
  175. U32 : 24;
  176. } bitc;
  177. } GH_PMU_IRT_TRANSMIT2_3_S;
  178. typedef union { /* PMU_IRT_Transmit3_0 */
  179. U32 all;
  180. struct {
  181. U32 value : 8;
  182. U32 : 24;
  183. } bitc;
  184. } GH_PMU_IRT_TRANSMIT3_0_S;
  185. typedef union { /* PMU_IRT_Transmit3_1 */
  186. U32 all;
  187. struct {
  188. U32 value : 8;
  189. U32 : 24;
  190. } bitc;
  191. } GH_PMU_IRT_TRANSMIT3_1_S;
  192. typedef union { /* PMU_IRT_Transmit3_2 */
  193. U32 all;
  194. struct {
  195. U32 value : 8;
  196. U32 : 24;
  197. } bitc;
  198. } GH_PMU_IRT_TRANSMIT3_2_S;
  199. typedef union { /* PMU_IRT_Transmit3_3 */
  200. U32 all;
  201. struct {
  202. U32 value : 8;
  203. U32 : 24;
  204. } bitc;
  205. } GH_PMU_IRT_TRANSMIT3_3_S;
  206. typedef union { /* PMU_IRT_Sent_Clock_l */
  207. U32 all;
  208. struct {
  209. U32 value : 8;
  210. U32 : 24;
  211. } bitc;
  212. } GH_PMU_IRT_SENT_CLOCK_L_S;
  213. typedef union { /* PMU_IRT_Sent_Clock_h */
  214. U32 all;
  215. struct {
  216. U32 value : 8;
  217. U32 : 24;
  218. } bitc;
  219. } GH_PMU_IRT_SENT_CLOCK_H_S;
  220. typedef union { /* PMU_IRT_Shift_Clock */
  221. U32 all;
  222. struct {
  223. U32 value : 8;
  224. U32 : 24;
  225. } bitc;
  226. } GH_PMU_IRT_SHIFT_CLOCK_S;
  227. typedef union { /* PMU_IRT_Sent_Conf */
  228. U32 all;
  229. struct {
  230. U32 en_tx_irq : 1;
  231. U32 mode : 1;
  232. U32 : 30;
  233. } bitc;
  234. } GH_PMU_IRT_SENT_CONF_S;
  235. typedef union { /* PMU_IRT_Compvalue */
  236. U32 all;
  237. struct {
  238. U32 value : 8;
  239. U32 : 24;
  240. } bitc;
  241. } GH_PMU_IRT_COMPVALUE_S;
  242. typedef union { /* PMU_IRT_Start */
  243. U32 all;
  244. struct {
  245. U32 start_tx : 1;
  246. U32 : 31;
  247. } bitc;
  248. } GH_PMU_IRT_START_S;
  249. /*----------------------------------------------------------------------------*/
  250. /* mirror variables */
  251. /*----------------------------------------------------------------------------*/
  252. extern GH_PMU_IRT_READ_S m_pmu_irt_read;
  253. extern GH_PMU_IRT_TRANSMIT0_0_S m_pmu_irt_transmit0_0;
  254. extern GH_PMU_IRT_TRANSMIT0_1_S m_pmu_irt_transmit0_1;
  255. extern GH_PMU_IRT_TRANSMIT0_2_S m_pmu_irt_transmit0_2;
  256. extern GH_PMU_IRT_TRANSMIT0_3_S m_pmu_irt_transmit0_3;
  257. extern GH_PMU_IRT_TRANSMIT1_0_S m_pmu_irt_transmit1_0;
  258. extern GH_PMU_IRT_TRANSMIT1_1_S m_pmu_irt_transmit1_1;
  259. extern GH_PMU_IRT_TRANSMIT1_2_S m_pmu_irt_transmit1_2;
  260. extern GH_PMU_IRT_TRANSMIT1_3_S m_pmu_irt_transmit1_3;
  261. extern GH_PMU_IRT_TRANSMIT2_0_S m_pmu_irt_transmit2_0;
  262. extern GH_PMU_IRT_TRANSMIT2_1_S m_pmu_irt_transmit2_1;
  263. extern GH_PMU_IRT_TRANSMIT2_2_S m_pmu_irt_transmit2_2;
  264. extern GH_PMU_IRT_TRANSMIT2_3_S m_pmu_irt_transmit2_3;
  265. extern GH_PMU_IRT_TRANSMIT3_0_S m_pmu_irt_transmit3_0;
  266. extern GH_PMU_IRT_TRANSMIT3_1_S m_pmu_irt_transmit3_1;
  267. extern GH_PMU_IRT_TRANSMIT3_2_S m_pmu_irt_transmit3_2;
  268. extern GH_PMU_IRT_TRANSMIT3_3_S m_pmu_irt_transmit3_3;
  269. extern GH_PMU_IRT_SENT_CLOCK_L_S m_pmu_irt_sent_clock_l;
  270. extern GH_PMU_IRT_SENT_CLOCK_H_S m_pmu_irt_sent_clock_h;
  271. extern GH_PMU_IRT_SHIFT_CLOCK_S m_pmu_irt_shift_clock;
  272. extern GH_PMU_IRT_SENT_CONF_S m_pmu_irt_sent_conf;
  273. extern GH_PMU_IRT_COMPVALUE_S m_pmu_irt_compvalue;
  274. extern GH_PMU_IRT_START_S m_pmu_irt_start;
  275. #ifdef __cplusplus
  276. extern "C" {
  277. #endif
  278. /*----------------------------------------------------------------------------*/
  279. /* register PMU_IRT_Read (read/clear) */
  280. /*----------------------------------------------------------------------------*/
  281. #if GH_INLINE_LEVEL < 2
  282. /*! \brief Writes the register 'PMU_IRT_Read'. */
  283. U32 GH_PMU_IRT_get_Read(void);
  284. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Read'. */
  285. U32 GH_PMU_IRT_getm_Read(void);
  286. /*! \brief Reads the bit group 'IRR_PULSE01' from the mirror variable of register 'PMU_IRT_Read'. */
  287. U8 GH_PMU_IRT_getm_Read_IRR_PULSE01(void);
  288. /*! \brief Reads the bit group 'NO_USED' from the mirror variable of register 'PMU_IRT_Read'. */
  289. U8 GH_PMU_IRT_getm_Read_NO_USED(void);
  290. /*! \brief Reads the bit group 'IRT_TRANSMIT0' from the mirror variable of register 'PMU_IRT_Read'. */
  291. U8 GH_PMU_IRT_getm_Read_IRT_TRANSMIT0(void);
  292. /*! \brief Reads the bit group 'IRT_TRANSMIT1' from the mirror variable of register 'PMU_IRT_Read'. */
  293. U8 GH_PMU_IRT_getm_Read_IRT_TRANSMIT1(void);
  294. #else /* GH_INLINE_LEVEL < 2 */
  295. GH_INLINE U32 GH_PMU_IRT_get_Read(void)
  296. {
  297. m_pmu_irt_read.all = *(volatile U32 *)REG_PMU_IRT_READ;
  298. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  299. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_PMU_IRT_get_Read] --> 0x%08x\n",
  300. REG_PMU_IRT_READ,m_pmu_irt_read.all );
  301. #endif
  302. return m_pmu_irt_read.all;
  303. }
  304. GH_INLINE U32 GH_PMU_IRT_getm_Read(void)
  305. {
  306. return m_pmu_irt_read.all;
  307. }
  308. GH_INLINE U8 GH_PMU_IRT_getm_Read_IRR_PULSE01(void)
  309. {
  310. return m_pmu_irt_read.bitc.irr_pulse01;
  311. }
  312. GH_INLINE U8 GH_PMU_IRT_getm_Read_NO_USED(void)
  313. {
  314. return m_pmu_irt_read.bitc.no_used;
  315. }
  316. GH_INLINE U8 GH_PMU_IRT_getm_Read_IRT_TRANSMIT0(void)
  317. {
  318. return m_pmu_irt_read.bitc.irt_transmit0;
  319. }
  320. GH_INLINE U8 GH_PMU_IRT_getm_Read_IRT_TRANSMIT1(void)
  321. {
  322. return m_pmu_irt_read.bitc.irt_transmit1;
  323. }
  324. #endif /* GH_INLINE_LEVEL < 2 */
  325. /*----------------------------------------------------------------------------*/
  326. /* register PMU_IRT_Transmit0_0 (write) */
  327. /*----------------------------------------------------------------------------*/
  328. #if GH_INLINE_LEVEL < 2
  329. /*! \brief Writes the register 'PMU_IRT_Transmit0_0'. */
  330. void GH_PMU_IRT_set_Transmit0_0(U32 data);
  331. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit0_0'. */
  332. U32 GH_PMU_IRT_getm_Transmit0_0(void);
  333. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit0_0'. */
  334. void GH_PMU_IRT_set_Transmit0_0_VALUE(U8 data);
  335. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit0_0'. */
  336. U8 GH_PMU_IRT_getm_Transmit0_0_VALUE(void);
  337. #else /* GH_INLINE_LEVEL < 2 */
  338. GH_INLINE void GH_PMU_IRT_set_Transmit0_0(U32 data)
  339. {
  340. m_pmu_irt_transmit0_0.all = data;
  341. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_0 = data;
  342. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  343. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_0] <-- 0x%08x\n",
  344. REG_PMU_IRT_TRANSMIT0_0,data,data);
  345. #endif
  346. }
  347. GH_INLINE U32 GH_PMU_IRT_getm_Transmit0_0(void)
  348. {
  349. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  350. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_0] --> 0x%08x\n",
  351. m_pmu_irt_transmit0_0.all);
  352. #endif
  353. return m_pmu_irt_transmit0_0.all;
  354. }
  355. GH_INLINE void GH_PMU_IRT_set_Transmit0_0_VALUE(U8 data)
  356. {
  357. m_pmu_irt_transmit0_0.bitc.value = data;
  358. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_0 = m_pmu_irt_transmit0_0.all;
  359. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  360. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_0_VALUE] <-- 0x%08x\n",
  361. REG_PMU_IRT_TRANSMIT0_0,m_pmu_irt_transmit0_0.all,m_pmu_irt_transmit0_0.all);
  362. #endif
  363. }
  364. GH_INLINE U8 GH_PMU_IRT_getm_Transmit0_0_VALUE(void)
  365. {
  366. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  367. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_0_VALUE] --> 0x%08x\n",
  368. m_pmu_irt_transmit0_0.bitc.value);
  369. #endif
  370. return m_pmu_irt_transmit0_0.bitc.value;
  371. }
  372. #endif /* GH_INLINE_LEVEL < 2 */
  373. /*----------------------------------------------------------------------------*/
  374. /* register PMU_IRT_Transmit0_1 (write) */
  375. /*----------------------------------------------------------------------------*/
  376. #if GH_INLINE_LEVEL < 2
  377. /*! \brief Writes the register 'PMU_IRT_Transmit0_1'. */
  378. void GH_PMU_IRT_set_Transmit0_1(U32 data);
  379. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit0_1'. */
  380. U32 GH_PMU_IRT_getm_Transmit0_1(void);
  381. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit0_1'. */
  382. void GH_PMU_IRT_set_Transmit0_1_VALUE(U8 data);
  383. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit0_1'. */
  384. U8 GH_PMU_IRT_getm_Transmit0_1_VALUE(void);
  385. #else /* GH_INLINE_LEVEL < 2 */
  386. GH_INLINE void GH_PMU_IRT_set_Transmit0_1(U32 data)
  387. {
  388. m_pmu_irt_transmit0_1.all = data;
  389. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_1 = data;
  390. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  391. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_1] <-- 0x%08x\n",
  392. REG_PMU_IRT_TRANSMIT0_1,data,data);
  393. #endif
  394. }
  395. GH_INLINE U32 GH_PMU_IRT_getm_Transmit0_1(void)
  396. {
  397. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  398. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_1] --> 0x%08x\n",
  399. m_pmu_irt_transmit0_1.all);
  400. #endif
  401. return m_pmu_irt_transmit0_1.all;
  402. }
  403. GH_INLINE void GH_PMU_IRT_set_Transmit0_1_VALUE(U8 data)
  404. {
  405. m_pmu_irt_transmit0_1.bitc.value = data;
  406. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_1 = m_pmu_irt_transmit0_1.all;
  407. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  408. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_1_VALUE] <-- 0x%08x\n",
  409. REG_PMU_IRT_TRANSMIT0_1,m_pmu_irt_transmit0_1.all,m_pmu_irt_transmit0_1.all);
  410. #endif
  411. }
  412. GH_INLINE U8 GH_PMU_IRT_getm_Transmit0_1_VALUE(void)
  413. {
  414. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  415. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_1_VALUE] --> 0x%08x\n",
  416. m_pmu_irt_transmit0_1.bitc.value);
  417. #endif
  418. return m_pmu_irt_transmit0_1.bitc.value;
  419. }
  420. #endif /* GH_INLINE_LEVEL < 2 */
  421. /*----------------------------------------------------------------------------*/
  422. /* register PMU_IRT_Transmit0_2 (write) */
  423. /*----------------------------------------------------------------------------*/
  424. #if GH_INLINE_LEVEL < 2
  425. /*! \brief Writes the register 'PMU_IRT_Transmit0_2'. */
  426. void GH_PMU_IRT_set_Transmit0_2(U32 data);
  427. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit0_2'. */
  428. U32 GH_PMU_IRT_getm_Transmit0_2(void);
  429. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit0_2'. */
  430. void GH_PMU_IRT_set_Transmit0_2_VALUE(U8 data);
  431. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit0_2'. */
  432. U8 GH_PMU_IRT_getm_Transmit0_2_VALUE(void);
  433. #else /* GH_INLINE_LEVEL < 2 */
  434. GH_INLINE void GH_PMU_IRT_set_Transmit0_2(U32 data)
  435. {
  436. m_pmu_irt_transmit0_2.all = data;
  437. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_2 = data;
  438. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  439. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_2] <-- 0x%08x\n",
  440. REG_PMU_IRT_TRANSMIT0_2,data,data);
  441. #endif
  442. }
  443. GH_INLINE U32 GH_PMU_IRT_getm_Transmit0_2(void)
  444. {
  445. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  446. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_2] --> 0x%08x\n",
  447. m_pmu_irt_transmit0_2.all);
  448. #endif
  449. return m_pmu_irt_transmit0_2.all;
  450. }
  451. GH_INLINE void GH_PMU_IRT_set_Transmit0_2_VALUE(U8 data)
  452. {
  453. m_pmu_irt_transmit0_2.bitc.value = data;
  454. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_2 = m_pmu_irt_transmit0_2.all;
  455. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  456. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_2_VALUE] <-- 0x%08x\n",
  457. REG_PMU_IRT_TRANSMIT0_2,m_pmu_irt_transmit0_2.all,m_pmu_irt_transmit0_2.all);
  458. #endif
  459. }
  460. GH_INLINE U8 GH_PMU_IRT_getm_Transmit0_2_VALUE(void)
  461. {
  462. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  463. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_2_VALUE] --> 0x%08x\n",
  464. m_pmu_irt_transmit0_2.bitc.value);
  465. #endif
  466. return m_pmu_irt_transmit0_2.bitc.value;
  467. }
  468. #endif /* GH_INLINE_LEVEL < 2 */
  469. /*----------------------------------------------------------------------------*/
  470. /* register PMU_IRT_Transmit0_3 (write) */
  471. /*----------------------------------------------------------------------------*/
  472. #if GH_INLINE_LEVEL < 2
  473. /*! \brief Writes the register 'PMU_IRT_Transmit0_3'. */
  474. void GH_PMU_IRT_set_Transmit0_3(U32 data);
  475. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit0_3'. */
  476. U32 GH_PMU_IRT_getm_Transmit0_3(void);
  477. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit0_3'. */
  478. void GH_PMU_IRT_set_Transmit0_3_VALUE(U8 data);
  479. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit0_3'. */
  480. U8 GH_PMU_IRT_getm_Transmit0_3_VALUE(void);
  481. #else /* GH_INLINE_LEVEL < 2 */
  482. GH_INLINE void GH_PMU_IRT_set_Transmit0_3(U32 data)
  483. {
  484. m_pmu_irt_transmit0_3.all = data;
  485. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_3 = data;
  486. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  487. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_3] <-- 0x%08x\n",
  488. REG_PMU_IRT_TRANSMIT0_3,data,data);
  489. #endif
  490. }
  491. GH_INLINE U32 GH_PMU_IRT_getm_Transmit0_3(void)
  492. {
  493. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  494. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_3] --> 0x%08x\n",
  495. m_pmu_irt_transmit0_3.all);
  496. #endif
  497. return m_pmu_irt_transmit0_3.all;
  498. }
  499. GH_INLINE void GH_PMU_IRT_set_Transmit0_3_VALUE(U8 data)
  500. {
  501. m_pmu_irt_transmit0_3.bitc.value = data;
  502. *(volatile U32 *)REG_PMU_IRT_TRANSMIT0_3 = m_pmu_irt_transmit0_3.all;
  503. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  504. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit0_3_VALUE] <-- 0x%08x\n",
  505. REG_PMU_IRT_TRANSMIT0_3,m_pmu_irt_transmit0_3.all,m_pmu_irt_transmit0_3.all);
  506. #endif
  507. }
  508. GH_INLINE U8 GH_PMU_IRT_getm_Transmit0_3_VALUE(void)
  509. {
  510. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  511. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit0_3_VALUE] --> 0x%08x\n",
  512. m_pmu_irt_transmit0_3.bitc.value);
  513. #endif
  514. return m_pmu_irt_transmit0_3.bitc.value;
  515. }
  516. #endif /* GH_INLINE_LEVEL < 2 */
  517. /*----------------------------------------------------------------------------*/
  518. /* register PMU_IRT_Transmit1_0 (write) */
  519. /*----------------------------------------------------------------------------*/
  520. #if GH_INLINE_LEVEL < 2
  521. /*! \brief Writes the register 'PMU_IRT_Transmit1_0'. */
  522. void GH_PMU_IRT_set_Transmit1_0(U32 data);
  523. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit1_0'. */
  524. U32 GH_PMU_IRT_getm_Transmit1_0(void);
  525. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit1_0'. */
  526. void GH_PMU_IRT_set_Transmit1_0_VALUE(U8 data);
  527. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit1_0'. */
  528. U8 GH_PMU_IRT_getm_Transmit1_0_VALUE(void);
  529. #else /* GH_INLINE_LEVEL < 2 */
  530. GH_INLINE void GH_PMU_IRT_set_Transmit1_0(U32 data)
  531. {
  532. m_pmu_irt_transmit1_0.all = data;
  533. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_0 = data;
  534. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  535. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_0] <-- 0x%08x\n",
  536. REG_PMU_IRT_TRANSMIT1_0,data,data);
  537. #endif
  538. }
  539. GH_INLINE U32 GH_PMU_IRT_getm_Transmit1_0(void)
  540. {
  541. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  542. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_0] --> 0x%08x\n",
  543. m_pmu_irt_transmit1_0.all);
  544. #endif
  545. return m_pmu_irt_transmit1_0.all;
  546. }
  547. GH_INLINE void GH_PMU_IRT_set_Transmit1_0_VALUE(U8 data)
  548. {
  549. m_pmu_irt_transmit1_0.bitc.value = data;
  550. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_0 = m_pmu_irt_transmit1_0.all;
  551. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  552. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_0_VALUE] <-- 0x%08x\n",
  553. REG_PMU_IRT_TRANSMIT1_0,m_pmu_irt_transmit1_0.all,m_pmu_irt_transmit1_0.all);
  554. #endif
  555. }
  556. GH_INLINE U8 GH_PMU_IRT_getm_Transmit1_0_VALUE(void)
  557. {
  558. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  559. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_0_VALUE] --> 0x%08x\n",
  560. m_pmu_irt_transmit1_0.bitc.value);
  561. #endif
  562. return m_pmu_irt_transmit1_0.bitc.value;
  563. }
  564. #endif /* GH_INLINE_LEVEL < 2 */
  565. /*----------------------------------------------------------------------------*/
  566. /* register PMU_IRT_Transmit1_1 (write) */
  567. /*----------------------------------------------------------------------------*/
  568. #if GH_INLINE_LEVEL < 2
  569. /*! \brief Writes the register 'PMU_IRT_Transmit1_1'. */
  570. void GH_PMU_IRT_set_Transmit1_1(U32 data);
  571. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit1_1'. */
  572. U32 GH_PMU_IRT_getm_Transmit1_1(void);
  573. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit1_1'. */
  574. void GH_PMU_IRT_set_Transmit1_1_VALUE(U8 data);
  575. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit1_1'. */
  576. U8 GH_PMU_IRT_getm_Transmit1_1_VALUE(void);
  577. #else /* GH_INLINE_LEVEL < 2 */
  578. GH_INLINE void GH_PMU_IRT_set_Transmit1_1(U32 data)
  579. {
  580. m_pmu_irt_transmit1_1.all = data;
  581. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_1 = data;
  582. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  583. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_1] <-- 0x%08x\n",
  584. REG_PMU_IRT_TRANSMIT1_1,data,data);
  585. #endif
  586. }
  587. GH_INLINE U32 GH_PMU_IRT_getm_Transmit1_1(void)
  588. {
  589. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  590. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_1] --> 0x%08x\n",
  591. m_pmu_irt_transmit1_1.all);
  592. #endif
  593. return m_pmu_irt_transmit1_1.all;
  594. }
  595. GH_INLINE void GH_PMU_IRT_set_Transmit1_1_VALUE(U8 data)
  596. {
  597. m_pmu_irt_transmit1_1.bitc.value = data;
  598. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_1 = m_pmu_irt_transmit1_1.all;
  599. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  600. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_1_VALUE] <-- 0x%08x\n",
  601. REG_PMU_IRT_TRANSMIT1_1,m_pmu_irt_transmit1_1.all,m_pmu_irt_transmit1_1.all);
  602. #endif
  603. }
  604. GH_INLINE U8 GH_PMU_IRT_getm_Transmit1_1_VALUE(void)
  605. {
  606. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  607. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_1_VALUE] --> 0x%08x\n",
  608. m_pmu_irt_transmit1_1.bitc.value);
  609. #endif
  610. return m_pmu_irt_transmit1_1.bitc.value;
  611. }
  612. #endif /* GH_INLINE_LEVEL < 2 */
  613. /*----------------------------------------------------------------------------*/
  614. /* register PMU_IRT_Transmit1_2 (write) */
  615. /*----------------------------------------------------------------------------*/
  616. #if GH_INLINE_LEVEL < 2
  617. /*! \brief Writes the register 'PMU_IRT_Transmit1_2'. */
  618. void GH_PMU_IRT_set_Transmit1_2(U32 data);
  619. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit1_2'. */
  620. U32 GH_PMU_IRT_getm_Transmit1_2(void);
  621. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit1_2'. */
  622. void GH_PMU_IRT_set_Transmit1_2_VALUE(U8 data);
  623. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit1_2'. */
  624. U8 GH_PMU_IRT_getm_Transmit1_2_VALUE(void);
  625. #else /* GH_INLINE_LEVEL < 2 */
  626. GH_INLINE void GH_PMU_IRT_set_Transmit1_2(U32 data)
  627. {
  628. m_pmu_irt_transmit1_2.all = data;
  629. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_2 = data;
  630. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  631. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_2] <-- 0x%08x\n",
  632. REG_PMU_IRT_TRANSMIT1_2,data,data);
  633. #endif
  634. }
  635. GH_INLINE U32 GH_PMU_IRT_getm_Transmit1_2(void)
  636. {
  637. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  638. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_2] --> 0x%08x\n",
  639. m_pmu_irt_transmit1_2.all);
  640. #endif
  641. return m_pmu_irt_transmit1_2.all;
  642. }
  643. GH_INLINE void GH_PMU_IRT_set_Transmit1_2_VALUE(U8 data)
  644. {
  645. m_pmu_irt_transmit1_2.bitc.value = data;
  646. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_2 = m_pmu_irt_transmit1_2.all;
  647. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  648. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_2_VALUE] <-- 0x%08x\n",
  649. REG_PMU_IRT_TRANSMIT1_2,m_pmu_irt_transmit1_2.all,m_pmu_irt_transmit1_2.all);
  650. #endif
  651. }
  652. GH_INLINE U8 GH_PMU_IRT_getm_Transmit1_2_VALUE(void)
  653. {
  654. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  655. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_2_VALUE] --> 0x%08x\n",
  656. m_pmu_irt_transmit1_2.bitc.value);
  657. #endif
  658. return m_pmu_irt_transmit1_2.bitc.value;
  659. }
  660. #endif /* GH_INLINE_LEVEL < 2 */
  661. /*----------------------------------------------------------------------------*/
  662. /* register PMU_IRT_Transmit1_3 (write) */
  663. /*----------------------------------------------------------------------------*/
  664. #if GH_INLINE_LEVEL < 2
  665. /*! \brief Writes the register 'PMU_IRT_Transmit1_3'. */
  666. void GH_PMU_IRT_set_Transmit1_3(U32 data);
  667. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit1_3'. */
  668. U32 GH_PMU_IRT_getm_Transmit1_3(void);
  669. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit1_3'. */
  670. void GH_PMU_IRT_set_Transmit1_3_VALUE(U8 data);
  671. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit1_3'. */
  672. U8 GH_PMU_IRT_getm_Transmit1_3_VALUE(void);
  673. #else /* GH_INLINE_LEVEL < 2 */
  674. GH_INLINE void GH_PMU_IRT_set_Transmit1_3(U32 data)
  675. {
  676. m_pmu_irt_transmit1_3.all = data;
  677. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_3 = data;
  678. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  679. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_3] <-- 0x%08x\n",
  680. REG_PMU_IRT_TRANSMIT1_3,data,data);
  681. #endif
  682. }
  683. GH_INLINE U32 GH_PMU_IRT_getm_Transmit1_3(void)
  684. {
  685. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  686. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_3] --> 0x%08x\n",
  687. m_pmu_irt_transmit1_3.all);
  688. #endif
  689. return m_pmu_irt_transmit1_3.all;
  690. }
  691. GH_INLINE void GH_PMU_IRT_set_Transmit1_3_VALUE(U8 data)
  692. {
  693. m_pmu_irt_transmit1_3.bitc.value = data;
  694. *(volatile U32 *)REG_PMU_IRT_TRANSMIT1_3 = m_pmu_irt_transmit1_3.all;
  695. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  696. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit1_3_VALUE] <-- 0x%08x\n",
  697. REG_PMU_IRT_TRANSMIT1_3,m_pmu_irt_transmit1_3.all,m_pmu_irt_transmit1_3.all);
  698. #endif
  699. }
  700. GH_INLINE U8 GH_PMU_IRT_getm_Transmit1_3_VALUE(void)
  701. {
  702. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  703. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit1_3_VALUE] --> 0x%08x\n",
  704. m_pmu_irt_transmit1_3.bitc.value);
  705. #endif
  706. return m_pmu_irt_transmit1_3.bitc.value;
  707. }
  708. #endif /* GH_INLINE_LEVEL < 2 */
  709. /*----------------------------------------------------------------------------*/
  710. /* register PMU_IRT_Transmit2_0 (write) */
  711. /*----------------------------------------------------------------------------*/
  712. #if GH_INLINE_LEVEL < 2
  713. /*! \brief Writes the register 'PMU_IRT_Transmit2_0'. */
  714. void GH_PMU_IRT_set_Transmit2_0(U32 data);
  715. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit2_0'. */
  716. U32 GH_PMU_IRT_getm_Transmit2_0(void);
  717. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit2_0'. */
  718. void GH_PMU_IRT_set_Transmit2_0_VALUE(U8 data);
  719. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit2_0'. */
  720. U8 GH_PMU_IRT_getm_Transmit2_0_VALUE(void);
  721. #else /* GH_INLINE_LEVEL < 2 */
  722. GH_INLINE void GH_PMU_IRT_set_Transmit2_0(U32 data)
  723. {
  724. m_pmu_irt_transmit2_0.all = data;
  725. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_0 = data;
  726. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  727. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_0] <-- 0x%08x\n",
  728. REG_PMU_IRT_TRANSMIT2_0,data,data);
  729. #endif
  730. }
  731. GH_INLINE U32 GH_PMU_IRT_getm_Transmit2_0(void)
  732. {
  733. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  734. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_0] --> 0x%08x\n",
  735. m_pmu_irt_transmit2_0.all);
  736. #endif
  737. return m_pmu_irt_transmit2_0.all;
  738. }
  739. GH_INLINE void GH_PMU_IRT_set_Transmit2_0_VALUE(U8 data)
  740. {
  741. m_pmu_irt_transmit2_0.bitc.value = data;
  742. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_0 = m_pmu_irt_transmit2_0.all;
  743. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  744. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_0_VALUE] <-- 0x%08x\n",
  745. REG_PMU_IRT_TRANSMIT2_0,m_pmu_irt_transmit2_0.all,m_pmu_irt_transmit2_0.all);
  746. #endif
  747. }
  748. GH_INLINE U8 GH_PMU_IRT_getm_Transmit2_0_VALUE(void)
  749. {
  750. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  751. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_0_VALUE] --> 0x%08x\n",
  752. m_pmu_irt_transmit2_0.bitc.value);
  753. #endif
  754. return m_pmu_irt_transmit2_0.bitc.value;
  755. }
  756. #endif /* GH_INLINE_LEVEL < 2 */
  757. /*----------------------------------------------------------------------------*/
  758. /* register PMU_IRT_Transmit2_1 (write) */
  759. /*----------------------------------------------------------------------------*/
  760. #if GH_INLINE_LEVEL < 2
  761. /*! \brief Writes the register 'PMU_IRT_Transmit2_1'. */
  762. void GH_PMU_IRT_set_Transmit2_1(U32 data);
  763. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit2_1'. */
  764. U32 GH_PMU_IRT_getm_Transmit2_1(void);
  765. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit2_1'. */
  766. void GH_PMU_IRT_set_Transmit2_1_VALUE(U8 data);
  767. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit2_1'. */
  768. U8 GH_PMU_IRT_getm_Transmit2_1_VALUE(void);
  769. #else /* GH_INLINE_LEVEL < 2 */
  770. GH_INLINE void GH_PMU_IRT_set_Transmit2_1(U32 data)
  771. {
  772. m_pmu_irt_transmit2_1.all = data;
  773. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_1 = data;
  774. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  775. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_1] <-- 0x%08x\n",
  776. REG_PMU_IRT_TRANSMIT2_1,data,data);
  777. #endif
  778. }
  779. GH_INLINE U32 GH_PMU_IRT_getm_Transmit2_1(void)
  780. {
  781. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  782. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_1] --> 0x%08x\n",
  783. m_pmu_irt_transmit2_1.all);
  784. #endif
  785. return m_pmu_irt_transmit2_1.all;
  786. }
  787. GH_INLINE void GH_PMU_IRT_set_Transmit2_1_VALUE(U8 data)
  788. {
  789. m_pmu_irt_transmit2_1.bitc.value = data;
  790. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_1 = m_pmu_irt_transmit2_1.all;
  791. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  792. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_1_VALUE] <-- 0x%08x\n",
  793. REG_PMU_IRT_TRANSMIT2_1,m_pmu_irt_transmit2_1.all,m_pmu_irt_transmit2_1.all);
  794. #endif
  795. }
  796. GH_INLINE U8 GH_PMU_IRT_getm_Transmit2_1_VALUE(void)
  797. {
  798. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  799. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_1_VALUE] --> 0x%08x\n",
  800. m_pmu_irt_transmit2_1.bitc.value);
  801. #endif
  802. return m_pmu_irt_transmit2_1.bitc.value;
  803. }
  804. #endif /* GH_INLINE_LEVEL < 2 */
  805. /*----------------------------------------------------------------------------*/
  806. /* register PMU_IRT_Transmit2_2 (write) */
  807. /*----------------------------------------------------------------------------*/
  808. #if GH_INLINE_LEVEL < 2
  809. /*! \brief Writes the register 'PMU_IRT_Transmit2_2'. */
  810. void GH_PMU_IRT_set_Transmit2_2(U32 data);
  811. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit2_2'. */
  812. U32 GH_PMU_IRT_getm_Transmit2_2(void);
  813. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit2_2'. */
  814. void GH_PMU_IRT_set_Transmit2_2_VALUE(U8 data);
  815. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit2_2'. */
  816. U8 GH_PMU_IRT_getm_Transmit2_2_VALUE(void);
  817. #else /* GH_INLINE_LEVEL < 2 */
  818. GH_INLINE void GH_PMU_IRT_set_Transmit2_2(U32 data)
  819. {
  820. m_pmu_irt_transmit2_2.all = data;
  821. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_2 = data;
  822. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  823. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_2] <-- 0x%08x\n",
  824. REG_PMU_IRT_TRANSMIT2_2,data,data);
  825. #endif
  826. }
  827. GH_INLINE U32 GH_PMU_IRT_getm_Transmit2_2(void)
  828. {
  829. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  830. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_2] --> 0x%08x\n",
  831. m_pmu_irt_transmit2_2.all);
  832. #endif
  833. return m_pmu_irt_transmit2_2.all;
  834. }
  835. GH_INLINE void GH_PMU_IRT_set_Transmit2_2_VALUE(U8 data)
  836. {
  837. m_pmu_irt_transmit2_2.bitc.value = data;
  838. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_2 = m_pmu_irt_transmit2_2.all;
  839. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  840. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_2_VALUE] <-- 0x%08x\n",
  841. REG_PMU_IRT_TRANSMIT2_2,m_pmu_irt_transmit2_2.all,m_pmu_irt_transmit2_2.all);
  842. #endif
  843. }
  844. GH_INLINE U8 GH_PMU_IRT_getm_Transmit2_2_VALUE(void)
  845. {
  846. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  847. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_2_VALUE] --> 0x%08x\n",
  848. m_pmu_irt_transmit2_2.bitc.value);
  849. #endif
  850. return m_pmu_irt_transmit2_2.bitc.value;
  851. }
  852. #endif /* GH_INLINE_LEVEL < 2 */
  853. /*----------------------------------------------------------------------------*/
  854. /* register PMU_IRT_Transmit2_3 (write) */
  855. /*----------------------------------------------------------------------------*/
  856. #if GH_INLINE_LEVEL < 2
  857. /*! \brief Writes the register 'PMU_IRT_Transmit2_3'. */
  858. void GH_PMU_IRT_set_Transmit2_3(U32 data);
  859. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit2_3'. */
  860. U32 GH_PMU_IRT_getm_Transmit2_3(void);
  861. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit2_3'. */
  862. void GH_PMU_IRT_set_Transmit2_3_VALUE(U8 data);
  863. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit2_3'. */
  864. U8 GH_PMU_IRT_getm_Transmit2_3_VALUE(void);
  865. #else /* GH_INLINE_LEVEL < 2 */
  866. GH_INLINE void GH_PMU_IRT_set_Transmit2_3(U32 data)
  867. {
  868. m_pmu_irt_transmit2_3.all = data;
  869. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_3 = data;
  870. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  871. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_3] <-- 0x%08x\n",
  872. REG_PMU_IRT_TRANSMIT2_3,data,data);
  873. #endif
  874. }
  875. GH_INLINE U32 GH_PMU_IRT_getm_Transmit2_3(void)
  876. {
  877. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  878. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_3] --> 0x%08x\n",
  879. m_pmu_irt_transmit2_3.all);
  880. #endif
  881. return m_pmu_irt_transmit2_3.all;
  882. }
  883. GH_INLINE void GH_PMU_IRT_set_Transmit2_3_VALUE(U8 data)
  884. {
  885. m_pmu_irt_transmit2_3.bitc.value = data;
  886. *(volatile U32 *)REG_PMU_IRT_TRANSMIT2_3 = m_pmu_irt_transmit2_3.all;
  887. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  888. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit2_3_VALUE] <-- 0x%08x\n",
  889. REG_PMU_IRT_TRANSMIT2_3,m_pmu_irt_transmit2_3.all,m_pmu_irt_transmit2_3.all);
  890. #endif
  891. }
  892. GH_INLINE U8 GH_PMU_IRT_getm_Transmit2_3_VALUE(void)
  893. {
  894. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  895. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit2_3_VALUE] --> 0x%08x\n",
  896. m_pmu_irt_transmit2_3.bitc.value);
  897. #endif
  898. return m_pmu_irt_transmit2_3.bitc.value;
  899. }
  900. #endif /* GH_INLINE_LEVEL < 2 */
  901. /*----------------------------------------------------------------------------*/
  902. /* register PMU_IRT_Transmit3_0 (write) */
  903. /*----------------------------------------------------------------------------*/
  904. #if GH_INLINE_LEVEL < 2
  905. /*! \brief Writes the register 'PMU_IRT_Transmit3_0'. */
  906. void GH_PMU_IRT_set_Transmit3_0(U32 data);
  907. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit3_0'. */
  908. U32 GH_PMU_IRT_getm_Transmit3_0(void);
  909. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit3_0'. */
  910. void GH_PMU_IRT_set_Transmit3_0_VALUE(U8 data);
  911. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit3_0'. */
  912. U8 GH_PMU_IRT_getm_Transmit3_0_VALUE(void);
  913. #else /* GH_INLINE_LEVEL < 2 */
  914. GH_INLINE void GH_PMU_IRT_set_Transmit3_0(U32 data)
  915. {
  916. m_pmu_irt_transmit3_0.all = data;
  917. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_0 = data;
  918. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  919. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_0] <-- 0x%08x\n",
  920. REG_PMU_IRT_TRANSMIT3_0,data,data);
  921. #endif
  922. }
  923. GH_INLINE U32 GH_PMU_IRT_getm_Transmit3_0(void)
  924. {
  925. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  926. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_0] --> 0x%08x\n",
  927. m_pmu_irt_transmit3_0.all);
  928. #endif
  929. return m_pmu_irt_transmit3_0.all;
  930. }
  931. GH_INLINE void GH_PMU_IRT_set_Transmit3_0_VALUE(U8 data)
  932. {
  933. m_pmu_irt_transmit3_0.bitc.value = data;
  934. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_0 = m_pmu_irt_transmit3_0.all;
  935. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  936. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_0_VALUE] <-- 0x%08x\n",
  937. REG_PMU_IRT_TRANSMIT3_0,m_pmu_irt_transmit3_0.all,m_pmu_irt_transmit3_0.all);
  938. #endif
  939. }
  940. GH_INLINE U8 GH_PMU_IRT_getm_Transmit3_0_VALUE(void)
  941. {
  942. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  943. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_0_VALUE] --> 0x%08x\n",
  944. m_pmu_irt_transmit3_0.bitc.value);
  945. #endif
  946. return m_pmu_irt_transmit3_0.bitc.value;
  947. }
  948. #endif /* GH_INLINE_LEVEL < 2 */
  949. /*----------------------------------------------------------------------------*/
  950. /* register PMU_IRT_Transmit3_1 (write) */
  951. /*----------------------------------------------------------------------------*/
  952. #if GH_INLINE_LEVEL < 2
  953. /*! \brief Writes the register 'PMU_IRT_Transmit3_1'. */
  954. void GH_PMU_IRT_set_Transmit3_1(U32 data);
  955. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit3_1'. */
  956. U32 GH_PMU_IRT_getm_Transmit3_1(void);
  957. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit3_1'. */
  958. void GH_PMU_IRT_set_Transmit3_1_VALUE(U8 data);
  959. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit3_1'. */
  960. U8 GH_PMU_IRT_getm_Transmit3_1_VALUE(void);
  961. #else /* GH_INLINE_LEVEL < 2 */
  962. GH_INLINE void GH_PMU_IRT_set_Transmit3_1(U32 data)
  963. {
  964. m_pmu_irt_transmit3_1.all = data;
  965. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_1 = data;
  966. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  967. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_1] <-- 0x%08x\n",
  968. REG_PMU_IRT_TRANSMIT3_1,data,data);
  969. #endif
  970. }
  971. GH_INLINE U32 GH_PMU_IRT_getm_Transmit3_1(void)
  972. {
  973. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  974. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_1] --> 0x%08x\n",
  975. m_pmu_irt_transmit3_1.all);
  976. #endif
  977. return m_pmu_irt_transmit3_1.all;
  978. }
  979. GH_INLINE void GH_PMU_IRT_set_Transmit3_1_VALUE(U8 data)
  980. {
  981. m_pmu_irt_transmit3_1.bitc.value = data;
  982. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_1 = m_pmu_irt_transmit3_1.all;
  983. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  984. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_1_VALUE] <-- 0x%08x\n",
  985. REG_PMU_IRT_TRANSMIT3_1,m_pmu_irt_transmit3_1.all,m_pmu_irt_transmit3_1.all);
  986. #endif
  987. }
  988. GH_INLINE U8 GH_PMU_IRT_getm_Transmit3_1_VALUE(void)
  989. {
  990. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  991. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_1_VALUE] --> 0x%08x\n",
  992. m_pmu_irt_transmit3_1.bitc.value);
  993. #endif
  994. return m_pmu_irt_transmit3_1.bitc.value;
  995. }
  996. #endif /* GH_INLINE_LEVEL < 2 */
  997. /*----------------------------------------------------------------------------*/
  998. /* register PMU_IRT_Transmit3_2 (write) */
  999. /*----------------------------------------------------------------------------*/
  1000. #if GH_INLINE_LEVEL < 2
  1001. /*! \brief Writes the register 'PMU_IRT_Transmit3_2'. */
  1002. void GH_PMU_IRT_set_Transmit3_2(U32 data);
  1003. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit3_2'. */
  1004. U32 GH_PMU_IRT_getm_Transmit3_2(void);
  1005. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit3_2'. */
  1006. void GH_PMU_IRT_set_Transmit3_2_VALUE(U8 data);
  1007. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit3_2'. */
  1008. U8 GH_PMU_IRT_getm_Transmit3_2_VALUE(void);
  1009. #else /* GH_INLINE_LEVEL < 2 */
  1010. GH_INLINE void GH_PMU_IRT_set_Transmit3_2(U32 data)
  1011. {
  1012. m_pmu_irt_transmit3_2.all = data;
  1013. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_2 = data;
  1014. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1015. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_2] <-- 0x%08x\n",
  1016. REG_PMU_IRT_TRANSMIT3_2,data,data);
  1017. #endif
  1018. }
  1019. GH_INLINE U32 GH_PMU_IRT_getm_Transmit3_2(void)
  1020. {
  1021. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1022. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_2] --> 0x%08x\n",
  1023. m_pmu_irt_transmit3_2.all);
  1024. #endif
  1025. return m_pmu_irt_transmit3_2.all;
  1026. }
  1027. GH_INLINE void GH_PMU_IRT_set_Transmit3_2_VALUE(U8 data)
  1028. {
  1029. m_pmu_irt_transmit3_2.bitc.value = data;
  1030. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_2 = m_pmu_irt_transmit3_2.all;
  1031. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1032. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_2_VALUE] <-- 0x%08x\n",
  1033. REG_PMU_IRT_TRANSMIT3_2,m_pmu_irt_transmit3_2.all,m_pmu_irt_transmit3_2.all);
  1034. #endif
  1035. }
  1036. GH_INLINE U8 GH_PMU_IRT_getm_Transmit3_2_VALUE(void)
  1037. {
  1038. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1039. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_2_VALUE] --> 0x%08x\n",
  1040. m_pmu_irt_transmit3_2.bitc.value);
  1041. #endif
  1042. return m_pmu_irt_transmit3_2.bitc.value;
  1043. }
  1044. #endif /* GH_INLINE_LEVEL < 2 */
  1045. /*----------------------------------------------------------------------------*/
  1046. /* register PMU_IRT_Transmit3_3 (write) */
  1047. /*----------------------------------------------------------------------------*/
  1048. #if GH_INLINE_LEVEL < 2
  1049. /*! \brief Writes the register 'PMU_IRT_Transmit3_3'. */
  1050. void GH_PMU_IRT_set_Transmit3_3(U32 data);
  1051. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Transmit3_3'. */
  1052. U32 GH_PMU_IRT_getm_Transmit3_3(void);
  1053. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Transmit3_3'. */
  1054. void GH_PMU_IRT_set_Transmit3_3_VALUE(U8 data);
  1055. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Transmit3_3'. */
  1056. U8 GH_PMU_IRT_getm_Transmit3_3_VALUE(void);
  1057. #else /* GH_INLINE_LEVEL < 2 */
  1058. GH_INLINE void GH_PMU_IRT_set_Transmit3_3(U32 data)
  1059. {
  1060. m_pmu_irt_transmit3_3.all = data;
  1061. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_3 = data;
  1062. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1063. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_3] <-- 0x%08x\n",
  1064. REG_PMU_IRT_TRANSMIT3_3,data,data);
  1065. #endif
  1066. }
  1067. GH_INLINE U32 GH_PMU_IRT_getm_Transmit3_3(void)
  1068. {
  1069. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1070. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_3] --> 0x%08x\n",
  1071. m_pmu_irt_transmit3_3.all);
  1072. #endif
  1073. return m_pmu_irt_transmit3_3.all;
  1074. }
  1075. GH_INLINE void GH_PMU_IRT_set_Transmit3_3_VALUE(U8 data)
  1076. {
  1077. m_pmu_irt_transmit3_3.bitc.value = data;
  1078. *(volatile U32 *)REG_PMU_IRT_TRANSMIT3_3 = m_pmu_irt_transmit3_3.all;
  1079. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1080. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Transmit3_3_VALUE] <-- 0x%08x\n",
  1081. REG_PMU_IRT_TRANSMIT3_3,m_pmu_irt_transmit3_3.all,m_pmu_irt_transmit3_3.all);
  1082. #endif
  1083. }
  1084. GH_INLINE U8 GH_PMU_IRT_getm_Transmit3_3_VALUE(void)
  1085. {
  1086. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1087. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Transmit3_3_VALUE] --> 0x%08x\n",
  1088. m_pmu_irt_transmit3_3.bitc.value);
  1089. #endif
  1090. return m_pmu_irt_transmit3_3.bitc.value;
  1091. }
  1092. #endif /* GH_INLINE_LEVEL < 2 */
  1093. /*----------------------------------------------------------------------------*/
  1094. /* register PMU_IRT_Sent_Clock_l (write) */
  1095. /*----------------------------------------------------------------------------*/
  1096. #if GH_INLINE_LEVEL < 2
  1097. /*! \brief Writes the register 'PMU_IRT_Sent_Clock_l'. */
  1098. void GH_PMU_IRT_set_Sent_Clock_l(U32 data);
  1099. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Sent_Clock_l'. */
  1100. U32 GH_PMU_IRT_getm_Sent_Clock_l(void);
  1101. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Sent_Clock_l'. */
  1102. void GH_PMU_IRT_set_Sent_Clock_l_VALUE(U8 data);
  1103. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Sent_Clock_l'. */
  1104. U8 GH_PMU_IRT_getm_Sent_Clock_l_VALUE(void);
  1105. #else /* GH_INLINE_LEVEL < 2 */
  1106. GH_INLINE void GH_PMU_IRT_set_Sent_Clock_l(U32 data)
  1107. {
  1108. m_pmu_irt_sent_clock_l.all = data;
  1109. *(volatile U32 *)REG_PMU_IRT_SENT_CLOCK_L = data;
  1110. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1111. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Sent_Clock_l] <-- 0x%08x\n",
  1112. REG_PMU_IRT_SENT_CLOCK_L,data,data);
  1113. #endif
  1114. }
  1115. GH_INLINE U32 GH_PMU_IRT_getm_Sent_Clock_l(void)
  1116. {
  1117. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1118. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Sent_Clock_l] --> 0x%08x\n",
  1119. m_pmu_irt_sent_clock_l.all);
  1120. #endif
  1121. return m_pmu_irt_sent_clock_l.all;
  1122. }
  1123. GH_INLINE void GH_PMU_IRT_set_Sent_Clock_l_VALUE(U8 data)
  1124. {
  1125. m_pmu_irt_sent_clock_l.bitc.value = data;
  1126. *(volatile U32 *)REG_PMU_IRT_SENT_CLOCK_L = m_pmu_irt_sent_clock_l.all;
  1127. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1128. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Sent_Clock_l_VALUE] <-- 0x%08x\n",
  1129. REG_PMU_IRT_SENT_CLOCK_L,m_pmu_irt_sent_clock_l.all,m_pmu_irt_sent_clock_l.all);
  1130. #endif
  1131. }
  1132. GH_INLINE U8 GH_PMU_IRT_getm_Sent_Clock_l_VALUE(void)
  1133. {
  1134. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1135. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Sent_Clock_l_VALUE] --> 0x%08x\n",
  1136. m_pmu_irt_sent_clock_l.bitc.value);
  1137. #endif
  1138. return m_pmu_irt_sent_clock_l.bitc.value;
  1139. }
  1140. #endif /* GH_INLINE_LEVEL < 2 */
  1141. /*----------------------------------------------------------------------------*/
  1142. /* register PMU_IRT_Sent_Clock_h (write) */
  1143. /*----------------------------------------------------------------------------*/
  1144. #if GH_INLINE_LEVEL < 2
  1145. /*! \brief Writes the register 'PMU_IRT_Sent_Clock_h'. */
  1146. void GH_PMU_IRT_set_Sent_Clock_h(U32 data);
  1147. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Sent_Clock_h'. */
  1148. U32 GH_PMU_IRT_getm_Sent_Clock_h(void);
  1149. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Sent_Clock_h'. */
  1150. void GH_PMU_IRT_set_Sent_Clock_h_VALUE(U8 data);
  1151. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Sent_Clock_h'. */
  1152. U8 GH_PMU_IRT_getm_Sent_Clock_h_VALUE(void);
  1153. #else /* GH_INLINE_LEVEL < 2 */
  1154. GH_INLINE void GH_PMU_IRT_set_Sent_Clock_h(U32 data)
  1155. {
  1156. m_pmu_irt_sent_clock_h.all = data;
  1157. *(volatile U32 *)REG_PMU_IRT_SENT_CLOCK_H = data;
  1158. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1159. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Sent_Clock_h] <-- 0x%08x\n",
  1160. REG_PMU_IRT_SENT_CLOCK_H,data,data);
  1161. #endif
  1162. }
  1163. GH_INLINE U32 GH_PMU_IRT_getm_Sent_Clock_h(void)
  1164. {
  1165. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1166. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Sent_Clock_h] --> 0x%08x\n",
  1167. m_pmu_irt_sent_clock_h.all);
  1168. #endif
  1169. return m_pmu_irt_sent_clock_h.all;
  1170. }
  1171. GH_INLINE void GH_PMU_IRT_set_Sent_Clock_h_VALUE(U8 data)
  1172. {
  1173. m_pmu_irt_sent_clock_h.bitc.value = data;
  1174. *(volatile U32 *)REG_PMU_IRT_SENT_CLOCK_H = m_pmu_irt_sent_clock_h.all;
  1175. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1176. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Sent_Clock_h_VALUE] <-- 0x%08x\n",
  1177. REG_PMU_IRT_SENT_CLOCK_H,m_pmu_irt_sent_clock_h.all,m_pmu_irt_sent_clock_h.all);
  1178. #endif
  1179. }
  1180. GH_INLINE U8 GH_PMU_IRT_getm_Sent_Clock_h_VALUE(void)
  1181. {
  1182. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1183. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Sent_Clock_h_VALUE] --> 0x%08x\n",
  1184. m_pmu_irt_sent_clock_h.bitc.value);
  1185. #endif
  1186. return m_pmu_irt_sent_clock_h.bitc.value;
  1187. }
  1188. #endif /* GH_INLINE_LEVEL < 2 */
  1189. /*----------------------------------------------------------------------------*/
  1190. /* register PMU_IRT_Shift_Clock (write) */
  1191. /*----------------------------------------------------------------------------*/
  1192. #if GH_INLINE_LEVEL < 2
  1193. /*! \brief Writes the register 'PMU_IRT_Shift_Clock'. */
  1194. void GH_PMU_IRT_set_Shift_Clock(U32 data);
  1195. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Shift_Clock'. */
  1196. U32 GH_PMU_IRT_getm_Shift_Clock(void);
  1197. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Shift_Clock'. */
  1198. void GH_PMU_IRT_set_Shift_Clock_VALUE(U8 data);
  1199. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Shift_Clock'. */
  1200. U8 GH_PMU_IRT_getm_Shift_Clock_VALUE(void);
  1201. #else /* GH_INLINE_LEVEL < 2 */
  1202. GH_INLINE void GH_PMU_IRT_set_Shift_Clock(U32 data)
  1203. {
  1204. m_pmu_irt_shift_clock.all = data;
  1205. *(volatile U32 *)REG_PMU_IRT_SHIFT_CLOCK = data;
  1206. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1207. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Shift_Clock] <-- 0x%08x\n",
  1208. REG_PMU_IRT_SHIFT_CLOCK,data,data);
  1209. #endif
  1210. }
  1211. GH_INLINE U32 GH_PMU_IRT_getm_Shift_Clock(void)
  1212. {
  1213. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1214. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Shift_Clock] --> 0x%08x\n",
  1215. m_pmu_irt_shift_clock.all);
  1216. #endif
  1217. return m_pmu_irt_shift_clock.all;
  1218. }
  1219. GH_INLINE void GH_PMU_IRT_set_Shift_Clock_VALUE(U8 data)
  1220. {
  1221. m_pmu_irt_shift_clock.bitc.value = data;
  1222. *(volatile U32 *)REG_PMU_IRT_SHIFT_CLOCK = m_pmu_irt_shift_clock.all;
  1223. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1224. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Shift_Clock_VALUE] <-- 0x%08x\n",
  1225. REG_PMU_IRT_SHIFT_CLOCK,m_pmu_irt_shift_clock.all,m_pmu_irt_shift_clock.all);
  1226. #endif
  1227. }
  1228. GH_INLINE U8 GH_PMU_IRT_getm_Shift_Clock_VALUE(void)
  1229. {
  1230. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1231. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Shift_Clock_VALUE] --> 0x%08x\n",
  1232. m_pmu_irt_shift_clock.bitc.value);
  1233. #endif
  1234. return m_pmu_irt_shift_clock.bitc.value;
  1235. }
  1236. #endif /* GH_INLINE_LEVEL < 2 */
  1237. /*----------------------------------------------------------------------------*/
  1238. /* register PMU_IRT_Sent_Conf (write) */
  1239. /*----------------------------------------------------------------------------*/
  1240. #if GH_INLINE_LEVEL < 2
  1241. /*! \brief Writes the register 'PMU_IRT_Sent_Conf'. */
  1242. void GH_PMU_IRT_set_Sent_Conf(U32 data);
  1243. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Sent_Conf'. */
  1244. U32 GH_PMU_IRT_getm_Sent_Conf(void);
  1245. /*! \brief Writes the bit group 'EN_TX_IRQ' of register 'PMU_IRT_Sent_Conf'. */
  1246. void GH_PMU_IRT_set_Sent_Conf_EN_TX_IRQ(U8 data);
  1247. /*! \brief Reads the bit group 'EN_TX_IRQ' from the mirror variable of register 'PMU_IRT_Sent_Conf'. */
  1248. U8 GH_PMU_IRT_getm_Sent_Conf_EN_TX_IRQ(void);
  1249. /*! \brief Writes the bit group 'MODE' of register 'PMU_IRT_Sent_Conf'. */
  1250. void GH_PMU_IRT_set_Sent_Conf_MODE(U8 data);
  1251. /*! \brief Reads the bit group 'MODE' from the mirror variable of register 'PMU_IRT_Sent_Conf'. */
  1252. U8 GH_PMU_IRT_getm_Sent_Conf_MODE(void);
  1253. #else /* GH_INLINE_LEVEL < 2 */
  1254. GH_INLINE void GH_PMU_IRT_set_Sent_Conf(U32 data)
  1255. {
  1256. m_pmu_irt_sent_conf.all = data;
  1257. *(volatile U32 *)REG_PMU_IRT_SENT_CONF = data;
  1258. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1259. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Sent_Conf] <-- 0x%08x\n",
  1260. REG_PMU_IRT_SENT_CONF,data,data);
  1261. #endif
  1262. }
  1263. GH_INLINE U32 GH_PMU_IRT_getm_Sent_Conf(void)
  1264. {
  1265. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1266. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Sent_Conf] --> 0x%08x\n",
  1267. m_pmu_irt_sent_conf.all);
  1268. #endif
  1269. return m_pmu_irt_sent_conf.all;
  1270. }
  1271. GH_INLINE void GH_PMU_IRT_set_Sent_Conf_EN_TX_IRQ(U8 data)
  1272. {
  1273. m_pmu_irt_sent_conf.bitc.en_tx_irq = data;
  1274. *(volatile U32 *)REG_PMU_IRT_SENT_CONF = m_pmu_irt_sent_conf.all;
  1275. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1276. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Sent_Conf_EN_TX_IRQ] <-- 0x%08x\n",
  1277. REG_PMU_IRT_SENT_CONF,m_pmu_irt_sent_conf.all,m_pmu_irt_sent_conf.all);
  1278. #endif
  1279. }
  1280. GH_INLINE U8 GH_PMU_IRT_getm_Sent_Conf_EN_TX_IRQ(void)
  1281. {
  1282. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1283. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Sent_Conf_EN_TX_IRQ] --> 0x%08x\n",
  1284. m_pmu_irt_sent_conf.bitc.en_tx_irq);
  1285. #endif
  1286. return m_pmu_irt_sent_conf.bitc.en_tx_irq;
  1287. }
  1288. GH_INLINE void GH_PMU_IRT_set_Sent_Conf_MODE(U8 data)
  1289. {
  1290. m_pmu_irt_sent_conf.bitc.mode = data;
  1291. *(volatile U32 *)REG_PMU_IRT_SENT_CONF = m_pmu_irt_sent_conf.all;
  1292. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1293. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Sent_Conf_MODE] <-- 0x%08x\n",
  1294. REG_PMU_IRT_SENT_CONF,m_pmu_irt_sent_conf.all,m_pmu_irt_sent_conf.all);
  1295. #endif
  1296. }
  1297. GH_INLINE U8 GH_PMU_IRT_getm_Sent_Conf_MODE(void)
  1298. {
  1299. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1300. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Sent_Conf_MODE] --> 0x%08x\n",
  1301. m_pmu_irt_sent_conf.bitc.mode);
  1302. #endif
  1303. return m_pmu_irt_sent_conf.bitc.mode;
  1304. }
  1305. #endif /* GH_INLINE_LEVEL < 2 */
  1306. /*----------------------------------------------------------------------------*/
  1307. /* register PMU_IRT_Compvalue (write) */
  1308. /*----------------------------------------------------------------------------*/
  1309. #if GH_INLINE_LEVEL < 2
  1310. /*! \brief Writes the register 'PMU_IRT_Compvalue'. */
  1311. void GH_PMU_IRT_set_Compvalue(U32 data);
  1312. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Compvalue'. */
  1313. U32 GH_PMU_IRT_getm_Compvalue(void);
  1314. /*! \brief Writes the bit group 'VALUE' of register 'PMU_IRT_Compvalue'. */
  1315. void GH_PMU_IRT_set_Compvalue_VALUE(U8 data);
  1316. /*! \brief Reads the bit group 'VALUE' from the mirror variable of register 'PMU_IRT_Compvalue'. */
  1317. U8 GH_PMU_IRT_getm_Compvalue_VALUE(void);
  1318. #else /* GH_INLINE_LEVEL < 2 */
  1319. GH_INLINE void GH_PMU_IRT_set_Compvalue(U32 data)
  1320. {
  1321. m_pmu_irt_compvalue.all = data;
  1322. *(volatile U32 *)REG_PMU_IRT_COMPVALUE = data;
  1323. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1324. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Compvalue] <-- 0x%08x\n",
  1325. REG_PMU_IRT_COMPVALUE,data,data);
  1326. #endif
  1327. }
  1328. GH_INLINE U32 GH_PMU_IRT_getm_Compvalue(void)
  1329. {
  1330. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1331. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Compvalue] --> 0x%08x\n",
  1332. m_pmu_irt_compvalue.all);
  1333. #endif
  1334. return m_pmu_irt_compvalue.all;
  1335. }
  1336. GH_INLINE void GH_PMU_IRT_set_Compvalue_VALUE(U8 data)
  1337. {
  1338. m_pmu_irt_compvalue.bitc.value = data;
  1339. *(volatile U32 *)REG_PMU_IRT_COMPVALUE = m_pmu_irt_compvalue.all;
  1340. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1341. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Compvalue_VALUE] <-- 0x%08x\n",
  1342. REG_PMU_IRT_COMPVALUE,m_pmu_irt_compvalue.all,m_pmu_irt_compvalue.all);
  1343. #endif
  1344. }
  1345. GH_INLINE U8 GH_PMU_IRT_getm_Compvalue_VALUE(void)
  1346. {
  1347. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1348. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Compvalue_VALUE] --> 0x%08x\n",
  1349. m_pmu_irt_compvalue.bitc.value);
  1350. #endif
  1351. return m_pmu_irt_compvalue.bitc.value;
  1352. }
  1353. #endif /* GH_INLINE_LEVEL < 2 */
  1354. /*----------------------------------------------------------------------------*/
  1355. /* register PMU_IRT_Start (write) */
  1356. /*----------------------------------------------------------------------------*/
  1357. #if GH_INLINE_LEVEL < 2
  1358. /*! \brief Writes the register 'PMU_IRT_Start'. */
  1359. void GH_PMU_IRT_set_Start(U32 data);
  1360. /*! \brief Reads the mirror variable of the register 'PMU_IRT_Start'. */
  1361. U32 GH_PMU_IRT_getm_Start(void);
  1362. /*! \brief Writes the bit group 'START_TX' of register 'PMU_IRT_Start'. */
  1363. void GH_PMU_IRT_set_Start_START_TX(U8 data);
  1364. /*! \brief Reads the bit group 'START_TX' from the mirror variable of register 'PMU_IRT_Start'. */
  1365. U8 GH_PMU_IRT_getm_Start_START_TX(void);
  1366. #else /* GH_INLINE_LEVEL < 2 */
  1367. GH_INLINE void GH_PMU_IRT_set_Start(U32 data)
  1368. {
  1369. m_pmu_irt_start.all = data;
  1370. *(volatile U32 *)REG_PMU_IRT_START = data;
  1371. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1372. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Start] <-- 0x%08x\n",
  1373. REG_PMU_IRT_START,data,data);
  1374. #endif
  1375. }
  1376. GH_INLINE U32 GH_PMU_IRT_getm_Start(void)
  1377. {
  1378. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1379. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Start] --> 0x%08x\n",
  1380. m_pmu_irt_start.all);
  1381. #endif
  1382. return m_pmu_irt_start.all;
  1383. }
  1384. GH_INLINE void GH_PMU_IRT_set_Start_START_TX(U8 data)
  1385. {
  1386. m_pmu_irt_start.bitc.start_tx = data;
  1387. *(volatile U32 *)REG_PMU_IRT_START = m_pmu_irt_start.all;
  1388. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1389. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_PMU_IRT_set_Start_START_TX] <-- 0x%08x\n",
  1390. REG_PMU_IRT_START,m_pmu_irt_start.all,m_pmu_irt_start.all);
  1391. #endif
  1392. }
  1393. GH_INLINE U8 GH_PMU_IRT_getm_Start_START_TX(void)
  1394. {
  1395. #if GH_PMU_IRT_ENABLE_DEBUG_PRINT
  1396. GH_PMU_IRT_DEBUG_PRINT_FUNCTION( "[GH_PMU_IRT_getm_Start_START_TX] --> 0x%08x\n",
  1397. m_pmu_irt_start.bitc.start_tx);
  1398. #endif
  1399. return m_pmu_irt_start.bitc.start_tx;
  1400. }
  1401. #endif /* GH_INLINE_LEVEL < 2 */
  1402. /*----------------------------------------------------------------------------*/
  1403. /* init function */
  1404. /*----------------------------------------------------------------------------*/
  1405. /*! \brief Initialises the registers and mirror variables. */
  1406. void GH_PMU_IRT_init(void);
  1407. #ifdef __cplusplus
  1408. }
  1409. #endif
  1410. #endif /* _GH_PMU_IRT_H */
  1411. /*----------------------------------------------------------------------------*/
  1412. /* end of file */
  1413. /*----------------------------------------------------------------------------*/