gh_eth.h 154 KB

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  1. /*!
  2. *******************************************************************************
  3. **
  4. ** \file gh_eth.h
  5. **
  6. ** \brief Ethernet controller.
  7. **
  8. ** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
  9. **
  10. ** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
  11. ** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
  12. ** OMMISSIONS.
  13. **
  14. ** \note Do not modify this file as it is generated automatically.
  15. **
  16. ******************************************************************************/
  17. #ifndef _GH_ETH_H
  18. #define _GH_ETH_H
  19. #ifdef __LINUX__
  20. #include "reg4linux.h"
  21. #else
  22. #define FIO_ADDRESS(block,address) (address)
  23. #define FIO_MOFFSET(block,moffset) (moffset)
  24. #endif
  25. #ifndef __LINUX__
  26. #include "gtypes.h" /* global type definitions */
  27. #include "gh_lib_cfg.h" /* configuration */
  28. #endif
  29. #define GH_ETH_ENABLE_DEBUG_PRINT 0
  30. #ifdef __LINUX__
  31. #define GH_ETH_DEBUG_PRINT_FUNCTION printk
  32. #else
  33. #define GH_ETH_DEBUG_PRINT_FUNCTION printf
  34. #endif
  35. #ifndef __LINUX__
  36. #if GH_ETH_ENABLE_DEBUG_PRINT
  37. #include <stdio.h>
  38. #endif
  39. #endif
  40. /* check configuration */
  41. #ifndef GH_INLINE_LEVEL
  42. #error "GH_INLINE_LEVEL is not defined!"
  43. #endif
  44. #if GH_INLINE_LEVEL > 2
  45. #error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
  46. #endif
  47. #ifndef GH_INLINE
  48. #error "GH_INLINE is not defined!"
  49. #endif
  50. /* disable inlining for debugging */
  51. #ifdef DEBUG
  52. #undef GH_INLINE_LEVEL
  53. #define GH_INLINE_LEVEL 0
  54. #endif
  55. /*----------------------------------------------------------------------------*/
  56. /* registers */
  57. /*----------------------------------------------------------------------------*/
  58. #define REG_ETH_MCR FIO_ADDRESS(ETH,0x9000E000) /* read/write */
  59. #define REG_ETH_GAR FIO_ADDRESS(ETH,0x9000E004) /* read/write */
  60. #define REG_ETH_GDR FIO_ADDRESS(ETH,0x9000E008) /* read/write */
  61. #define REG_ETH_MFFR FIO_ADDRESS(ETH,0x9000E00C) /* read/write */
  62. #define REG_ETH_MHTRH FIO_ADDRESS(ETH,0x9000E010) /* read/write */
  63. #define REG_ETH_MHTRL FIO_ADDRESS(ETH,0x9000E014) /* read/write */
  64. #define REG_ETH_FCR FIO_ADDRESS(ETH,0x9000E018) /* read/write */
  65. #define REG_ETH_VTR FIO_ADDRESS(ETH,0x9000E01C) /* read/write */
  66. #define REG_ETH_MAR0H FIO_ADDRESS(ETH,0x9000E040) /* read/write */
  67. #define REG_ETH_MAR0L FIO_ADDRESS(ETH,0x9000E044) /* read/write */
  68. #define REG_ETH_MAR1H FIO_ADDRESS(ETH,0x9000E048) /* read/write */
  69. #define REG_ETH_MAR1L FIO_ADDRESS(ETH,0x9000E04C) /* read/write */
  70. #define REG_ETH_MAR2H FIO_ADDRESS(ETH,0x9000E050) /* read/write */
  71. #define REG_ETH_MAR2L FIO_ADDRESS(ETH,0x9000E054) /* read/write */
  72. #define REG_ETH_VR FIO_ADDRESS(ETH,0x9000E058) /* read */
  73. #define REG_ETH_EPHY_DEBUG FIO_ADDRESS(ETH,0x9000E05C) /* read/write */
  74. #define REG_ETH_TPDR FIO_ADDRESS(ETH,0x9000F000) /* read/write */
  75. #define REG_ETH_RPDR FIO_ADDRESS(ETH,0x9000F004) /* read/write */
  76. #define REG_ETH_BMR FIO_ADDRESS(ETH,0x9000F008) /* read/write */
  77. #define REG_ETH_RDLAR FIO_ADDRESS(ETH,0x9000F00C) /* read/write */
  78. #define REG_ETH_TDLAR FIO_ADDRESS(ETH,0x9000F010) /* read/write */
  79. #define REG_ETH_SR FIO_ADDRESS(ETH,0x9000F014) /* read/write */
  80. #define REG_ETH_MFBOCR FIO_ADDRESS(ETH,0x9000F018) /* read/write */
  81. #define REG_ETH_IER FIO_ADDRESS(ETH,0x9000F01C) /* read/write */
  82. #define REG_ETH_OMR FIO_ADDRESS(ETH,0x9000F020) /* read/write */
  83. #define REG_ETH_CHTBAR FIO_ADDRESS(ETH,0x9000F040) /* read/write */
  84. #define REG_ETH_CHRBAR FIO_ADDRESS(ETH,0x9000F044) /* read/write */
  85. #define REG_ETH_CHTDR FIO_ADDRESS(ETH,0x9000F048) /* read/write */
  86. #define REG_ETH_CHRDR FIO_ADDRESS(ETH,0x9000F04C) /* read/write */
  87. /*----------------------------------------------------------------------------*/
  88. /* bit group structures */
  89. /*----------------------------------------------------------------------------*/
  90. typedef union { /* ETH_MCR */
  91. U32 all;
  92. struct {
  93. U32 : 2;
  94. U32 re : 1;
  95. U32 te : 1;
  96. U32 dc : 1;
  97. U32 bl : 2;
  98. U32 acs : 1;
  99. U32 lud : 1;
  100. U32 dr : 1;
  101. U32 ipc : 1;
  102. U32 dm : 1;
  103. U32 lm : 1;
  104. U32 dro : 1;
  105. U32 fes : 1;
  106. U32 ps : 1;
  107. U32 dcrs : 1;
  108. U32 ifg : 3;
  109. U32 je : 1;
  110. U32 be : 1;
  111. U32 jd : 1;
  112. U32 wd : 1;
  113. U32 : 8;
  114. } bitc;
  115. } GH_ETH_MCR_S;
  116. typedef union { /* ETH_GAR */
  117. U32 all;
  118. struct {
  119. U32 gb : 1;
  120. U32 gw : 1;
  121. U32 cr : 3;
  122. U32 : 1;
  123. U32 gr : 5;
  124. U32 pa : 5;
  125. U32 : 16;
  126. } bitc;
  127. } GH_ETH_GAR_S;
  128. typedef union { /* ETH_GDR */
  129. U32 all;
  130. struct {
  131. U32 gd : 16;
  132. U32 : 16;
  133. } bitc;
  134. } GH_ETH_GDR_S;
  135. typedef union { /* ETH_MFFR */
  136. U32 all;
  137. struct {
  138. U32 pr : 1;
  139. U32 huc : 1;
  140. U32 hmc : 1;
  141. U32 ift : 1;
  142. U32 pm : 1;
  143. U32 db : 1;
  144. U32 : 1;
  145. U32 pcf : 1;
  146. U32 saif : 1;
  147. U32 saf : 1;
  148. U32 hpf : 1;
  149. U32 : 20;
  150. U32 ra : 1;
  151. } bitc;
  152. } GH_ETH_MFFR_S;
  153. typedef union { /* ETH_MHTRH */
  154. U32 all;
  155. struct {
  156. U32 hth : 32;
  157. } bitc;
  158. } GH_ETH_MHTRH_S;
  159. typedef union { /* ETH_MHTRL */
  160. U32 all;
  161. struct {
  162. U32 htl : 32;
  163. } bitc;
  164. } GH_ETH_MHTRL_S;
  165. typedef union { /* ETH_FCR */
  166. U32 all;
  167. struct {
  168. U32 fcb : 1;
  169. U32 tfe : 1;
  170. U32 rfe : 1;
  171. U32 up : 1;
  172. U32 plt : 2;
  173. U32 : 10;
  174. U32 pt : 16;
  175. } bitc;
  176. } GH_ETH_FCR_S;
  177. typedef union { /* ETH_VTR */
  178. U32 all;
  179. struct {
  180. U32 vl : 16;
  181. U32 etv : 1;
  182. U32 : 15;
  183. } bitc;
  184. } GH_ETH_VTR_S;
  185. typedef union { /* ETH_MAR0H */
  186. U32 all;
  187. struct {
  188. U32 a0 : 16;
  189. U32 : 15;
  190. U32 m0 : 1;
  191. } bitc;
  192. } GH_ETH_MAR0H_S;
  193. typedef union { /* ETH_MAR0L */
  194. U32 all;
  195. struct {
  196. U32 a0 : 32;
  197. } bitc;
  198. } GH_ETH_MAR0L_S;
  199. typedef union { /* ETH_MAR1H */
  200. U32 all;
  201. struct {
  202. U32 a1 : 16;
  203. U32 : 8;
  204. U32 mbc : 6;
  205. U32 sa : 1;
  206. U32 a1e : 1;
  207. } bitc;
  208. } GH_ETH_MAR1H_S;
  209. typedef union { /* ETH_MAR1L */
  210. U32 all;
  211. struct {
  212. U32 a1 : 32;
  213. } bitc;
  214. } GH_ETH_MAR1L_S;
  215. typedef union { /* ETH_MAR2H */
  216. U32 all;
  217. struct {
  218. U32 a2 : 16;
  219. U32 : 8;
  220. U32 mbc : 6;
  221. U32 sa : 1;
  222. U32 a2e : 1;
  223. } bitc;
  224. } GH_ETH_MAR2H_S;
  225. typedef union { /* ETH_MAR2L */
  226. U32 all;
  227. struct {
  228. U32 a2 : 32;
  229. } bitc;
  230. } GH_ETH_MAR2L_S;
  231. typedef union { /* ETH_EPHY_DEBUG */
  232. U32 all;
  233. struct {
  234. U32 : 8;
  235. U32 debug : 24;
  236. } bitc;
  237. } GH_ETH_EPHY_DEBUG_S;
  238. typedef union { /* ETH_BMR */
  239. U32 all;
  240. struct {
  241. U32 swr : 1;
  242. U32 da : 1;
  243. U32 dsl : 5;
  244. U32 : 1;
  245. U32 pbl : 6;
  246. U32 pr : 2;
  247. U32 fb : 1;
  248. U32 rpbl : 6;
  249. U32 usp : 1;
  250. U32 pbl4x : 1;
  251. U32 aal : 1;
  252. U32 : 6;
  253. } bitc;
  254. } GH_ETH_BMR_S;
  255. typedef union { /* ETH_SR */
  256. U32 all;
  257. struct {
  258. U32 ti : 1;
  259. U32 tps : 1;
  260. U32 tu : 1;
  261. U32 tjt : 1;
  262. U32 ovf : 1;
  263. U32 unf : 1;
  264. U32 ri : 1;
  265. U32 ru : 1;
  266. U32 rps : 1;
  267. U32 rwt : 1;
  268. U32 eti : 1;
  269. U32 : 2;
  270. U32 fbe : 1;
  271. U32 eri : 1;
  272. U32 ais : 1;
  273. U32 nis : 1;
  274. U32 rs : 3;
  275. U32 ts : 3;
  276. U32 eb : 3;
  277. U32 gli : 1;
  278. U32 gmi : 1;
  279. U32 gpi : 1;
  280. U32 : 3;
  281. } bitc;
  282. } GH_ETH_SR_S;
  283. typedef union { /* ETH_MFBOCR */
  284. U32 all;
  285. struct {
  286. U32 nmfh : 16;
  287. U32 ovmfc : 1;
  288. U32 nmff : 11;
  289. U32 onmff : 1;
  290. U32 : 3;
  291. } bitc;
  292. } GH_ETH_MFBOCR_S;
  293. typedef union { /* ETH_IER */
  294. U32 all;
  295. struct {
  296. U32 ti : 1;
  297. U32 ts : 1;
  298. U32 tu : 1;
  299. U32 tj : 1;
  300. U32 ov : 1;
  301. U32 un : 1;
  302. U32 ri : 1;
  303. U32 ru : 1;
  304. U32 rs : 1;
  305. U32 rw : 1;
  306. U32 ete : 1;
  307. U32 : 2;
  308. U32 fbe : 1;
  309. U32 ere : 1;
  310. U32 ai : 1;
  311. U32 ni : 1;
  312. U32 : 15;
  313. } bitc;
  314. } GH_ETH_IER_S;
  315. typedef union { /* ETH_OMR */
  316. U32 all;
  317. struct {
  318. U32 : 1;
  319. U32 sr : 1;
  320. U32 osf : 1;
  321. U32 rtc : 2;
  322. U32 : 1;
  323. U32 fuf : 1;
  324. U32 fef : 1;
  325. U32 efc : 1;
  326. U32 rfa : 2;
  327. U32 rfd : 2;
  328. U32 st : 1;
  329. U32 ttc : 3;
  330. U32 : 3;
  331. U32 ftf : 1;
  332. U32 sf : 1;
  333. U32 : 10;
  334. } bitc;
  335. } GH_ETH_OMR_S;
  336. /*----------------------------------------------------------------------------*/
  337. /* mirror variables */
  338. /*----------------------------------------------------------------------------*/
  339. #ifdef __cplusplus
  340. extern "C" {
  341. #endif
  342. /*----------------------------------------------------------------------------*/
  343. /* register ETH_MCR (read/write) */
  344. /*----------------------------------------------------------------------------*/
  345. #if GH_INLINE_LEVEL == 0
  346. /*! \brief Writes the register 'ETH_MCR'. */
  347. void GH_ETH_set_MCR(U32 data);
  348. /*! \brief Reads the register 'ETH_MCR'. */
  349. U32 GH_ETH_get_MCR(void);
  350. /*! \brief Writes the bit group 'RE' of register 'ETH_MCR'. */
  351. void GH_ETH_set_MCR_RE(U8 data);
  352. /*! \brief Reads the bit group 'RE' of register 'ETH_MCR'. */
  353. U8 GH_ETH_get_MCR_RE(void);
  354. /*! \brief Writes the bit group 'TE' of register 'ETH_MCR'. */
  355. void GH_ETH_set_MCR_TE(U8 data);
  356. /*! \brief Reads the bit group 'TE' of register 'ETH_MCR'. */
  357. U8 GH_ETH_get_MCR_TE(void);
  358. /*! \brief Writes the bit group 'DC' of register 'ETH_MCR'. */
  359. void GH_ETH_set_MCR_DC(U8 data);
  360. /*! \brief Reads the bit group 'DC' of register 'ETH_MCR'. */
  361. U8 GH_ETH_get_MCR_DC(void);
  362. /*! \brief Writes the bit group 'BL' of register 'ETH_MCR'. */
  363. void GH_ETH_set_MCR_BL(U8 data);
  364. /*! \brief Reads the bit group 'BL' of register 'ETH_MCR'. */
  365. U8 GH_ETH_get_MCR_BL(void);
  366. /*! \brief Writes the bit group 'ACS' of register 'ETH_MCR'. */
  367. void GH_ETH_set_MCR_ACS(U8 data);
  368. /*! \brief Reads the bit group 'ACS' of register 'ETH_MCR'. */
  369. U8 GH_ETH_get_MCR_ACS(void);
  370. /*! \brief Writes the bit group 'LUD' of register 'ETH_MCR'. */
  371. void GH_ETH_set_MCR_LUD(U8 data);
  372. /*! \brief Reads the bit group 'LUD' of register 'ETH_MCR'. */
  373. U8 GH_ETH_get_MCR_LUD(void);
  374. /*! \brief Writes the bit group 'DR' of register 'ETH_MCR'. */
  375. void GH_ETH_set_MCR_DR(U8 data);
  376. /*! \brief Reads the bit group 'DR' of register 'ETH_MCR'. */
  377. U8 GH_ETH_get_MCR_DR(void);
  378. /*! \brief Writes the bit group 'IPC' of register 'ETH_MCR'. */
  379. void GH_ETH_set_MCR_IPC(U8 data);
  380. /*! \brief Reads the bit group 'IPC' of register 'ETH_MCR'. */
  381. U8 GH_ETH_get_MCR_IPC(void);
  382. /*! \brief Writes the bit group 'DM' of register 'ETH_MCR'. */
  383. void GH_ETH_set_MCR_DM(U8 data);
  384. /*! \brief Reads the bit group 'DM' of register 'ETH_MCR'. */
  385. U8 GH_ETH_get_MCR_DM(void);
  386. /*! \brief Writes the bit group 'LM' of register 'ETH_MCR'. */
  387. void GH_ETH_set_MCR_LM(U8 data);
  388. /*! \brief Reads the bit group 'LM' of register 'ETH_MCR'. */
  389. U8 GH_ETH_get_MCR_LM(void);
  390. /*! \brief Writes the bit group 'DRO' of register 'ETH_MCR'. */
  391. void GH_ETH_set_MCR_DRO(U8 data);
  392. /*! \brief Reads the bit group 'DRO' of register 'ETH_MCR'. */
  393. U8 GH_ETH_get_MCR_DRO(void);
  394. /*! \brief Writes the bit group 'FES' of register 'ETH_MCR'. */
  395. void GH_ETH_set_MCR_FES(U8 data);
  396. /*! \brief Reads the bit group 'FES' of register 'ETH_MCR'. */
  397. U8 GH_ETH_get_MCR_FES(void);
  398. /*! \brief Writes the bit group 'PS' of register 'ETH_MCR'. */
  399. void GH_ETH_set_MCR_PS(U8 data);
  400. /*! \brief Reads the bit group 'PS' of register 'ETH_MCR'. */
  401. U8 GH_ETH_get_MCR_PS(void);
  402. /*! \brief Writes the bit group 'DCRS' of register 'ETH_MCR'. */
  403. void GH_ETH_set_MCR_DCRS(U8 data);
  404. /*! \brief Reads the bit group 'DCRS' of register 'ETH_MCR'. */
  405. U8 GH_ETH_get_MCR_DCRS(void);
  406. /*! \brief Writes the bit group 'IFG' of register 'ETH_MCR'. */
  407. void GH_ETH_set_MCR_IFG(U8 data);
  408. /*! \brief Reads the bit group 'IFG' of register 'ETH_MCR'. */
  409. U8 GH_ETH_get_MCR_IFG(void);
  410. /*! \brief Writes the bit group 'JE' of register 'ETH_MCR'. */
  411. void GH_ETH_set_MCR_JE(U8 data);
  412. /*! \brief Reads the bit group 'JE' of register 'ETH_MCR'. */
  413. U8 GH_ETH_get_MCR_JE(void);
  414. /*! \brief Writes the bit group 'BE' of register 'ETH_MCR'. */
  415. void GH_ETH_set_MCR_BE(U8 data);
  416. /*! \brief Reads the bit group 'BE' of register 'ETH_MCR'. */
  417. U8 GH_ETH_get_MCR_BE(void);
  418. /*! \brief Writes the bit group 'JD' of register 'ETH_MCR'. */
  419. void GH_ETH_set_MCR_JD(U8 data);
  420. /*! \brief Reads the bit group 'JD' of register 'ETH_MCR'. */
  421. U8 GH_ETH_get_MCR_JD(void);
  422. /*! \brief Writes the bit group 'WD' of register 'ETH_MCR'. */
  423. void GH_ETH_set_MCR_WD(U8 data);
  424. /*! \brief Reads the bit group 'WD' of register 'ETH_MCR'. */
  425. U8 GH_ETH_get_MCR_WD(void);
  426. #else /* GH_INLINE_LEVEL == 0 */
  427. GH_INLINE void GH_ETH_set_MCR(U32 data)
  428. {
  429. *(volatile U32 *)REG_ETH_MCR = data;
  430. #if GH_ETH_ENABLE_DEBUG_PRINT
  431. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR] <-- 0x%08x\n",
  432. REG_ETH_MCR,data,data);
  433. #endif
  434. }
  435. GH_INLINE U32 GH_ETH_get_MCR(void)
  436. {
  437. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  438. #if GH_ETH_ENABLE_DEBUG_PRINT
  439. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR] --> 0x%08x\n",
  440. REG_ETH_MCR,value);
  441. #endif
  442. return value;
  443. }
  444. GH_INLINE void GH_ETH_set_MCR_RE(U8 data)
  445. {
  446. GH_ETH_MCR_S d;
  447. d.all = *(volatile U32 *)REG_ETH_MCR;
  448. d.bitc.re = data;
  449. *(volatile U32 *)REG_ETH_MCR = d.all;
  450. #if GH_ETH_ENABLE_DEBUG_PRINT
  451. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_RE] <-- 0x%08x\n",
  452. REG_ETH_MCR,d.all,d.all);
  453. #endif
  454. }
  455. GH_INLINE U8 GH_ETH_get_MCR_RE(void)
  456. {
  457. GH_ETH_MCR_S tmp_value;
  458. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  459. tmp_value.all = value;
  460. #if GH_ETH_ENABLE_DEBUG_PRINT
  461. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_RE] --> 0x%08x\n",
  462. REG_ETH_MCR,value);
  463. #endif
  464. return tmp_value.bitc.re;
  465. }
  466. GH_INLINE void GH_ETH_set_MCR_TE(U8 data)
  467. {
  468. GH_ETH_MCR_S d;
  469. d.all = *(volatile U32 *)REG_ETH_MCR;
  470. d.bitc.te = data;
  471. *(volatile U32 *)REG_ETH_MCR = d.all;
  472. #if GH_ETH_ENABLE_DEBUG_PRINT
  473. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_TE] <-- 0x%08x\n",
  474. REG_ETH_MCR,d.all,d.all);
  475. #endif
  476. }
  477. GH_INLINE U8 GH_ETH_get_MCR_TE(void)
  478. {
  479. GH_ETH_MCR_S tmp_value;
  480. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  481. tmp_value.all = value;
  482. #if GH_ETH_ENABLE_DEBUG_PRINT
  483. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_TE] --> 0x%08x\n",
  484. REG_ETH_MCR,value);
  485. #endif
  486. return tmp_value.bitc.te;
  487. }
  488. GH_INLINE void GH_ETH_set_MCR_DC(U8 data)
  489. {
  490. GH_ETH_MCR_S d;
  491. d.all = *(volatile U32 *)REG_ETH_MCR;
  492. d.bitc.dc = data;
  493. *(volatile U32 *)REG_ETH_MCR = d.all;
  494. #if GH_ETH_ENABLE_DEBUG_PRINT
  495. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_DC] <-- 0x%08x\n",
  496. REG_ETH_MCR,d.all,d.all);
  497. #endif
  498. }
  499. GH_INLINE U8 GH_ETH_get_MCR_DC(void)
  500. {
  501. GH_ETH_MCR_S tmp_value;
  502. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  503. tmp_value.all = value;
  504. #if GH_ETH_ENABLE_DEBUG_PRINT
  505. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_DC] --> 0x%08x\n",
  506. REG_ETH_MCR,value);
  507. #endif
  508. return tmp_value.bitc.dc;
  509. }
  510. GH_INLINE void GH_ETH_set_MCR_BL(U8 data)
  511. {
  512. GH_ETH_MCR_S d;
  513. d.all = *(volatile U32 *)REG_ETH_MCR;
  514. d.bitc.bl = data;
  515. *(volatile U32 *)REG_ETH_MCR = d.all;
  516. #if GH_ETH_ENABLE_DEBUG_PRINT
  517. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_BL] <-- 0x%08x\n",
  518. REG_ETH_MCR,d.all,d.all);
  519. #endif
  520. }
  521. GH_INLINE U8 GH_ETH_get_MCR_BL(void)
  522. {
  523. GH_ETH_MCR_S tmp_value;
  524. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  525. tmp_value.all = value;
  526. #if GH_ETH_ENABLE_DEBUG_PRINT
  527. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_BL] --> 0x%08x\n",
  528. REG_ETH_MCR,value);
  529. #endif
  530. return tmp_value.bitc.bl;
  531. }
  532. GH_INLINE void GH_ETH_set_MCR_ACS(U8 data)
  533. {
  534. GH_ETH_MCR_S d;
  535. d.all = *(volatile U32 *)REG_ETH_MCR;
  536. d.bitc.acs = data;
  537. *(volatile U32 *)REG_ETH_MCR = d.all;
  538. #if GH_ETH_ENABLE_DEBUG_PRINT
  539. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_ACS] <-- 0x%08x\n",
  540. REG_ETH_MCR,d.all,d.all);
  541. #endif
  542. }
  543. GH_INLINE U8 GH_ETH_get_MCR_ACS(void)
  544. {
  545. GH_ETH_MCR_S tmp_value;
  546. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  547. tmp_value.all = value;
  548. #if GH_ETH_ENABLE_DEBUG_PRINT
  549. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_ACS] --> 0x%08x\n",
  550. REG_ETH_MCR,value);
  551. #endif
  552. return tmp_value.bitc.acs;
  553. }
  554. GH_INLINE void GH_ETH_set_MCR_LUD(U8 data)
  555. {
  556. GH_ETH_MCR_S d;
  557. d.all = *(volatile U32 *)REG_ETH_MCR;
  558. d.bitc.lud = data;
  559. *(volatile U32 *)REG_ETH_MCR = d.all;
  560. #if GH_ETH_ENABLE_DEBUG_PRINT
  561. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_LUD] <-- 0x%08x\n",
  562. REG_ETH_MCR,d.all,d.all);
  563. #endif
  564. }
  565. GH_INLINE U8 GH_ETH_get_MCR_LUD(void)
  566. {
  567. GH_ETH_MCR_S tmp_value;
  568. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  569. tmp_value.all = value;
  570. #if GH_ETH_ENABLE_DEBUG_PRINT
  571. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_LUD] --> 0x%08x\n",
  572. REG_ETH_MCR,value);
  573. #endif
  574. return tmp_value.bitc.lud;
  575. }
  576. GH_INLINE void GH_ETH_set_MCR_DR(U8 data)
  577. {
  578. GH_ETH_MCR_S d;
  579. d.all = *(volatile U32 *)REG_ETH_MCR;
  580. d.bitc.dr = data;
  581. *(volatile U32 *)REG_ETH_MCR = d.all;
  582. #if GH_ETH_ENABLE_DEBUG_PRINT
  583. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_DR] <-- 0x%08x\n",
  584. REG_ETH_MCR,d.all,d.all);
  585. #endif
  586. }
  587. GH_INLINE U8 GH_ETH_get_MCR_DR(void)
  588. {
  589. GH_ETH_MCR_S tmp_value;
  590. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  591. tmp_value.all = value;
  592. #if GH_ETH_ENABLE_DEBUG_PRINT
  593. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_DR] --> 0x%08x\n",
  594. REG_ETH_MCR,value);
  595. #endif
  596. return tmp_value.bitc.dr;
  597. }
  598. GH_INLINE void GH_ETH_set_MCR_IPC(U8 data)
  599. {
  600. GH_ETH_MCR_S d;
  601. d.all = *(volatile U32 *)REG_ETH_MCR;
  602. d.bitc.ipc = data;
  603. *(volatile U32 *)REG_ETH_MCR = d.all;
  604. #if GH_ETH_ENABLE_DEBUG_PRINT
  605. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_IPC] <-- 0x%08x\n",
  606. REG_ETH_MCR,d.all,d.all);
  607. #endif
  608. }
  609. GH_INLINE U8 GH_ETH_get_MCR_IPC(void)
  610. {
  611. GH_ETH_MCR_S tmp_value;
  612. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  613. tmp_value.all = value;
  614. #if GH_ETH_ENABLE_DEBUG_PRINT
  615. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_IPC] --> 0x%08x\n",
  616. REG_ETH_MCR,value);
  617. #endif
  618. return tmp_value.bitc.ipc;
  619. }
  620. GH_INLINE void GH_ETH_set_MCR_DM(U8 data)
  621. {
  622. GH_ETH_MCR_S d;
  623. d.all = *(volatile U32 *)REG_ETH_MCR;
  624. d.bitc.dm = data;
  625. *(volatile U32 *)REG_ETH_MCR = d.all;
  626. #if GH_ETH_ENABLE_DEBUG_PRINT
  627. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_DM] <-- 0x%08x\n",
  628. REG_ETH_MCR,d.all,d.all);
  629. #endif
  630. }
  631. GH_INLINE U8 GH_ETH_get_MCR_DM(void)
  632. {
  633. GH_ETH_MCR_S tmp_value;
  634. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  635. tmp_value.all = value;
  636. #if GH_ETH_ENABLE_DEBUG_PRINT
  637. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_DM] --> 0x%08x\n",
  638. REG_ETH_MCR,value);
  639. #endif
  640. return tmp_value.bitc.dm;
  641. }
  642. GH_INLINE void GH_ETH_set_MCR_LM(U8 data)
  643. {
  644. GH_ETH_MCR_S d;
  645. d.all = *(volatile U32 *)REG_ETH_MCR;
  646. d.bitc.lm = data;
  647. *(volatile U32 *)REG_ETH_MCR = d.all;
  648. #if GH_ETH_ENABLE_DEBUG_PRINT
  649. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_LM] <-- 0x%08x\n",
  650. REG_ETH_MCR,d.all,d.all);
  651. #endif
  652. }
  653. GH_INLINE U8 GH_ETH_get_MCR_LM(void)
  654. {
  655. GH_ETH_MCR_S tmp_value;
  656. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  657. tmp_value.all = value;
  658. #if GH_ETH_ENABLE_DEBUG_PRINT
  659. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_LM] --> 0x%08x\n",
  660. REG_ETH_MCR,value);
  661. #endif
  662. return tmp_value.bitc.lm;
  663. }
  664. GH_INLINE void GH_ETH_set_MCR_DRO(U8 data)
  665. {
  666. GH_ETH_MCR_S d;
  667. d.all = *(volatile U32 *)REG_ETH_MCR;
  668. d.bitc.dro = data;
  669. *(volatile U32 *)REG_ETH_MCR = d.all;
  670. #if GH_ETH_ENABLE_DEBUG_PRINT
  671. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_DRO] <-- 0x%08x\n",
  672. REG_ETH_MCR,d.all,d.all);
  673. #endif
  674. }
  675. GH_INLINE U8 GH_ETH_get_MCR_DRO(void)
  676. {
  677. GH_ETH_MCR_S tmp_value;
  678. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  679. tmp_value.all = value;
  680. #if GH_ETH_ENABLE_DEBUG_PRINT
  681. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_DRO] --> 0x%08x\n",
  682. REG_ETH_MCR,value);
  683. #endif
  684. return tmp_value.bitc.dro;
  685. }
  686. GH_INLINE void GH_ETH_set_MCR_FES(U8 data)
  687. {
  688. GH_ETH_MCR_S d;
  689. d.all = *(volatile U32 *)REG_ETH_MCR;
  690. d.bitc.fes = data;
  691. *(volatile U32 *)REG_ETH_MCR = d.all;
  692. #if GH_ETH_ENABLE_DEBUG_PRINT
  693. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_FES] <-- 0x%08x\n",
  694. REG_ETH_MCR,d.all,d.all);
  695. #endif
  696. }
  697. GH_INLINE U8 GH_ETH_get_MCR_FES(void)
  698. {
  699. GH_ETH_MCR_S tmp_value;
  700. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  701. tmp_value.all = value;
  702. #if GH_ETH_ENABLE_DEBUG_PRINT
  703. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_FES] --> 0x%08x\n",
  704. REG_ETH_MCR,value);
  705. #endif
  706. return tmp_value.bitc.fes;
  707. }
  708. GH_INLINE void GH_ETH_set_MCR_PS(U8 data)
  709. {
  710. GH_ETH_MCR_S d;
  711. d.all = *(volatile U32 *)REG_ETH_MCR;
  712. d.bitc.ps = data;
  713. *(volatile U32 *)REG_ETH_MCR = d.all;
  714. #if GH_ETH_ENABLE_DEBUG_PRINT
  715. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_PS] <-- 0x%08x\n",
  716. REG_ETH_MCR,d.all,d.all);
  717. #endif
  718. }
  719. GH_INLINE U8 GH_ETH_get_MCR_PS(void)
  720. {
  721. GH_ETH_MCR_S tmp_value;
  722. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  723. tmp_value.all = value;
  724. #if GH_ETH_ENABLE_DEBUG_PRINT
  725. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_PS] --> 0x%08x\n",
  726. REG_ETH_MCR,value);
  727. #endif
  728. return tmp_value.bitc.ps;
  729. }
  730. GH_INLINE void GH_ETH_set_MCR_DCRS(U8 data)
  731. {
  732. GH_ETH_MCR_S d;
  733. d.all = *(volatile U32 *)REG_ETH_MCR;
  734. d.bitc.dcrs = data;
  735. *(volatile U32 *)REG_ETH_MCR = d.all;
  736. #if GH_ETH_ENABLE_DEBUG_PRINT
  737. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_DCRS] <-- 0x%08x\n",
  738. REG_ETH_MCR,d.all,d.all);
  739. #endif
  740. }
  741. GH_INLINE U8 GH_ETH_get_MCR_DCRS(void)
  742. {
  743. GH_ETH_MCR_S tmp_value;
  744. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  745. tmp_value.all = value;
  746. #if GH_ETH_ENABLE_DEBUG_PRINT
  747. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_DCRS] --> 0x%08x\n",
  748. REG_ETH_MCR,value);
  749. #endif
  750. return tmp_value.bitc.dcrs;
  751. }
  752. GH_INLINE void GH_ETH_set_MCR_IFG(U8 data)
  753. {
  754. GH_ETH_MCR_S d;
  755. d.all = *(volatile U32 *)REG_ETH_MCR;
  756. d.bitc.ifg = data;
  757. *(volatile U32 *)REG_ETH_MCR = d.all;
  758. #if GH_ETH_ENABLE_DEBUG_PRINT
  759. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_IFG] <-- 0x%08x\n",
  760. REG_ETH_MCR,d.all,d.all);
  761. #endif
  762. }
  763. GH_INLINE U8 GH_ETH_get_MCR_IFG(void)
  764. {
  765. GH_ETH_MCR_S tmp_value;
  766. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  767. tmp_value.all = value;
  768. #if GH_ETH_ENABLE_DEBUG_PRINT
  769. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_IFG] --> 0x%08x\n",
  770. REG_ETH_MCR,value);
  771. #endif
  772. return tmp_value.bitc.ifg;
  773. }
  774. GH_INLINE void GH_ETH_set_MCR_JE(U8 data)
  775. {
  776. GH_ETH_MCR_S d;
  777. d.all = *(volatile U32 *)REG_ETH_MCR;
  778. d.bitc.je = data;
  779. *(volatile U32 *)REG_ETH_MCR = d.all;
  780. #if GH_ETH_ENABLE_DEBUG_PRINT
  781. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_JE] <-- 0x%08x\n",
  782. REG_ETH_MCR,d.all,d.all);
  783. #endif
  784. }
  785. GH_INLINE U8 GH_ETH_get_MCR_JE(void)
  786. {
  787. GH_ETH_MCR_S tmp_value;
  788. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  789. tmp_value.all = value;
  790. #if GH_ETH_ENABLE_DEBUG_PRINT
  791. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_JE] --> 0x%08x\n",
  792. REG_ETH_MCR,value);
  793. #endif
  794. return tmp_value.bitc.je;
  795. }
  796. GH_INLINE void GH_ETH_set_MCR_BE(U8 data)
  797. {
  798. GH_ETH_MCR_S d;
  799. d.all = *(volatile U32 *)REG_ETH_MCR;
  800. d.bitc.be = data;
  801. *(volatile U32 *)REG_ETH_MCR = d.all;
  802. #if GH_ETH_ENABLE_DEBUG_PRINT
  803. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_BE] <-- 0x%08x\n",
  804. REG_ETH_MCR,d.all,d.all);
  805. #endif
  806. }
  807. GH_INLINE U8 GH_ETH_get_MCR_BE(void)
  808. {
  809. GH_ETH_MCR_S tmp_value;
  810. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  811. tmp_value.all = value;
  812. #if GH_ETH_ENABLE_DEBUG_PRINT
  813. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_BE] --> 0x%08x\n",
  814. REG_ETH_MCR,value);
  815. #endif
  816. return tmp_value.bitc.be;
  817. }
  818. GH_INLINE void GH_ETH_set_MCR_JD(U8 data)
  819. {
  820. GH_ETH_MCR_S d;
  821. d.all = *(volatile U32 *)REG_ETH_MCR;
  822. d.bitc.jd = data;
  823. *(volatile U32 *)REG_ETH_MCR = d.all;
  824. #if GH_ETH_ENABLE_DEBUG_PRINT
  825. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_JD] <-- 0x%08x\n",
  826. REG_ETH_MCR,d.all,d.all);
  827. #endif
  828. }
  829. GH_INLINE U8 GH_ETH_get_MCR_JD(void)
  830. {
  831. GH_ETH_MCR_S tmp_value;
  832. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  833. tmp_value.all = value;
  834. #if GH_ETH_ENABLE_DEBUG_PRINT
  835. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_JD] --> 0x%08x\n",
  836. REG_ETH_MCR,value);
  837. #endif
  838. return tmp_value.bitc.jd;
  839. }
  840. GH_INLINE void GH_ETH_set_MCR_WD(U8 data)
  841. {
  842. GH_ETH_MCR_S d;
  843. d.all = *(volatile U32 *)REG_ETH_MCR;
  844. d.bitc.wd = data;
  845. *(volatile U32 *)REG_ETH_MCR = d.all;
  846. #if GH_ETH_ENABLE_DEBUG_PRINT
  847. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MCR_WD] <-- 0x%08x\n",
  848. REG_ETH_MCR,d.all,d.all);
  849. #endif
  850. }
  851. GH_INLINE U8 GH_ETH_get_MCR_WD(void)
  852. {
  853. GH_ETH_MCR_S tmp_value;
  854. U32 value = (*(volatile U32 *)REG_ETH_MCR);
  855. tmp_value.all = value;
  856. #if GH_ETH_ENABLE_DEBUG_PRINT
  857. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MCR_WD] --> 0x%08x\n",
  858. REG_ETH_MCR,value);
  859. #endif
  860. return tmp_value.bitc.wd;
  861. }
  862. #endif /* GH_INLINE_LEVEL == 0 */
  863. /*----------------------------------------------------------------------------*/
  864. /* register ETH_GAR (read/write) */
  865. /*----------------------------------------------------------------------------*/
  866. #if GH_INLINE_LEVEL == 0
  867. /*! \brief Writes the register 'ETH_GAR'. */
  868. void GH_ETH_set_GAR(U32 data);
  869. /*! \brief Reads the register 'ETH_GAR'. */
  870. U32 GH_ETH_get_GAR(void);
  871. /*! \brief Writes the bit group 'GB' of register 'ETH_GAR'. */
  872. void GH_ETH_set_GAR_GB(U8 data);
  873. /*! \brief Reads the bit group 'GB' of register 'ETH_GAR'. */
  874. U8 GH_ETH_get_GAR_GB(void);
  875. /*! \brief Writes the bit group 'GW' of register 'ETH_GAR'. */
  876. void GH_ETH_set_GAR_GW(U8 data);
  877. /*! \brief Reads the bit group 'GW' of register 'ETH_GAR'. */
  878. U8 GH_ETH_get_GAR_GW(void);
  879. /*! \brief Writes the bit group 'CR' of register 'ETH_GAR'. */
  880. void GH_ETH_set_GAR_CR(U8 data);
  881. /*! \brief Reads the bit group 'CR' of register 'ETH_GAR'. */
  882. U8 GH_ETH_get_GAR_CR(void);
  883. /*! \brief Writes the bit group 'GR' of register 'ETH_GAR'. */
  884. void GH_ETH_set_GAR_GR(U8 data);
  885. /*! \brief Reads the bit group 'GR' of register 'ETH_GAR'. */
  886. U8 GH_ETH_get_GAR_GR(void);
  887. /*! \brief Writes the bit group 'PA' of register 'ETH_GAR'. */
  888. void GH_ETH_set_GAR_PA(U8 data);
  889. /*! \brief Reads the bit group 'PA' of register 'ETH_GAR'. */
  890. U8 GH_ETH_get_GAR_PA(void);
  891. #else /* GH_INLINE_LEVEL == 0 */
  892. GH_INLINE void GH_ETH_set_GAR(U32 data)
  893. {
  894. *(volatile U32 *)REG_ETH_GAR = data;
  895. #if GH_ETH_ENABLE_DEBUG_PRINT
  896. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GAR] <-- 0x%08x\n",
  897. REG_ETH_GAR,data,data);
  898. #endif
  899. }
  900. GH_INLINE U32 GH_ETH_get_GAR(void)
  901. {
  902. U32 value = (*(volatile U32 *)REG_ETH_GAR);
  903. #if GH_ETH_ENABLE_DEBUG_PRINT
  904. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GAR] --> 0x%08x\n",
  905. REG_ETH_GAR,value);
  906. #endif
  907. return value;
  908. }
  909. GH_INLINE void GH_ETH_set_GAR_GB(U8 data)
  910. {
  911. GH_ETH_GAR_S d;
  912. d.all = *(volatile U32 *)REG_ETH_GAR;
  913. d.bitc.gb = data;
  914. *(volatile U32 *)REG_ETH_GAR = d.all;
  915. #if GH_ETH_ENABLE_DEBUG_PRINT
  916. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GAR_GB] <-- 0x%08x\n",
  917. REG_ETH_GAR,d.all,d.all);
  918. #endif
  919. }
  920. GH_INLINE U8 GH_ETH_get_GAR_GB(void)
  921. {
  922. GH_ETH_GAR_S tmp_value;
  923. U32 value = (*(volatile U32 *)REG_ETH_GAR);
  924. tmp_value.all = value;
  925. #if GH_ETH_ENABLE_DEBUG_PRINT
  926. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GAR_GB] --> 0x%08x\n",
  927. REG_ETH_GAR,value);
  928. #endif
  929. return tmp_value.bitc.gb;
  930. }
  931. GH_INLINE void GH_ETH_set_GAR_GW(U8 data)
  932. {
  933. GH_ETH_GAR_S d;
  934. d.all = *(volatile U32 *)REG_ETH_GAR;
  935. d.bitc.gw = data;
  936. *(volatile U32 *)REG_ETH_GAR = d.all;
  937. #if GH_ETH_ENABLE_DEBUG_PRINT
  938. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GAR_GW] <-- 0x%08x\n",
  939. REG_ETH_GAR,d.all,d.all);
  940. #endif
  941. }
  942. GH_INLINE U8 GH_ETH_get_GAR_GW(void)
  943. {
  944. GH_ETH_GAR_S tmp_value;
  945. U32 value = (*(volatile U32 *)REG_ETH_GAR);
  946. tmp_value.all = value;
  947. #if GH_ETH_ENABLE_DEBUG_PRINT
  948. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GAR_GW] --> 0x%08x\n",
  949. REG_ETH_GAR,value);
  950. #endif
  951. return tmp_value.bitc.gw;
  952. }
  953. GH_INLINE void GH_ETH_set_GAR_CR(U8 data)
  954. {
  955. GH_ETH_GAR_S d;
  956. d.all = *(volatile U32 *)REG_ETH_GAR;
  957. d.bitc.cr = data;
  958. *(volatile U32 *)REG_ETH_GAR = d.all;
  959. #if GH_ETH_ENABLE_DEBUG_PRINT
  960. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GAR_CR] <-- 0x%08x\n",
  961. REG_ETH_GAR,d.all,d.all);
  962. #endif
  963. }
  964. GH_INLINE U8 GH_ETH_get_GAR_CR(void)
  965. {
  966. GH_ETH_GAR_S tmp_value;
  967. U32 value = (*(volatile U32 *)REG_ETH_GAR);
  968. tmp_value.all = value;
  969. #if GH_ETH_ENABLE_DEBUG_PRINT
  970. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GAR_CR] --> 0x%08x\n",
  971. REG_ETH_GAR,value);
  972. #endif
  973. return tmp_value.bitc.cr;
  974. }
  975. GH_INLINE void GH_ETH_set_GAR_GR(U8 data)
  976. {
  977. GH_ETH_GAR_S d;
  978. d.all = *(volatile U32 *)REG_ETH_GAR;
  979. d.bitc.gr = data;
  980. *(volatile U32 *)REG_ETH_GAR = d.all;
  981. #if GH_ETH_ENABLE_DEBUG_PRINT
  982. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GAR_GR] <-- 0x%08x\n",
  983. REG_ETH_GAR,d.all,d.all);
  984. #endif
  985. }
  986. GH_INLINE U8 GH_ETH_get_GAR_GR(void)
  987. {
  988. GH_ETH_GAR_S tmp_value;
  989. U32 value = (*(volatile U32 *)REG_ETH_GAR);
  990. tmp_value.all = value;
  991. #if GH_ETH_ENABLE_DEBUG_PRINT
  992. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GAR_GR] --> 0x%08x\n",
  993. REG_ETH_GAR,value);
  994. #endif
  995. return tmp_value.bitc.gr;
  996. }
  997. GH_INLINE void GH_ETH_set_GAR_PA(U8 data)
  998. {
  999. GH_ETH_GAR_S d;
  1000. d.all = *(volatile U32 *)REG_ETH_GAR;
  1001. d.bitc.pa = data;
  1002. *(volatile U32 *)REG_ETH_GAR = d.all;
  1003. #if GH_ETH_ENABLE_DEBUG_PRINT
  1004. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GAR_PA] <-- 0x%08x\n",
  1005. REG_ETH_GAR,d.all,d.all);
  1006. #endif
  1007. }
  1008. GH_INLINE U8 GH_ETH_get_GAR_PA(void)
  1009. {
  1010. GH_ETH_GAR_S tmp_value;
  1011. U32 value = (*(volatile U32 *)REG_ETH_GAR);
  1012. tmp_value.all = value;
  1013. #if GH_ETH_ENABLE_DEBUG_PRINT
  1014. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GAR_PA] --> 0x%08x\n",
  1015. REG_ETH_GAR,value);
  1016. #endif
  1017. return tmp_value.bitc.pa;
  1018. }
  1019. #endif /* GH_INLINE_LEVEL == 0 */
  1020. /*----------------------------------------------------------------------------*/
  1021. /* register ETH_GDR (read/write) */
  1022. /*----------------------------------------------------------------------------*/
  1023. #if GH_INLINE_LEVEL == 0
  1024. /*! \brief Writes the register 'ETH_GDR'. */
  1025. void GH_ETH_set_GDR(U32 data);
  1026. /*! \brief Reads the register 'ETH_GDR'. */
  1027. U32 GH_ETH_get_GDR(void);
  1028. /*! \brief Writes the bit group 'GD' of register 'ETH_GDR'. */
  1029. void GH_ETH_set_GDR_GD(U16 data);
  1030. /*! \brief Reads the bit group 'GD' of register 'ETH_GDR'. */
  1031. U16 GH_ETH_get_GDR_GD(void);
  1032. #else /* GH_INLINE_LEVEL == 0 */
  1033. GH_INLINE void GH_ETH_set_GDR(U32 data)
  1034. {
  1035. *(volatile U32 *)REG_ETH_GDR = data;
  1036. #if GH_ETH_ENABLE_DEBUG_PRINT
  1037. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GDR] <-- 0x%08x\n",
  1038. REG_ETH_GDR,data,data);
  1039. #endif
  1040. }
  1041. GH_INLINE U32 GH_ETH_get_GDR(void)
  1042. {
  1043. U32 value = (*(volatile U32 *)REG_ETH_GDR);
  1044. #if GH_ETH_ENABLE_DEBUG_PRINT
  1045. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GDR] --> 0x%08x\n",
  1046. REG_ETH_GDR,value);
  1047. #endif
  1048. return value;
  1049. }
  1050. GH_INLINE void GH_ETH_set_GDR_GD(U16 data)
  1051. {
  1052. GH_ETH_GDR_S d;
  1053. d.all = *(volatile U32 *)REG_ETH_GDR;
  1054. d.bitc.gd = data;
  1055. *(volatile U32 *)REG_ETH_GDR = d.all;
  1056. #if GH_ETH_ENABLE_DEBUG_PRINT
  1057. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_GDR_GD] <-- 0x%08x\n",
  1058. REG_ETH_GDR,d.all,d.all);
  1059. #endif
  1060. }
  1061. GH_INLINE U16 GH_ETH_get_GDR_GD(void)
  1062. {
  1063. GH_ETH_GDR_S tmp_value;
  1064. U32 value = (*(volatile U32 *)REG_ETH_GDR);
  1065. tmp_value.all = value;
  1066. #if GH_ETH_ENABLE_DEBUG_PRINT
  1067. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_GDR_GD] --> 0x%08x\n",
  1068. REG_ETH_GDR,value);
  1069. #endif
  1070. return tmp_value.bitc.gd;
  1071. }
  1072. #endif /* GH_INLINE_LEVEL == 0 */
  1073. /*----------------------------------------------------------------------------*/
  1074. /* register ETH_MFFR (read/write) */
  1075. /*----------------------------------------------------------------------------*/
  1076. #if GH_INLINE_LEVEL == 0
  1077. /*! \brief Writes the register 'ETH_MFFR'. */
  1078. void GH_ETH_set_MFFR(U32 data);
  1079. /*! \brief Reads the register 'ETH_MFFR'. */
  1080. U32 GH_ETH_get_MFFR(void);
  1081. /*! \brief Writes the bit group 'PR' of register 'ETH_MFFR'. */
  1082. void GH_ETH_set_MFFR_PR(U8 data);
  1083. /*! \brief Reads the bit group 'PR' of register 'ETH_MFFR'. */
  1084. U8 GH_ETH_get_MFFR_PR(void);
  1085. /*! \brief Writes the bit group 'HUC' of register 'ETH_MFFR'. */
  1086. void GH_ETH_set_MFFR_HUC(U8 data);
  1087. /*! \brief Reads the bit group 'HUC' of register 'ETH_MFFR'. */
  1088. U8 GH_ETH_get_MFFR_HUC(void);
  1089. /*! \brief Writes the bit group 'HMC' of register 'ETH_MFFR'. */
  1090. void GH_ETH_set_MFFR_HMC(U8 data);
  1091. /*! \brief Reads the bit group 'HMC' of register 'ETH_MFFR'. */
  1092. U8 GH_ETH_get_MFFR_HMC(void);
  1093. /*! \brief Writes the bit group 'IFT' of register 'ETH_MFFR'. */
  1094. void GH_ETH_set_MFFR_IFT(U8 data);
  1095. /*! \brief Reads the bit group 'IFT' of register 'ETH_MFFR'. */
  1096. U8 GH_ETH_get_MFFR_IFT(void);
  1097. /*! \brief Writes the bit group 'PM' of register 'ETH_MFFR'. */
  1098. void GH_ETH_set_MFFR_PM(U8 data);
  1099. /*! \brief Reads the bit group 'PM' of register 'ETH_MFFR'. */
  1100. U8 GH_ETH_get_MFFR_PM(void);
  1101. /*! \brief Writes the bit group 'DB' of register 'ETH_MFFR'. */
  1102. void GH_ETH_set_MFFR_DB(U8 data);
  1103. /*! \brief Reads the bit group 'DB' of register 'ETH_MFFR'. */
  1104. U8 GH_ETH_get_MFFR_DB(void);
  1105. /*! \brief Writes the bit group 'PCF' of register 'ETH_MFFR'. */
  1106. void GH_ETH_set_MFFR_PCF(U8 data);
  1107. /*! \brief Reads the bit group 'PCF' of register 'ETH_MFFR'. */
  1108. U8 GH_ETH_get_MFFR_PCF(void);
  1109. /*! \brief Writes the bit group 'SAIF' of register 'ETH_MFFR'. */
  1110. void GH_ETH_set_MFFR_SAIF(U8 data);
  1111. /*! \brief Reads the bit group 'SAIF' of register 'ETH_MFFR'. */
  1112. U8 GH_ETH_get_MFFR_SAIF(void);
  1113. /*! \brief Writes the bit group 'SAF' of register 'ETH_MFFR'. */
  1114. void GH_ETH_set_MFFR_SAF(U8 data);
  1115. /*! \brief Reads the bit group 'SAF' of register 'ETH_MFFR'. */
  1116. U8 GH_ETH_get_MFFR_SAF(void);
  1117. /*! \brief Writes the bit group 'HPF' of register 'ETH_MFFR'. */
  1118. void GH_ETH_set_MFFR_HPF(U8 data);
  1119. /*! \brief Reads the bit group 'HPF' of register 'ETH_MFFR'. */
  1120. U8 GH_ETH_get_MFFR_HPF(void);
  1121. /*! \brief Writes the bit group 'RA' of register 'ETH_MFFR'. */
  1122. void GH_ETH_set_MFFR_RA(U8 data);
  1123. /*! \brief Reads the bit group 'RA' of register 'ETH_MFFR'. */
  1124. U8 GH_ETH_get_MFFR_RA(void);
  1125. #else /* GH_INLINE_LEVEL == 0 */
  1126. GH_INLINE void GH_ETH_set_MFFR(U32 data)
  1127. {
  1128. *(volatile U32 *)REG_ETH_MFFR = data;
  1129. #if GH_ETH_ENABLE_DEBUG_PRINT
  1130. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR] <-- 0x%08x\n",
  1131. REG_ETH_MFFR,data,data);
  1132. #endif
  1133. }
  1134. GH_INLINE U32 GH_ETH_get_MFFR(void)
  1135. {
  1136. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1137. #if GH_ETH_ENABLE_DEBUG_PRINT
  1138. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR] --> 0x%08x\n",
  1139. REG_ETH_MFFR,value);
  1140. #endif
  1141. return value;
  1142. }
  1143. GH_INLINE void GH_ETH_set_MFFR_PR(U8 data)
  1144. {
  1145. GH_ETH_MFFR_S d;
  1146. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1147. d.bitc.pr = data;
  1148. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1149. #if GH_ETH_ENABLE_DEBUG_PRINT
  1150. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_PR] <-- 0x%08x\n",
  1151. REG_ETH_MFFR,d.all,d.all);
  1152. #endif
  1153. }
  1154. GH_INLINE U8 GH_ETH_get_MFFR_PR(void)
  1155. {
  1156. GH_ETH_MFFR_S tmp_value;
  1157. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1158. tmp_value.all = value;
  1159. #if GH_ETH_ENABLE_DEBUG_PRINT
  1160. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_PR] --> 0x%08x\n",
  1161. REG_ETH_MFFR,value);
  1162. #endif
  1163. return tmp_value.bitc.pr;
  1164. }
  1165. GH_INLINE void GH_ETH_set_MFFR_HUC(U8 data)
  1166. {
  1167. GH_ETH_MFFR_S d;
  1168. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1169. d.bitc.huc = data;
  1170. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1171. #if GH_ETH_ENABLE_DEBUG_PRINT
  1172. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_HUC] <-- 0x%08x\n",
  1173. REG_ETH_MFFR,d.all,d.all);
  1174. #endif
  1175. }
  1176. GH_INLINE U8 GH_ETH_get_MFFR_HUC(void)
  1177. {
  1178. GH_ETH_MFFR_S tmp_value;
  1179. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1180. tmp_value.all = value;
  1181. #if GH_ETH_ENABLE_DEBUG_PRINT
  1182. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_HUC] --> 0x%08x\n",
  1183. REG_ETH_MFFR,value);
  1184. #endif
  1185. return tmp_value.bitc.huc;
  1186. }
  1187. GH_INLINE void GH_ETH_set_MFFR_HMC(U8 data)
  1188. {
  1189. GH_ETH_MFFR_S d;
  1190. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1191. d.bitc.hmc = data;
  1192. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1193. #if GH_ETH_ENABLE_DEBUG_PRINT
  1194. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_HMC] <-- 0x%08x\n",
  1195. REG_ETH_MFFR,d.all,d.all);
  1196. #endif
  1197. }
  1198. GH_INLINE U8 GH_ETH_get_MFFR_HMC(void)
  1199. {
  1200. GH_ETH_MFFR_S tmp_value;
  1201. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1202. tmp_value.all = value;
  1203. #if GH_ETH_ENABLE_DEBUG_PRINT
  1204. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_HMC] --> 0x%08x\n",
  1205. REG_ETH_MFFR,value);
  1206. #endif
  1207. return tmp_value.bitc.hmc;
  1208. }
  1209. GH_INLINE void GH_ETH_set_MFFR_IFT(U8 data)
  1210. {
  1211. GH_ETH_MFFR_S d;
  1212. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1213. d.bitc.ift = data;
  1214. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1215. #if GH_ETH_ENABLE_DEBUG_PRINT
  1216. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_IFT] <-- 0x%08x\n",
  1217. REG_ETH_MFFR,d.all,d.all);
  1218. #endif
  1219. }
  1220. GH_INLINE U8 GH_ETH_get_MFFR_IFT(void)
  1221. {
  1222. GH_ETH_MFFR_S tmp_value;
  1223. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1224. tmp_value.all = value;
  1225. #if GH_ETH_ENABLE_DEBUG_PRINT
  1226. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_IFT] --> 0x%08x\n",
  1227. REG_ETH_MFFR,value);
  1228. #endif
  1229. return tmp_value.bitc.ift;
  1230. }
  1231. GH_INLINE void GH_ETH_set_MFFR_PM(U8 data)
  1232. {
  1233. GH_ETH_MFFR_S d;
  1234. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1235. d.bitc.pm = data;
  1236. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1237. #if GH_ETH_ENABLE_DEBUG_PRINT
  1238. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_PM] <-- 0x%08x\n",
  1239. REG_ETH_MFFR,d.all,d.all);
  1240. #endif
  1241. }
  1242. GH_INLINE U8 GH_ETH_get_MFFR_PM(void)
  1243. {
  1244. GH_ETH_MFFR_S tmp_value;
  1245. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1246. tmp_value.all = value;
  1247. #if GH_ETH_ENABLE_DEBUG_PRINT
  1248. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_PM] --> 0x%08x\n",
  1249. REG_ETH_MFFR,value);
  1250. #endif
  1251. return tmp_value.bitc.pm;
  1252. }
  1253. GH_INLINE void GH_ETH_set_MFFR_DB(U8 data)
  1254. {
  1255. GH_ETH_MFFR_S d;
  1256. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1257. d.bitc.db = data;
  1258. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1259. #if GH_ETH_ENABLE_DEBUG_PRINT
  1260. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_DB] <-- 0x%08x\n",
  1261. REG_ETH_MFFR,d.all,d.all);
  1262. #endif
  1263. }
  1264. GH_INLINE U8 GH_ETH_get_MFFR_DB(void)
  1265. {
  1266. GH_ETH_MFFR_S tmp_value;
  1267. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1268. tmp_value.all = value;
  1269. #if GH_ETH_ENABLE_DEBUG_PRINT
  1270. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_DB] --> 0x%08x\n",
  1271. REG_ETH_MFFR,value);
  1272. #endif
  1273. return tmp_value.bitc.db;
  1274. }
  1275. GH_INLINE void GH_ETH_set_MFFR_PCF(U8 data)
  1276. {
  1277. GH_ETH_MFFR_S d;
  1278. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1279. d.bitc.pcf = data;
  1280. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1281. #if GH_ETH_ENABLE_DEBUG_PRINT
  1282. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_PCF] <-- 0x%08x\n",
  1283. REG_ETH_MFFR,d.all,d.all);
  1284. #endif
  1285. }
  1286. GH_INLINE U8 GH_ETH_get_MFFR_PCF(void)
  1287. {
  1288. GH_ETH_MFFR_S tmp_value;
  1289. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1290. tmp_value.all = value;
  1291. #if GH_ETH_ENABLE_DEBUG_PRINT
  1292. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_PCF] --> 0x%08x\n",
  1293. REG_ETH_MFFR,value);
  1294. #endif
  1295. return tmp_value.bitc.pcf;
  1296. }
  1297. GH_INLINE void GH_ETH_set_MFFR_SAIF(U8 data)
  1298. {
  1299. GH_ETH_MFFR_S d;
  1300. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1301. d.bitc.saif = data;
  1302. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1303. #if GH_ETH_ENABLE_DEBUG_PRINT
  1304. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_SAIF] <-- 0x%08x\n",
  1305. REG_ETH_MFFR,d.all,d.all);
  1306. #endif
  1307. }
  1308. GH_INLINE U8 GH_ETH_get_MFFR_SAIF(void)
  1309. {
  1310. GH_ETH_MFFR_S tmp_value;
  1311. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1312. tmp_value.all = value;
  1313. #if GH_ETH_ENABLE_DEBUG_PRINT
  1314. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_SAIF] --> 0x%08x\n",
  1315. REG_ETH_MFFR,value);
  1316. #endif
  1317. return tmp_value.bitc.saif;
  1318. }
  1319. GH_INLINE void GH_ETH_set_MFFR_SAF(U8 data)
  1320. {
  1321. GH_ETH_MFFR_S d;
  1322. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1323. d.bitc.saf = data;
  1324. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1325. #if GH_ETH_ENABLE_DEBUG_PRINT
  1326. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_SAF] <-- 0x%08x\n",
  1327. REG_ETH_MFFR,d.all,d.all);
  1328. #endif
  1329. }
  1330. GH_INLINE U8 GH_ETH_get_MFFR_SAF(void)
  1331. {
  1332. GH_ETH_MFFR_S tmp_value;
  1333. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1334. tmp_value.all = value;
  1335. #if GH_ETH_ENABLE_DEBUG_PRINT
  1336. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_SAF] --> 0x%08x\n",
  1337. REG_ETH_MFFR,value);
  1338. #endif
  1339. return tmp_value.bitc.saf;
  1340. }
  1341. GH_INLINE void GH_ETH_set_MFFR_HPF(U8 data)
  1342. {
  1343. GH_ETH_MFFR_S d;
  1344. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1345. d.bitc.hpf = data;
  1346. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1347. #if GH_ETH_ENABLE_DEBUG_PRINT
  1348. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_HPF] <-- 0x%08x\n",
  1349. REG_ETH_MFFR,d.all,d.all);
  1350. #endif
  1351. }
  1352. GH_INLINE U8 GH_ETH_get_MFFR_HPF(void)
  1353. {
  1354. GH_ETH_MFFR_S tmp_value;
  1355. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1356. tmp_value.all = value;
  1357. #if GH_ETH_ENABLE_DEBUG_PRINT
  1358. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_HPF] --> 0x%08x\n",
  1359. REG_ETH_MFFR,value);
  1360. #endif
  1361. return tmp_value.bitc.hpf;
  1362. }
  1363. GH_INLINE void GH_ETH_set_MFFR_RA(U8 data)
  1364. {
  1365. GH_ETH_MFFR_S d;
  1366. d.all = *(volatile U32 *)REG_ETH_MFFR;
  1367. d.bitc.ra = data;
  1368. *(volatile U32 *)REG_ETH_MFFR = d.all;
  1369. #if GH_ETH_ENABLE_DEBUG_PRINT
  1370. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFFR_RA] <-- 0x%08x\n",
  1371. REG_ETH_MFFR,d.all,d.all);
  1372. #endif
  1373. }
  1374. GH_INLINE U8 GH_ETH_get_MFFR_RA(void)
  1375. {
  1376. GH_ETH_MFFR_S tmp_value;
  1377. U32 value = (*(volatile U32 *)REG_ETH_MFFR);
  1378. tmp_value.all = value;
  1379. #if GH_ETH_ENABLE_DEBUG_PRINT
  1380. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFFR_RA] --> 0x%08x\n",
  1381. REG_ETH_MFFR,value);
  1382. #endif
  1383. return tmp_value.bitc.ra;
  1384. }
  1385. #endif /* GH_INLINE_LEVEL == 0 */
  1386. /*----------------------------------------------------------------------------*/
  1387. /* register ETH_MHTRH (read/write) */
  1388. /*----------------------------------------------------------------------------*/
  1389. #if GH_INLINE_LEVEL == 0
  1390. /*! \brief Writes the register 'ETH_MHTRH'. */
  1391. void GH_ETH_set_MHTRH(U32 data);
  1392. /*! \brief Reads the register 'ETH_MHTRH'. */
  1393. U32 GH_ETH_get_MHTRH(void);
  1394. /*! \brief Writes the bit group 'HTH' of register 'ETH_MHTRH'. */
  1395. void GH_ETH_set_MHTRH_HTH(U32 data);
  1396. /*! \brief Reads the bit group 'HTH' of register 'ETH_MHTRH'. */
  1397. U32 GH_ETH_get_MHTRH_HTH(void);
  1398. #else /* GH_INLINE_LEVEL == 0 */
  1399. GH_INLINE void GH_ETH_set_MHTRH(U32 data)
  1400. {
  1401. *(volatile U32 *)REG_ETH_MHTRH = data;
  1402. #if GH_ETH_ENABLE_DEBUG_PRINT
  1403. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MHTRH] <-- 0x%08x\n",
  1404. REG_ETH_MHTRH,data,data);
  1405. #endif
  1406. }
  1407. GH_INLINE U32 GH_ETH_get_MHTRH(void)
  1408. {
  1409. U32 value = (*(volatile U32 *)REG_ETH_MHTRH);
  1410. #if GH_ETH_ENABLE_DEBUG_PRINT
  1411. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MHTRH] --> 0x%08x\n",
  1412. REG_ETH_MHTRH,value);
  1413. #endif
  1414. return value;
  1415. }
  1416. GH_INLINE void GH_ETH_set_MHTRH_HTH(U32 data)
  1417. {
  1418. GH_ETH_MHTRH_S d;
  1419. d.all = *(volatile U32 *)REG_ETH_MHTRH;
  1420. d.bitc.hth = data;
  1421. *(volatile U32 *)REG_ETH_MHTRH = d.all;
  1422. #if GH_ETH_ENABLE_DEBUG_PRINT
  1423. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MHTRH_HTH] <-- 0x%08x\n",
  1424. REG_ETH_MHTRH,d.all,d.all);
  1425. #endif
  1426. }
  1427. GH_INLINE U32 GH_ETH_get_MHTRH_HTH(void)
  1428. {
  1429. GH_ETH_MHTRH_S tmp_value;
  1430. U32 value = (*(volatile U32 *)REG_ETH_MHTRH);
  1431. tmp_value.all = value;
  1432. #if GH_ETH_ENABLE_DEBUG_PRINT
  1433. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MHTRH_HTH] --> 0x%08x\n",
  1434. REG_ETH_MHTRH,value);
  1435. #endif
  1436. return tmp_value.bitc.hth;
  1437. }
  1438. #endif /* GH_INLINE_LEVEL == 0 */
  1439. /*----------------------------------------------------------------------------*/
  1440. /* register ETH_MHTRL (read/write) */
  1441. /*----------------------------------------------------------------------------*/
  1442. #if GH_INLINE_LEVEL == 0
  1443. /*! \brief Writes the register 'ETH_MHTRL'. */
  1444. void GH_ETH_set_MHTRL(U32 data);
  1445. /*! \brief Reads the register 'ETH_MHTRL'. */
  1446. U32 GH_ETH_get_MHTRL(void);
  1447. /*! \brief Writes the bit group 'HTL' of register 'ETH_MHTRL'. */
  1448. void GH_ETH_set_MHTRL_HTL(U32 data);
  1449. /*! \brief Reads the bit group 'HTL' of register 'ETH_MHTRL'. */
  1450. U32 GH_ETH_get_MHTRL_HTL(void);
  1451. #else /* GH_INLINE_LEVEL == 0 */
  1452. GH_INLINE void GH_ETH_set_MHTRL(U32 data)
  1453. {
  1454. *(volatile U32 *)REG_ETH_MHTRL = data;
  1455. #if GH_ETH_ENABLE_DEBUG_PRINT
  1456. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MHTRL] <-- 0x%08x\n",
  1457. REG_ETH_MHTRL,data,data);
  1458. #endif
  1459. }
  1460. GH_INLINE U32 GH_ETH_get_MHTRL(void)
  1461. {
  1462. U32 value = (*(volatile U32 *)REG_ETH_MHTRL);
  1463. #if GH_ETH_ENABLE_DEBUG_PRINT
  1464. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MHTRL] --> 0x%08x\n",
  1465. REG_ETH_MHTRL,value);
  1466. #endif
  1467. return value;
  1468. }
  1469. GH_INLINE void GH_ETH_set_MHTRL_HTL(U32 data)
  1470. {
  1471. GH_ETH_MHTRL_S d;
  1472. d.all = *(volatile U32 *)REG_ETH_MHTRL;
  1473. d.bitc.htl = data;
  1474. *(volatile U32 *)REG_ETH_MHTRL = d.all;
  1475. #if GH_ETH_ENABLE_DEBUG_PRINT
  1476. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MHTRL_HTL] <-- 0x%08x\n",
  1477. REG_ETH_MHTRL,d.all,d.all);
  1478. #endif
  1479. }
  1480. GH_INLINE U32 GH_ETH_get_MHTRL_HTL(void)
  1481. {
  1482. GH_ETH_MHTRL_S tmp_value;
  1483. U32 value = (*(volatile U32 *)REG_ETH_MHTRL);
  1484. tmp_value.all = value;
  1485. #if GH_ETH_ENABLE_DEBUG_PRINT
  1486. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MHTRL_HTL] --> 0x%08x\n",
  1487. REG_ETH_MHTRL,value);
  1488. #endif
  1489. return tmp_value.bitc.htl;
  1490. }
  1491. #endif /* GH_INLINE_LEVEL == 0 */
  1492. /*----------------------------------------------------------------------------*/
  1493. /* register ETH_FCR (read/write) */
  1494. /*----------------------------------------------------------------------------*/
  1495. #if GH_INLINE_LEVEL == 0
  1496. /*! \brief Writes the register 'ETH_FCR'. */
  1497. void GH_ETH_set_FCR(U32 data);
  1498. /*! \brief Reads the register 'ETH_FCR'. */
  1499. U32 GH_ETH_get_FCR(void);
  1500. /*! \brief Writes the bit group 'FCB' of register 'ETH_FCR'. */
  1501. void GH_ETH_set_FCR_FCB(U8 data);
  1502. /*! \brief Reads the bit group 'FCB' of register 'ETH_FCR'. */
  1503. U8 GH_ETH_get_FCR_FCB(void);
  1504. /*! \brief Writes the bit group 'TFE' of register 'ETH_FCR'. */
  1505. void GH_ETH_set_FCR_TFE(U8 data);
  1506. /*! \brief Reads the bit group 'TFE' of register 'ETH_FCR'. */
  1507. U8 GH_ETH_get_FCR_TFE(void);
  1508. /*! \brief Writes the bit group 'RFE' of register 'ETH_FCR'. */
  1509. void GH_ETH_set_FCR_RFE(U8 data);
  1510. /*! \brief Reads the bit group 'RFE' of register 'ETH_FCR'. */
  1511. U8 GH_ETH_get_FCR_RFE(void);
  1512. /*! \brief Writes the bit group 'UP' of register 'ETH_FCR'. */
  1513. void GH_ETH_set_FCR_UP(U8 data);
  1514. /*! \brief Reads the bit group 'UP' of register 'ETH_FCR'. */
  1515. U8 GH_ETH_get_FCR_UP(void);
  1516. /*! \brief Writes the bit group 'PLT' of register 'ETH_FCR'. */
  1517. void GH_ETH_set_FCR_PLT(U8 data);
  1518. /*! \brief Reads the bit group 'PLT' of register 'ETH_FCR'. */
  1519. U8 GH_ETH_get_FCR_PLT(void);
  1520. /*! \brief Writes the bit group 'PT' of register 'ETH_FCR'. */
  1521. void GH_ETH_set_FCR_PT(U16 data);
  1522. /*! \brief Reads the bit group 'PT' of register 'ETH_FCR'. */
  1523. U16 GH_ETH_get_FCR_PT(void);
  1524. #else /* GH_INLINE_LEVEL == 0 */
  1525. GH_INLINE void GH_ETH_set_FCR(U32 data)
  1526. {
  1527. *(volatile U32 *)REG_ETH_FCR = data;
  1528. #if GH_ETH_ENABLE_DEBUG_PRINT
  1529. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_FCR] <-- 0x%08x\n",
  1530. REG_ETH_FCR,data,data);
  1531. #endif
  1532. }
  1533. GH_INLINE U32 GH_ETH_get_FCR(void)
  1534. {
  1535. U32 value = (*(volatile U32 *)REG_ETH_FCR);
  1536. #if GH_ETH_ENABLE_DEBUG_PRINT
  1537. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_FCR] --> 0x%08x\n",
  1538. REG_ETH_FCR,value);
  1539. #endif
  1540. return value;
  1541. }
  1542. GH_INLINE void GH_ETH_set_FCR_FCB(U8 data)
  1543. {
  1544. GH_ETH_FCR_S d;
  1545. d.all = *(volatile U32 *)REG_ETH_FCR;
  1546. d.bitc.fcb = data;
  1547. *(volatile U32 *)REG_ETH_FCR = d.all;
  1548. #if GH_ETH_ENABLE_DEBUG_PRINT
  1549. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_FCR_FCB] <-- 0x%08x\n",
  1550. REG_ETH_FCR,d.all,d.all);
  1551. #endif
  1552. }
  1553. GH_INLINE U8 GH_ETH_get_FCR_FCB(void)
  1554. {
  1555. GH_ETH_FCR_S tmp_value;
  1556. U32 value = (*(volatile U32 *)REG_ETH_FCR);
  1557. tmp_value.all = value;
  1558. #if GH_ETH_ENABLE_DEBUG_PRINT
  1559. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_FCR_FCB] --> 0x%08x\n",
  1560. REG_ETH_FCR,value);
  1561. #endif
  1562. return tmp_value.bitc.fcb;
  1563. }
  1564. GH_INLINE void GH_ETH_set_FCR_TFE(U8 data)
  1565. {
  1566. GH_ETH_FCR_S d;
  1567. d.all = *(volatile U32 *)REG_ETH_FCR;
  1568. d.bitc.tfe = data;
  1569. *(volatile U32 *)REG_ETH_FCR = d.all;
  1570. #if GH_ETH_ENABLE_DEBUG_PRINT
  1571. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_FCR_TFE] <-- 0x%08x\n",
  1572. REG_ETH_FCR,d.all,d.all);
  1573. #endif
  1574. }
  1575. GH_INLINE U8 GH_ETH_get_FCR_TFE(void)
  1576. {
  1577. GH_ETH_FCR_S tmp_value;
  1578. U32 value = (*(volatile U32 *)REG_ETH_FCR);
  1579. tmp_value.all = value;
  1580. #if GH_ETH_ENABLE_DEBUG_PRINT
  1581. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_FCR_TFE] --> 0x%08x\n",
  1582. REG_ETH_FCR,value);
  1583. #endif
  1584. return tmp_value.bitc.tfe;
  1585. }
  1586. GH_INLINE void GH_ETH_set_FCR_RFE(U8 data)
  1587. {
  1588. GH_ETH_FCR_S d;
  1589. d.all = *(volatile U32 *)REG_ETH_FCR;
  1590. d.bitc.rfe = data;
  1591. *(volatile U32 *)REG_ETH_FCR = d.all;
  1592. #if GH_ETH_ENABLE_DEBUG_PRINT
  1593. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_FCR_RFE] <-- 0x%08x\n",
  1594. REG_ETH_FCR,d.all,d.all);
  1595. #endif
  1596. }
  1597. GH_INLINE U8 GH_ETH_get_FCR_RFE(void)
  1598. {
  1599. GH_ETH_FCR_S tmp_value;
  1600. U32 value = (*(volatile U32 *)REG_ETH_FCR);
  1601. tmp_value.all = value;
  1602. #if GH_ETH_ENABLE_DEBUG_PRINT
  1603. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_FCR_RFE] --> 0x%08x\n",
  1604. REG_ETH_FCR,value);
  1605. #endif
  1606. return tmp_value.bitc.rfe;
  1607. }
  1608. GH_INLINE void GH_ETH_set_FCR_UP(U8 data)
  1609. {
  1610. GH_ETH_FCR_S d;
  1611. d.all = *(volatile U32 *)REG_ETH_FCR;
  1612. d.bitc.up = data;
  1613. *(volatile U32 *)REG_ETH_FCR = d.all;
  1614. #if GH_ETH_ENABLE_DEBUG_PRINT
  1615. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_FCR_UP] <-- 0x%08x\n",
  1616. REG_ETH_FCR,d.all,d.all);
  1617. #endif
  1618. }
  1619. GH_INLINE U8 GH_ETH_get_FCR_UP(void)
  1620. {
  1621. GH_ETH_FCR_S tmp_value;
  1622. U32 value = (*(volatile U32 *)REG_ETH_FCR);
  1623. tmp_value.all = value;
  1624. #if GH_ETH_ENABLE_DEBUG_PRINT
  1625. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_FCR_UP] --> 0x%08x\n",
  1626. REG_ETH_FCR,value);
  1627. #endif
  1628. return tmp_value.bitc.up;
  1629. }
  1630. GH_INLINE void GH_ETH_set_FCR_PLT(U8 data)
  1631. {
  1632. GH_ETH_FCR_S d;
  1633. d.all = *(volatile U32 *)REG_ETH_FCR;
  1634. d.bitc.plt = data;
  1635. *(volatile U32 *)REG_ETH_FCR = d.all;
  1636. #if GH_ETH_ENABLE_DEBUG_PRINT
  1637. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_FCR_PLT] <-- 0x%08x\n",
  1638. REG_ETH_FCR,d.all,d.all);
  1639. #endif
  1640. }
  1641. GH_INLINE U8 GH_ETH_get_FCR_PLT(void)
  1642. {
  1643. GH_ETH_FCR_S tmp_value;
  1644. U32 value = (*(volatile U32 *)REG_ETH_FCR);
  1645. tmp_value.all = value;
  1646. #if GH_ETH_ENABLE_DEBUG_PRINT
  1647. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_FCR_PLT] --> 0x%08x\n",
  1648. REG_ETH_FCR,value);
  1649. #endif
  1650. return tmp_value.bitc.plt;
  1651. }
  1652. GH_INLINE void GH_ETH_set_FCR_PT(U16 data)
  1653. {
  1654. GH_ETH_FCR_S d;
  1655. d.all = *(volatile U32 *)REG_ETH_FCR;
  1656. d.bitc.pt = data;
  1657. *(volatile U32 *)REG_ETH_FCR = d.all;
  1658. #if GH_ETH_ENABLE_DEBUG_PRINT
  1659. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_FCR_PT] <-- 0x%08x\n",
  1660. REG_ETH_FCR,d.all,d.all);
  1661. #endif
  1662. }
  1663. GH_INLINE U16 GH_ETH_get_FCR_PT(void)
  1664. {
  1665. GH_ETH_FCR_S tmp_value;
  1666. U32 value = (*(volatile U32 *)REG_ETH_FCR);
  1667. tmp_value.all = value;
  1668. #if GH_ETH_ENABLE_DEBUG_PRINT
  1669. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_FCR_PT] --> 0x%08x\n",
  1670. REG_ETH_FCR,value);
  1671. #endif
  1672. return tmp_value.bitc.pt;
  1673. }
  1674. #endif /* GH_INLINE_LEVEL == 0 */
  1675. /*----------------------------------------------------------------------------*/
  1676. /* register ETH_VTR (read/write) */
  1677. /*----------------------------------------------------------------------------*/
  1678. #if GH_INLINE_LEVEL == 0
  1679. /*! \brief Writes the register 'ETH_VTR'. */
  1680. void GH_ETH_set_VTR(U32 data);
  1681. /*! \brief Reads the register 'ETH_VTR'. */
  1682. U32 GH_ETH_get_VTR(void);
  1683. /*! \brief Writes the bit group 'VL' of register 'ETH_VTR'. */
  1684. void GH_ETH_set_VTR_VL(U16 data);
  1685. /*! \brief Reads the bit group 'VL' of register 'ETH_VTR'. */
  1686. U16 GH_ETH_get_VTR_VL(void);
  1687. /*! \brief Writes the bit group 'ETV' of register 'ETH_VTR'. */
  1688. void GH_ETH_set_VTR_ETV(U8 data);
  1689. /*! \brief Reads the bit group 'ETV' of register 'ETH_VTR'. */
  1690. U8 GH_ETH_get_VTR_ETV(void);
  1691. #else /* GH_INLINE_LEVEL == 0 */
  1692. GH_INLINE void GH_ETH_set_VTR(U32 data)
  1693. {
  1694. *(volatile U32 *)REG_ETH_VTR = data;
  1695. #if GH_ETH_ENABLE_DEBUG_PRINT
  1696. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_VTR] <-- 0x%08x\n",
  1697. REG_ETH_VTR,data,data);
  1698. #endif
  1699. }
  1700. GH_INLINE U32 GH_ETH_get_VTR(void)
  1701. {
  1702. U32 value = (*(volatile U32 *)REG_ETH_VTR);
  1703. #if GH_ETH_ENABLE_DEBUG_PRINT
  1704. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_VTR] --> 0x%08x\n",
  1705. REG_ETH_VTR,value);
  1706. #endif
  1707. return value;
  1708. }
  1709. GH_INLINE void GH_ETH_set_VTR_VL(U16 data)
  1710. {
  1711. GH_ETH_VTR_S d;
  1712. d.all = *(volatile U32 *)REG_ETH_VTR;
  1713. d.bitc.vl = data;
  1714. *(volatile U32 *)REG_ETH_VTR = d.all;
  1715. #if GH_ETH_ENABLE_DEBUG_PRINT
  1716. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_VTR_VL] <-- 0x%08x\n",
  1717. REG_ETH_VTR,d.all,d.all);
  1718. #endif
  1719. }
  1720. GH_INLINE U16 GH_ETH_get_VTR_VL(void)
  1721. {
  1722. GH_ETH_VTR_S tmp_value;
  1723. U32 value = (*(volatile U32 *)REG_ETH_VTR);
  1724. tmp_value.all = value;
  1725. #if GH_ETH_ENABLE_DEBUG_PRINT
  1726. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_VTR_VL] --> 0x%08x\n",
  1727. REG_ETH_VTR,value);
  1728. #endif
  1729. return tmp_value.bitc.vl;
  1730. }
  1731. GH_INLINE void GH_ETH_set_VTR_ETV(U8 data)
  1732. {
  1733. GH_ETH_VTR_S d;
  1734. d.all = *(volatile U32 *)REG_ETH_VTR;
  1735. d.bitc.etv = data;
  1736. *(volatile U32 *)REG_ETH_VTR = d.all;
  1737. #if GH_ETH_ENABLE_DEBUG_PRINT
  1738. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_VTR_ETV] <-- 0x%08x\n",
  1739. REG_ETH_VTR,d.all,d.all);
  1740. #endif
  1741. }
  1742. GH_INLINE U8 GH_ETH_get_VTR_ETV(void)
  1743. {
  1744. GH_ETH_VTR_S tmp_value;
  1745. U32 value = (*(volatile U32 *)REG_ETH_VTR);
  1746. tmp_value.all = value;
  1747. #if GH_ETH_ENABLE_DEBUG_PRINT
  1748. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_VTR_ETV] --> 0x%08x\n",
  1749. REG_ETH_VTR,value);
  1750. #endif
  1751. return tmp_value.bitc.etv;
  1752. }
  1753. #endif /* GH_INLINE_LEVEL == 0 */
  1754. /*----------------------------------------------------------------------------*/
  1755. /* register ETH_MAR0H (read/write) */
  1756. /*----------------------------------------------------------------------------*/
  1757. #if GH_INLINE_LEVEL == 0
  1758. /*! \brief Writes the register 'ETH_MAR0H'. */
  1759. void GH_ETH_set_MAR0H(U32 data);
  1760. /*! \brief Reads the register 'ETH_MAR0H'. */
  1761. U32 GH_ETH_get_MAR0H(void);
  1762. /*! \brief Writes the bit group 'A0' of register 'ETH_MAR0H'. */
  1763. void GH_ETH_set_MAR0H_A0(U16 data);
  1764. /*! \brief Reads the bit group 'A0' of register 'ETH_MAR0H'. */
  1765. U16 GH_ETH_get_MAR0H_A0(void);
  1766. /*! \brief Writes the bit group 'M0' of register 'ETH_MAR0H'. */
  1767. void GH_ETH_set_MAR0H_M0(U8 data);
  1768. /*! \brief Reads the bit group 'M0' of register 'ETH_MAR0H'. */
  1769. U8 GH_ETH_get_MAR0H_M0(void);
  1770. #else /* GH_INLINE_LEVEL == 0 */
  1771. GH_INLINE void GH_ETH_set_MAR0H(U32 data)
  1772. {
  1773. *(volatile U32 *)REG_ETH_MAR0H = data;
  1774. #if GH_ETH_ENABLE_DEBUG_PRINT
  1775. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR0H] <-- 0x%08x\n",
  1776. REG_ETH_MAR0H,data,data);
  1777. #endif
  1778. }
  1779. GH_INLINE U32 GH_ETH_get_MAR0H(void)
  1780. {
  1781. U32 value = (*(volatile U32 *)REG_ETH_MAR0H);
  1782. #if GH_ETH_ENABLE_DEBUG_PRINT
  1783. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR0H] --> 0x%08x\n",
  1784. REG_ETH_MAR0H,value);
  1785. #endif
  1786. return value;
  1787. }
  1788. GH_INLINE void GH_ETH_set_MAR0H_A0(U16 data)
  1789. {
  1790. GH_ETH_MAR0H_S d;
  1791. d.all = *(volatile U32 *)REG_ETH_MAR0H;
  1792. d.bitc.a0 = data;
  1793. *(volatile U32 *)REG_ETH_MAR0H = d.all;
  1794. #if GH_ETH_ENABLE_DEBUG_PRINT
  1795. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR0H_A0] <-- 0x%08x\n",
  1796. REG_ETH_MAR0H,d.all,d.all);
  1797. #endif
  1798. }
  1799. GH_INLINE U16 GH_ETH_get_MAR0H_A0(void)
  1800. {
  1801. GH_ETH_MAR0H_S tmp_value;
  1802. U32 value = (*(volatile U32 *)REG_ETH_MAR0H);
  1803. tmp_value.all = value;
  1804. #if GH_ETH_ENABLE_DEBUG_PRINT
  1805. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR0H_A0] --> 0x%08x\n",
  1806. REG_ETH_MAR0H,value);
  1807. #endif
  1808. return tmp_value.bitc.a0;
  1809. }
  1810. GH_INLINE void GH_ETH_set_MAR0H_M0(U8 data)
  1811. {
  1812. GH_ETH_MAR0H_S d;
  1813. d.all = *(volatile U32 *)REG_ETH_MAR0H;
  1814. d.bitc.m0 = data;
  1815. *(volatile U32 *)REG_ETH_MAR0H = d.all;
  1816. #if GH_ETH_ENABLE_DEBUG_PRINT
  1817. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR0H_M0] <-- 0x%08x\n",
  1818. REG_ETH_MAR0H,d.all,d.all);
  1819. #endif
  1820. }
  1821. GH_INLINE U8 GH_ETH_get_MAR0H_M0(void)
  1822. {
  1823. GH_ETH_MAR0H_S tmp_value;
  1824. U32 value = (*(volatile U32 *)REG_ETH_MAR0H);
  1825. tmp_value.all = value;
  1826. #if GH_ETH_ENABLE_DEBUG_PRINT
  1827. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR0H_M0] --> 0x%08x\n",
  1828. REG_ETH_MAR0H,value);
  1829. #endif
  1830. return tmp_value.bitc.m0;
  1831. }
  1832. #endif /* GH_INLINE_LEVEL == 0 */
  1833. /*----------------------------------------------------------------------------*/
  1834. /* register ETH_MAR0L (read/write) */
  1835. /*----------------------------------------------------------------------------*/
  1836. #if GH_INLINE_LEVEL == 0
  1837. /*! \brief Writes the register 'ETH_MAR0L'. */
  1838. void GH_ETH_set_MAR0L(U32 data);
  1839. /*! \brief Reads the register 'ETH_MAR0L'. */
  1840. U32 GH_ETH_get_MAR0L(void);
  1841. /*! \brief Writes the bit group 'A0' of register 'ETH_MAR0L'. */
  1842. void GH_ETH_set_MAR0L_A0(U32 data);
  1843. /*! \brief Reads the bit group 'A0' of register 'ETH_MAR0L'. */
  1844. U32 GH_ETH_get_MAR0L_A0(void);
  1845. #else /* GH_INLINE_LEVEL == 0 */
  1846. GH_INLINE void GH_ETH_set_MAR0L(U32 data)
  1847. {
  1848. *(volatile U32 *)REG_ETH_MAR0L = data;
  1849. #if GH_ETH_ENABLE_DEBUG_PRINT
  1850. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR0L] <-- 0x%08x\n",
  1851. REG_ETH_MAR0L,data,data);
  1852. #endif
  1853. }
  1854. GH_INLINE U32 GH_ETH_get_MAR0L(void)
  1855. {
  1856. U32 value = (*(volatile U32 *)REG_ETH_MAR0L);
  1857. #if GH_ETH_ENABLE_DEBUG_PRINT
  1858. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR0L] --> 0x%08x\n",
  1859. REG_ETH_MAR0L,value);
  1860. #endif
  1861. return value;
  1862. }
  1863. GH_INLINE void GH_ETH_set_MAR0L_A0(U32 data)
  1864. {
  1865. GH_ETH_MAR0L_S d;
  1866. d.all = *(volatile U32 *)REG_ETH_MAR0L;
  1867. d.bitc.a0 = data;
  1868. *(volatile U32 *)REG_ETH_MAR0L = d.all;
  1869. #if GH_ETH_ENABLE_DEBUG_PRINT
  1870. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR0L_A0] <-- 0x%08x\n",
  1871. REG_ETH_MAR0L,d.all,d.all);
  1872. #endif
  1873. }
  1874. GH_INLINE U32 GH_ETH_get_MAR0L_A0(void)
  1875. {
  1876. GH_ETH_MAR0L_S tmp_value;
  1877. U32 value = (*(volatile U32 *)REG_ETH_MAR0L);
  1878. tmp_value.all = value;
  1879. #if GH_ETH_ENABLE_DEBUG_PRINT
  1880. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR0L_A0] --> 0x%08x\n",
  1881. REG_ETH_MAR0L,value);
  1882. #endif
  1883. return tmp_value.bitc.a0;
  1884. }
  1885. #endif /* GH_INLINE_LEVEL == 0 */
  1886. /*----------------------------------------------------------------------------*/
  1887. /* register ETH_MAR1H (read/write) */
  1888. /*----------------------------------------------------------------------------*/
  1889. #if GH_INLINE_LEVEL == 0
  1890. /*! \brief Writes the register 'ETH_MAR1H'. */
  1891. void GH_ETH_set_MAR1H(U32 data);
  1892. /*! \brief Reads the register 'ETH_MAR1H'. */
  1893. U32 GH_ETH_get_MAR1H(void);
  1894. /*! \brief Writes the bit group 'A1' of register 'ETH_MAR1H'. */
  1895. void GH_ETH_set_MAR1H_A1(U16 data);
  1896. /*! \brief Reads the bit group 'A1' of register 'ETH_MAR1H'. */
  1897. U16 GH_ETH_get_MAR1H_A1(void);
  1898. /*! \brief Writes the bit group 'MBC' of register 'ETH_MAR1H'. */
  1899. void GH_ETH_set_MAR1H_MBC(U8 data);
  1900. /*! \brief Reads the bit group 'MBC' of register 'ETH_MAR1H'. */
  1901. U8 GH_ETH_get_MAR1H_MBC(void);
  1902. /*! \brief Writes the bit group 'SA' of register 'ETH_MAR1H'. */
  1903. void GH_ETH_set_MAR1H_SA(U8 data);
  1904. /*! \brief Reads the bit group 'SA' of register 'ETH_MAR1H'. */
  1905. U8 GH_ETH_get_MAR1H_SA(void);
  1906. /*! \brief Writes the bit group 'A1E' of register 'ETH_MAR1H'. */
  1907. void GH_ETH_set_MAR1H_A1E(U8 data);
  1908. /*! \brief Reads the bit group 'A1E' of register 'ETH_MAR1H'. */
  1909. U8 GH_ETH_get_MAR1H_A1E(void);
  1910. #else /* GH_INLINE_LEVEL == 0 */
  1911. GH_INLINE void GH_ETH_set_MAR1H(U32 data)
  1912. {
  1913. *(volatile U32 *)REG_ETH_MAR1H = data;
  1914. #if GH_ETH_ENABLE_DEBUG_PRINT
  1915. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR1H] <-- 0x%08x\n",
  1916. REG_ETH_MAR1H,data,data);
  1917. #endif
  1918. }
  1919. GH_INLINE U32 GH_ETH_get_MAR1H(void)
  1920. {
  1921. U32 value = (*(volatile U32 *)REG_ETH_MAR1H);
  1922. #if GH_ETH_ENABLE_DEBUG_PRINT
  1923. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR1H] --> 0x%08x\n",
  1924. REG_ETH_MAR1H,value);
  1925. #endif
  1926. return value;
  1927. }
  1928. GH_INLINE void GH_ETH_set_MAR1H_A1(U16 data)
  1929. {
  1930. GH_ETH_MAR1H_S d;
  1931. d.all = *(volatile U32 *)REG_ETH_MAR1H;
  1932. d.bitc.a1 = data;
  1933. *(volatile U32 *)REG_ETH_MAR1H = d.all;
  1934. #if GH_ETH_ENABLE_DEBUG_PRINT
  1935. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR1H_A1] <-- 0x%08x\n",
  1936. REG_ETH_MAR1H,d.all,d.all);
  1937. #endif
  1938. }
  1939. GH_INLINE U16 GH_ETH_get_MAR1H_A1(void)
  1940. {
  1941. GH_ETH_MAR1H_S tmp_value;
  1942. U32 value = (*(volatile U32 *)REG_ETH_MAR1H);
  1943. tmp_value.all = value;
  1944. #if GH_ETH_ENABLE_DEBUG_PRINT
  1945. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR1H_A1] --> 0x%08x\n",
  1946. REG_ETH_MAR1H,value);
  1947. #endif
  1948. return tmp_value.bitc.a1;
  1949. }
  1950. GH_INLINE void GH_ETH_set_MAR1H_MBC(U8 data)
  1951. {
  1952. GH_ETH_MAR1H_S d;
  1953. d.all = *(volatile U32 *)REG_ETH_MAR1H;
  1954. d.bitc.mbc = data;
  1955. *(volatile U32 *)REG_ETH_MAR1H = d.all;
  1956. #if GH_ETH_ENABLE_DEBUG_PRINT
  1957. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR1H_MBC] <-- 0x%08x\n",
  1958. REG_ETH_MAR1H,d.all,d.all);
  1959. #endif
  1960. }
  1961. GH_INLINE U8 GH_ETH_get_MAR1H_MBC(void)
  1962. {
  1963. GH_ETH_MAR1H_S tmp_value;
  1964. U32 value = (*(volatile U32 *)REG_ETH_MAR1H);
  1965. tmp_value.all = value;
  1966. #if GH_ETH_ENABLE_DEBUG_PRINT
  1967. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR1H_MBC] --> 0x%08x\n",
  1968. REG_ETH_MAR1H,value);
  1969. #endif
  1970. return tmp_value.bitc.mbc;
  1971. }
  1972. GH_INLINE void GH_ETH_set_MAR1H_SA(U8 data)
  1973. {
  1974. GH_ETH_MAR1H_S d;
  1975. d.all = *(volatile U32 *)REG_ETH_MAR1H;
  1976. d.bitc.sa = data;
  1977. *(volatile U32 *)REG_ETH_MAR1H = d.all;
  1978. #if GH_ETH_ENABLE_DEBUG_PRINT
  1979. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR1H_SA] <-- 0x%08x\n",
  1980. REG_ETH_MAR1H,d.all,d.all);
  1981. #endif
  1982. }
  1983. GH_INLINE U8 GH_ETH_get_MAR1H_SA(void)
  1984. {
  1985. GH_ETH_MAR1H_S tmp_value;
  1986. U32 value = (*(volatile U32 *)REG_ETH_MAR1H);
  1987. tmp_value.all = value;
  1988. #if GH_ETH_ENABLE_DEBUG_PRINT
  1989. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR1H_SA] --> 0x%08x\n",
  1990. REG_ETH_MAR1H,value);
  1991. #endif
  1992. return tmp_value.bitc.sa;
  1993. }
  1994. GH_INLINE void GH_ETH_set_MAR1H_A1E(U8 data)
  1995. {
  1996. GH_ETH_MAR1H_S d;
  1997. d.all = *(volatile U32 *)REG_ETH_MAR1H;
  1998. d.bitc.a1e = data;
  1999. *(volatile U32 *)REG_ETH_MAR1H = d.all;
  2000. #if GH_ETH_ENABLE_DEBUG_PRINT
  2001. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR1H_A1E] <-- 0x%08x\n",
  2002. REG_ETH_MAR1H,d.all,d.all);
  2003. #endif
  2004. }
  2005. GH_INLINE U8 GH_ETH_get_MAR1H_A1E(void)
  2006. {
  2007. GH_ETH_MAR1H_S tmp_value;
  2008. U32 value = (*(volatile U32 *)REG_ETH_MAR1H);
  2009. tmp_value.all = value;
  2010. #if GH_ETH_ENABLE_DEBUG_PRINT
  2011. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR1H_A1E] --> 0x%08x\n",
  2012. REG_ETH_MAR1H,value);
  2013. #endif
  2014. return tmp_value.bitc.a1e;
  2015. }
  2016. #endif /* GH_INLINE_LEVEL == 0 */
  2017. /*----------------------------------------------------------------------------*/
  2018. /* register ETH_MAR1L (read/write) */
  2019. /*----------------------------------------------------------------------------*/
  2020. #if GH_INLINE_LEVEL == 0
  2021. /*! \brief Writes the register 'ETH_MAR1L'. */
  2022. void GH_ETH_set_MAR1L(U32 data);
  2023. /*! \brief Reads the register 'ETH_MAR1L'. */
  2024. U32 GH_ETH_get_MAR1L(void);
  2025. /*! \brief Writes the bit group 'A1' of register 'ETH_MAR1L'. */
  2026. void GH_ETH_set_MAR1L_A1(U32 data);
  2027. /*! \brief Reads the bit group 'A1' of register 'ETH_MAR1L'. */
  2028. U32 GH_ETH_get_MAR1L_A1(void);
  2029. #else /* GH_INLINE_LEVEL == 0 */
  2030. GH_INLINE void GH_ETH_set_MAR1L(U32 data)
  2031. {
  2032. *(volatile U32 *)REG_ETH_MAR1L = data;
  2033. #if GH_ETH_ENABLE_DEBUG_PRINT
  2034. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR1L] <-- 0x%08x\n",
  2035. REG_ETH_MAR1L,data,data);
  2036. #endif
  2037. }
  2038. GH_INLINE U32 GH_ETH_get_MAR1L(void)
  2039. {
  2040. U32 value = (*(volatile U32 *)REG_ETH_MAR1L);
  2041. #if GH_ETH_ENABLE_DEBUG_PRINT
  2042. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR1L] --> 0x%08x\n",
  2043. REG_ETH_MAR1L,value);
  2044. #endif
  2045. return value;
  2046. }
  2047. GH_INLINE void GH_ETH_set_MAR1L_A1(U32 data)
  2048. {
  2049. GH_ETH_MAR1L_S d;
  2050. d.all = *(volatile U32 *)REG_ETH_MAR1L;
  2051. d.bitc.a1 = data;
  2052. *(volatile U32 *)REG_ETH_MAR1L = d.all;
  2053. #if GH_ETH_ENABLE_DEBUG_PRINT
  2054. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR1L_A1] <-- 0x%08x\n",
  2055. REG_ETH_MAR1L,d.all,d.all);
  2056. #endif
  2057. }
  2058. GH_INLINE U32 GH_ETH_get_MAR1L_A1(void)
  2059. {
  2060. GH_ETH_MAR1L_S tmp_value;
  2061. U32 value = (*(volatile U32 *)REG_ETH_MAR1L);
  2062. tmp_value.all = value;
  2063. #if GH_ETH_ENABLE_DEBUG_PRINT
  2064. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR1L_A1] --> 0x%08x\n",
  2065. REG_ETH_MAR1L,value);
  2066. #endif
  2067. return tmp_value.bitc.a1;
  2068. }
  2069. #endif /* GH_INLINE_LEVEL == 0 */
  2070. /*----------------------------------------------------------------------------*/
  2071. /* register ETH_MAR2H (read/write) */
  2072. /*----------------------------------------------------------------------------*/
  2073. #if GH_INLINE_LEVEL == 0
  2074. /*! \brief Writes the register 'ETH_MAR2H'. */
  2075. void GH_ETH_set_MAR2H(U32 data);
  2076. /*! \brief Reads the register 'ETH_MAR2H'. */
  2077. U32 GH_ETH_get_MAR2H(void);
  2078. /*! \brief Writes the bit group 'A2' of register 'ETH_MAR2H'. */
  2079. void GH_ETH_set_MAR2H_A2(U16 data);
  2080. /*! \brief Reads the bit group 'A2' of register 'ETH_MAR2H'. */
  2081. U16 GH_ETH_get_MAR2H_A2(void);
  2082. /*! \brief Writes the bit group 'MBC' of register 'ETH_MAR2H'. */
  2083. void GH_ETH_set_MAR2H_MBC(U8 data);
  2084. /*! \brief Reads the bit group 'MBC' of register 'ETH_MAR2H'. */
  2085. U8 GH_ETH_get_MAR2H_MBC(void);
  2086. /*! \brief Writes the bit group 'SA' of register 'ETH_MAR2H'. */
  2087. void GH_ETH_set_MAR2H_SA(U8 data);
  2088. /*! \brief Reads the bit group 'SA' of register 'ETH_MAR2H'. */
  2089. U8 GH_ETH_get_MAR2H_SA(void);
  2090. /*! \brief Writes the bit group 'A2E' of register 'ETH_MAR2H'. */
  2091. void GH_ETH_set_MAR2H_A2E(U8 data);
  2092. /*! \brief Reads the bit group 'A2E' of register 'ETH_MAR2H'. */
  2093. U8 GH_ETH_get_MAR2H_A2E(void);
  2094. #else /* GH_INLINE_LEVEL == 0 */
  2095. GH_INLINE void GH_ETH_set_MAR2H(U32 data)
  2096. {
  2097. *(volatile U32 *)REG_ETH_MAR2H = data;
  2098. #if GH_ETH_ENABLE_DEBUG_PRINT
  2099. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR2H] <-- 0x%08x\n",
  2100. REG_ETH_MAR2H,data,data);
  2101. #endif
  2102. }
  2103. GH_INLINE U32 GH_ETH_get_MAR2H(void)
  2104. {
  2105. U32 value = (*(volatile U32 *)REG_ETH_MAR2H);
  2106. #if GH_ETH_ENABLE_DEBUG_PRINT
  2107. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR2H] --> 0x%08x\n",
  2108. REG_ETH_MAR2H,value);
  2109. #endif
  2110. return value;
  2111. }
  2112. GH_INLINE void GH_ETH_set_MAR2H_A2(U16 data)
  2113. {
  2114. GH_ETH_MAR2H_S d;
  2115. d.all = *(volatile U32 *)REG_ETH_MAR2H;
  2116. d.bitc.a2 = data;
  2117. *(volatile U32 *)REG_ETH_MAR2H = d.all;
  2118. #if GH_ETH_ENABLE_DEBUG_PRINT
  2119. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR2H_A2] <-- 0x%08x\n",
  2120. REG_ETH_MAR2H,d.all,d.all);
  2121. #endif
  2122. }
  2123. GH_INLINE U16 GH_ETH_get_MAR2H_A2(void)
  2124. {
  2125. GH_ETH_MAR2H_S tmp_value;
  2126. U32 value = (*(volatile U32 *)REG_ETH_MAR2H);
  2127. tmp_value.all = value;
  2128. #if GH_ETH_ENABLE_DEBUG_PRINT
  2129. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR2H_A2] --> 0x%08x\n",
  2130. REG_ETH_MAR2H,value);
  2131. #endif
  2132. return tmp_value.bitc.a2;
  2133. }
  2134. GH_INLINE void GH_ETH_set_MAR2H_MBC(U8 data)
  2135. {
  2136. GH_ETH_MAR2H_S d;
  2137. d.all = *(volatile U32 *)REG_ETH_MAR2H;
  2138. d.bitc.mbc = data;
  2139. *(volatile U32 *)REG_ETH_MAR2H = d.all;
  2140. #if GH_ETH_ENABLE_DEBUG_PRINT
  2141. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR2H_MBC] <-- 0x%08x\n",
  2142. REG_ETH_MAR2H,d.all,d.all);
  2143. #endif
  2144. }
  2145. GH_INLINE U8 GH_ETH_get_MAR2H_MBC(void)
  2146. {
  2147. GH_ETH_MAR2H_S tmp_value;
  2148. U32 value = (*(volatile U32 *)REG_ETH_MAR2H);
  2149. tmp_value.all = value;
  2150. #if GH_ETH_ENABLE_DEBUG_PRINT
  2151. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR2H_MBC] --> 0x%08x\n",
  2152. REG_ETH_MAR2H,value);
  2153. #endif
  2154. return tmp_value.bitc.mbc;
  2155. }
  2156. GH_INLINE void GH_ETH_set_MAR2H_SA(U8 data)
  2157. {
  2158. GH_ETH_MAR2H_S d;
  2159. d.all = *(volatile U32 *)REG_ETH_MAR2H;
  2160. d.bitc.sa = data;
  2161. *(volatile U32 *)REG_ETH_MAR2H = d.all;
  2162. #if GH_ETH_ENABLE_DEBUG_PRINT
  2163. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR2H_SA] <-- 0x%08x\n",
  2164. REG_ETH_MAR2H,d.all,d.all);
  2165. #endif
  2166. }
  2167. GH_INLINE U8 GH_ETH_get_MAR2H_SA(void)
  2168. {
  2169. GH_ETH_MAR2H_S tmp_value;
  2170. U32 value = (*(volatile U32 *)REG_ETH_MAR2H);
  2171. tmp_value.all = value;
  2172. #if GH_ETH_ENABLE_DEBUG_PRINT
  2173. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR2H_SA] --> 0x%08x\n",
  2174. REG_ETH_MAR2H,value);
  2175. #endif
  2176. return tmp_value.bitc.sa;
  2177. }
  2178. GH_INLINE void GH_ETH_set_MAR2H_A2E(U8 data)
  2179. {
  2180. GH_ETH_MAR2H_S d;
  2181. d.all = *(volatile U32 *)REG_ETH_MAR2H;
  2182. d.bitc.a2e = data;
  2183. *(volatile U32 *)REG_ETH_MAR2H = d.all;
  2184. #if GH_ETH_ENABLE_DEBUG_PRINT
  2185. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR2H_A2E] <-- 0x%08x\n",
  2186. REG_ETH_MAR2H,d.all,d.all);
  2187. #endif
  2188. }
  2189. GH_INLINE U8 GH_ETH_get_MAR2H_A2E(void)
  2190. {
  2191. GH_ETH_MAR2H_S tmp_value;
  2192. U32 value = (*(volatile U32 *)REG_ETH_MAR2H);
  2193. tmp_value.all = value;
  2194. #if GH_ETH_ENABLE_DEBUG_PRINT
  2195. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR2H_A2E] --> 0x%08x\n",
  2196. REG_ETH_MAR2H,value);
  2197. #endif
  2198. return tmp_value.bitc.a2e;
  2199. }
  2200. #endif /* GH_INLINE_LEVEL == 0 */
  2201. /*----------------------------------------------------------------------------*/
  2202. /* register ETH_MAR2L (read/write) */
  2203. /*----------------------------------------------------------------------------*/
  2204. #if GH_INLINE_LEVEL == 0
  2205. /*! \brief Writes the register 'ETH_MAR2L'. */
  2206. void GH_ETH_set_MAR2L(U32 data);
  2207. /*! \brief Reads the register 'ETH_MAR2L'. */
  2208. U32 GH_ETH_get_MAR2L(void);
  2209. /*! \brief Writes the bit group 'A2' of register 'ETH_MAR2L'. */
  2210. void GH_ETH_set_MAR2L_A2(U32 data);
  2211. /*! \brief Reads the bit group 'A2' of register 'ETH_MAR2L'. */
  2212. U32 GH_ETH_get_MAR2L_A2(void);
  2213. #else /* GH_INLINE_LEVEL == 0 */
  2214. GH_INLINE void GH_ETH_set_MAR2L(U32 data)
  2215. {
  2216. *(volatile U32 *)REG_ETH_MAR2L = data;
  2217. #if GH_ETH_ENABLE_DEBUG_PRINT
  2218. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR2L] <-- 0x%08x\n",
  2219. REG_ETH_MAR2L,data,data);
  2220. #endif
  2221. }
  2222. GH_INLINE U32 GH_ETH_get_MAR2L(void)
  2223. {
  2224. U32 value = (*(volatile U32 *)REG_ETH_MAR2L);
  2225. #if GH_ETH_ENABLE_DEBUG_PRINT
  2226. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR2L] --> 0x%08x\n",
  2227. REG_ETH_MAR2L,value);
  2228. #endif
  2229. return value;
  2230. }
  2231. GH_INLINE void GH_ETH_set_MAR2L_A2(U32 data)
  2232. {
  2233. GH_ETH_MAR2L_S d;
  2234. d.all = *(volatile U32 *)REG_ETH_MAR2L;
  2235. d.bitc.a2 = data;
  2236. *(volatile U32 *)REG_ETH_MAR2L = d.all;
  2237. #if GH_ETH_ENABLE_DEBUG_PRINT
  2238. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MAR2L_A2] <-- 0x%08x\n",
  2239. REG_ETH_MAR2L,d.all,d.all);
  2240. #endif
  2241. }
  2242. GH_INLINE U32 GH_ETH_get_MAR2L_A2(void)
  2243. {
  2244. GH_ETH_MAR2L_S tmp_value;
  2245. U32 value = (*(volatile U32 *)REG_ETH_MAR2L);
  2246. tmp_value.all = value;
  2247. #if GH_ETH_ENABLE_DEBUG_PRINT
  2248. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MAR2L_A2] --> 0x%08x\n",
  2249. REG_ETH_MAR2L,value);
  2250. #endif
  2251. return tmp_value.bitc.a2;
  2252. }
  2253. #endif /* GH_INLINE_LEVEL == 0 */
  2254. /*----------------------------------------------------------------------------*/
  2255. /* register ETH_VR (read) */
  2256. /*----------------------------------------------------------------------------*/
  2257. #if GH_INLINE_LEVEL == 0
  2258. /*! \brief Reads the register 'ETH_VR'. */
  2259. U32 GH_ETH_get_VR(void);
  2260. #else /* GH_INLINE_LEVEL == 0 */
  2261. GH_INLINE U32 GH_ETH_get_VR(void)
  2262. {
  2263. U32 value = (*(volatile U32 *)REG_ETH_VR);
  2264. #if GH_ETH_ENABLE_DEBUG_PRINT
  2265. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_VR] --> 0x%08x\n",
  2266. REG_ETH_VR,value);
  2267. #endif
  2268. return value;
  2269. }
  2270. #endif /* GH_INLINE_LEVEL == 0 */
  2271. /*----------------------------------------------------------------------------*/
  2272. /* register ETH_EPHY_DEBUG (read/write) */
  2273. /*----------------------------------------------------------------------------*/
  2274. #if GH_INLINE_LEVEL == 0
  2275. /*! \brief Writes the register 'ETH_EPHY_DEBUG'. */
  2276. void GH_ETH_set_EPHY_DEBUG(U32 data);
  2277. /*! \brief Reads the register 'ETH_EPHY_DEBUG'. */
  2278. U32 GH_ETH_get_EPHY_DEBUG(void);
  2279. /*! \brief Writes the bit group 'debug' of register 'ETH_EPHY_DEBUG'. */
  2280. void GH_ETH_set_EPHY_DEBUG_debug(U32 data);
  2281. /*! \brief Reads the bit group 'debug' of register 'ETH_EPHY_DEBUG'. */
  2282. U32 GH_ETH_get_EPHY_DEBUG_debug(void);
  2283. #else /* GH_INLINE_LEVEL == 0 */
  2284. GH_INLINE void GH_ETH_set_EPHY_DEBUG(U32 data)
  2285. {
  2286. *(volatile U32 *)REG_ETH_EPHY_DEBUG = data;
  2287. #if GH_ETH_ENABLE_DEBUG_PRINT
  2288. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_EPHY_DEBUG] <-- 0x%08x\n",
  2289. REG_ETH_EPHY_DEBUG,data,data);
  2290. #endif
  2291. }
  2292. GH_INLINE U32 GH_ETH_get_EPHY_DEBUG(void)
  2293. {
  2294. U32 value = (*(volatile U32 *)REG_ETH_EPHY_DEBUG);
  2295. #if GH_ETH_ENABLE_DEBUG_PRINT
  2296. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_EPHY_DEBUG] --> 0x%08x\n",
  2297. REG_ETH_EPHY_DEBUG,value);
  2298. #endif
  2299. return value;
  2300. }
  2301. GH_INLINE void GH_ETH_set_EPHY_DEBUG_debug(U32 data)
  2302. {
  2303. GH_ETH_EPHY_DEBUG_S d;
  2304. d.all = *(volatile U32 *)REG_ETH_EPHY_DEBUG;
  2305. d.bitc.debug = data;
  2306. *(volatile U32 *)REG_ETH_EPHY_DEBUG = d.all;
  2307. #if GH_ETH_ENABLE_DEBUG_PRINT
  2308. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_EPHY_DEBUG_debug] <-- 0x%08x\n",
  2309. REG_ETH_EPHY_DEBUG,d.all,d.all);
  2310. #endif
  2311. }
  2312. GH_INLINE U32 GH_ETH_get_EPHY_DEBUG_debug(void)
  2313. {
  2314. GH_ETH_EPHY_DEBUG_S tmp_value;
  2315. U32 value = (*(volatile U32 *)REG_ETH_EPHY_DEBUG);
  2316. tmp_value.all = value;
  2317. #if GH_ETH_ENABLE_DEBUG_PRINT
  2318. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_EPHY_DEBUG_debug] --> 0x%08x\n",
  2319. REG_ETH_EPHY_DEBUG,value);
  2320. #endif
  2321. return tmp_value.bitc.debug;
  2322. }
  2323. #endif /* GH_INLINE_LEVEL == 0 */
  2324. /*----------------------------------------------------------------------------*/
  2325. /* register ETH_TPDR (read/write) */
  2326. /*----------------------------------------------------------------------------*/
  2327. #if GH_INLINE_LEVEL == 0
  2328. /*! \brief Writes the register 'ETH_TPDR'. */
  2329. void GH_ETH_set_TPDR(U32 data);
  2330. /*! \brief Reads the register 'ETH_TPDR'. */
  2331. U32 GH_ETH_get_TPDR(void);
  2332. #else /* GH_INLINE_LEVEL == 0 */
  2333. GH_INLINE void GH_ETH_set_TPDR(U32 data)
  2334. {
  2335. *(volatile U32 *)REG_ETH_TPDR = data;
  2336. #if GH_ETH_ENABLE_DEBUG_PRINT
  2337. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_TPDR] <-- 0x%08x\n",
  2338. REG_ETH_TPDR,data,data);
  2339. #endif
  2340. }
  2341. GH_INLINE U32 GH_ETH_get_TPDR(void)
  2342. {
  2343. U32 value = (*(volatile U32 *)REG_ETH_TPDR);
  2344. #if GH_ETH_ENABLE_DEBUG_PRINT
  2345. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_TPDR] --> 0x%08x\n",
  2346. REG_ETH_TPDR,value);
  2347. #endif
  2348. return value;
  2349. }
  2350. #endif /* GH_INLINE_LEVEL == 0 */
  2351. /*----------------------------------------------------------------------------*/
  2352. /* register ETH_RPDR (read/write) */
  2353. /*----------------------------------------------------------------------------*/
  2354. #if GH_INLINE_LEVEL == 0
  2355. /*! \brief Writes the register 'ETH_RPDR'. */
  2356. void GH_ETH_set_RPDR(U32 data);
  2357. /*! \brief Reads the register 'ETH_RPDR'. */
  2358. U32 GH_ETH_get_RPDR(void);
  2359. #else /* GH_INLINE_LEVEL == 0 */
  2360. GH_INLINE void GH_ETH_set_RPDR(U32 data)
  2361. {
  2362. *(volatile U32 *)REG_ETH_RPDR = data;
  2363. #if GH_ETH_ENABLE_DEBUG_PRINT
  2364. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_RPDR] <-- 0x%08x\n",
  2365. REG_ETH_RPDR,data,data);
  2366. #endif
  2367. }
  2368. GH_INLINE U32 GH_ETH_get_RPDR(void)
  2369. {
  2370. U32 value = (*(volatile U32 *)REG_ETH_RPDR);
  2371. #if GH_ETH_ENABLE_DEBUG_PRINT
  2372. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_RPDR] --> 0x%08x\n",
  2373. REG_ETH_RPDR,value);
  2374. #endif
  2375. return value;
  2376. }
  2377. #endif /* GH_INLINE_LEVEL == 0 */
  2378. /*----------------------------------------------------------------------------*/
  2379. /* register ETH_BMR (read/write) */
  2380. /*----------------------------------------------------------------------------*/
  2381. #if GH_INLINE_LEVEL == 0
  2382. /*! \brief Writes the register 'ETH_BMR'. */
  2383. void GH_ETH_set_BMR(U32 data);
  2384. /*! \brief Reads the register 'ETH_BMR'. */
  2385. U32 GH_ETH_get_BMR(void);
  2386. /*! \brief Writes the bit group 'SWR' of register 'ETH_BMR'. */
  2387. void GH_ETH_set_BMR_SWR(U8 data);
  2388. /*! \brief Reads the bit group 'SWR' of register 'ETH_BMR'. */
  2389. U8 GH_ETH_get_BMR_SWR(void);
  2390. /*! \brief Writes the bit group 'DA' of register 'ETH_BMR'. */
  2391. void GH_ETH_set_BMR_DA(U8 data);
  2392. /*! \brief Reads the bit group 'DA' of register 'ETH_BMR'. */
  2393. U8 GH_ETH_get_BMR_DA(void);
  2394. /*! \brief Writes the bit group 'DSL' of register 'ETH_BMR'. */
  2395. void GH_ETH_set_BMR_DSL(U8 data);
  2396. /*! \brief Reads the bit group 'DSL' of register 'ETH_BMR'. */
  2397. U8 GH_ETH_get_BMR_DSL(void);
  2398. /*! \brief Writes the bit group 'PBL' of register 'ETH_BMR'. */
  2399. void GH_ETH_set_BMR_PBL(U8 data);
  2400. /*! \brief Reads the bit group 'PBL' of register 'ETH_BMR'. */
  2401. U8 GH_ETH_get_BMR_PBL(void);
  2402. /*! \brief Writes the bit group 'PR' of register 'ETH_BMR'. */
  2403. void GH_ETH_set_BMR_PR(U8 data);
  2404. /*! \brief Reads the bit group 'PR' of register 'ETH_BMR'. */
  2405. U8 GH_ETH_get_BMR_PR(void);
  2406. /*! \brief Writes the bit group 'FB' of register 'ETH_BMR'. */
  2407. void GH_ETH_set_BMR_FB(U8 data);
  2408. /*! \brief Reads the bit group 'FB' of register 'ETH_BMR'. */
  2409. U8 GH_ETH_get_BMR_FB(void);
  2410. /*! \brief Writes the bit group 'RPBL' of register 'ETH_BMR'. */
  2411. void GH_ETH_set_BMR_RPBL(U8 data);
  2412. /*! \brief Reads the bit group 'RPBL' of register 'ETH_BMR'. */
  2413. U8 GH_ETH_get_BMR_RPBL(void);
  2414. /*! \brief Writes the bit group 'USP' of register 'ETH_BMR'. */
  2415. void GH_ETH_set_BMR_USP(U8 data);
  2416. /*! \brief Reads the bit group 'USP' of register 'ETH_BMR'. */
  2417. U8 GH_ETH_get_BMR_USP(void);
  2418. /*! \brief Writes the bit group 'PBL4X' of register 'ETH_BMR'. */
  2419. void GH_ETH_set_BMR_PBL4X(U8 data);
  2420. /*! \brief Reads the bit group 'PBL4X' of register 'ETH_BMR'. */
  2421. U8 GH_ETH_get_BMR_PBL4X(void);
  2422. /*! \brief Writes the bit group 'AAL' of register 'ETH_BMR'. */
  2423. void GH_ETH_set_BMR_AAL(U8 data);
  2424. /*! \brief Reads the bit group 'AAL' of register 'ETH_BMR'. */
  2425. U8 GH_ETH_get_BMR_AAL(void);
  2426. #else /* GH_INLINE_LEVEL == 0 */
  2427. GH_INLINE void GH_ETH_set_BMR(U32 data)
  2428. {
  2429. *(volatile U32 *)REG_ETH_BMR = data;
  2430. #if GH_ETH_ENABLE_DEBUG_PRINT
  2431. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR] <-- 0x%08x\n",
  2432. REG_ETH_BMR,data,data);
  2433. #endif
  2434. }
  2435. GH_INLINE U32 GH_ETH_get_BMR(void)
  2436. {
  2437. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2438. #if GH_ETH_ENABLE_DEBUG_PRINT
  2439. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR] --> 0x%08x\n",
  2440. REG_ETH_BMR,value);
  2441. #endif
  2442. return value;
  2443. }
  2444. GH_INLINE void GH_ETH_set_BMR_SWR(U8 data)
  2445. {
  2446. GH_ETH_BMR_S d;
  2447. d.all = *(volatile U32 *)REG_ETH_BMR;
  2448. d.bitc.swr = data;
  2449. *(volatile U32 *)REG_ETH_BMR = d.all;
  2450. #if GH_ETH_ENABLE_DEBUG_PRINT
  2451. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_SWR] <-- 0x%08x\n",
  2452. REG_ETH_BMR,d.all,d.all);
  2453. #endif
  2454. }
  2455. GH_INLINE U8 GH_ETH_get_BMR_SWR(void)
  2456. {
  2457. GH_ETH_BMR_S tmp_value;
  2458. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2459. tmp_value.all = value;
  2460. #if GH_ETH_ENABLE_DEBUG_PRINT
  2461. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_SWR] --> 0x%08x\n",
  2462. REG_ETH_BMR,value);
  2463. #endif
  2464. return tmp_value.bitc.swr;
  2465. }
  2466. GH_INLINE void GH_ETH_set_BMR_DA(U8 data)
  2467. {
  2468. GH_ETH_BMR_S d;
  2469. d.all = *(volatile U32 *)REG_ETH_BMR;
  2470. d.bitc.da = data;
  2471. *(volatile U32 *)REG_ETH_BMR = d.all;
  2472. #if GH_ETH_ENABLE_DEBUG_PRINT
  2473. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_DA] <-- 0x%08x\n",
  2474. REG_ETH_BMR,d.all,d.all);
  2475. #endif
  2476. }
  2477. GH_INLINE U8 GH_ETH_get_BMR_DA(void)
  2478. {
  2479. GH_ETH_BMR_S tmp_value;
  2480. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2481. tmp_value.all = value;
  2482. #if GH_ETH_ENABLE_DEBUG_PRINT
  2483. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_DA] --> 0x%08x\n",
  2484. REG_ETH_BMR,value);
  2485. #endif
  2486. return tmp_value.bitc.da;
  2487. }
  2488. GH_INLINE void GH_ETH_set_BMR_DSL(U8 data)
  2489. {
  2490. GH_ETH_BMR_S d;
  2491. d.all = *(volatile U32 *)REG_ETH_BMR;
  2492. d.bitc.dsl = data;
  2493. *(volatile U32 *)REG_ETH_BMR = d.all;
  2494. #if GH_ETH_ENABLE_DEBUG_PRINT
  2495. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_DSL] <-- 0x%08x\n",
  2496. REG_ETH_BMR,d.all,d.all);
  2497. #endif
  2498. }
  2499. GH_INLINE U8 GH_ETH_get_BMR_DSL(void)
  2500. {
  2501. GH_ETH_BMR_S tmp_value;
  2502. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2503. tmp_value.all = value;
  2504. #if GH_ETH_ENABLE_DEBUG_PRINT
  2505. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_DSL] --> 0x%08x\n",
  2506. REG_ETH_BMR,value);
  2507. #endif
  2508. return tmp_value.bitc.dsl;
  2509. }
  2510. GH_INLINE void GH_ETH_set_BMR_PBL(U8 data)
  2511. {
  2512. GH_ETH_BMR_S d;
  2513. d.all = *(volatile U32 *)REG_ETH_BMR;
  2514. d.bitc.pbl = data;
  2515. *(volatile U32 *)REG_ETH_BMR = d.all;
  2516. #if GH_ETH_ENABLE_DEBUG_PRINT
  2517. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_PBL] <-- 0x%08x\n",
  2518. REG_ETH_BMR,d.all,d.all);
  2519. #endif
  2520. }
  2521. GH_INLINE U8 GH_ETH_get_BMR_PBL(void)
  2522. {
  2523. GH_ETH_BMR_S tmp_value;
  2524. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2525. tmp_value.all = value;
  2526. #if GH_ETH_ENABLE_DEBUG_PRINT
  2527. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_PBL] --> 0x%08x\n",
  2528. REG_ETH_BMR,value);
  2529. #endif
  2530. return tmp_value.bitc.pbl;
  2531. }
  2532. GH_INLINE void GH_ETH_set_BMR_PR(U8 data)
  2533. {
  2534. GH_ETH_BMR_S d;
  2535. d.all = *(volatile U32 *)REG_ETH_BMR;
  2536. d.bitc.pr = data;
  2537. *(volatile U32 *)REG_ETH_BMR = d.all;
  2538. #if GH_ETH_ENABLE_DEBUG_PRINT
  2539. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_PR] <-- 0x%08x\n",
  2540. REG_ETH_BMR,d.all,d.all);
  2541. #endif
  2542. }
  2543. GH_INLINE U8 GH_ETH_get_BMR_PR(void)
  2544. {
  2545. GH_ETH_BMR_S tmp_value;
  2546. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2547. tmp_value.all = value;
  2548. #if GH_ETH_ENABLE_DEBUG_PRINT
  2549. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_PR] --> 0x%08x\n",
  2550. REG_ETH_BMR,value);
  2551. #endif
  2552. return tmp_value.bitc.pr;
  2553. }
  2554. GH_INLINE void GH_ETH_set_BMR_FB(U8 data)
  2555. {
  2556. GH_ETH_BMR_S d;
  2557. d.all = *(volatile U32 *)REG_ETH_BMR;
  2558. d.bitc.fb = data;
  2559. *(volatile U32 *)REG_ETH_BMR = d.all;
  2560. #if GH_ETH_ENABLE_DEBUG_PRINT
  2561. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_FB] <-- 0x%08x\n",
  2562. REG_ETH_BMR,d.all,d.all);
  2563. #endif
  2564. }
  2565. GH_INLINE U8 GH_ETH_get_BMR_FB(void)
  2566. {
  2567. GH_ETH_BMR_S tmp_value;
  2568. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2569. tmp_value.all = value;
  2570. #if GH_ETH_ENABLE_DEBUG_PRINT
  2571. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_FB] --> 0x%08x\n",
  2572. REG_ETH_BMR,value);
  2573. #endif
  2574. return tmp_value.bitc.fb;
  2575. }
  2576. GH_INLINE void GH_ETH_set_BMR_RPBL(U8 data)
  2577. {
  2578. GH_ETH_BMR_S d;
  2579. d.all = *(volatile U32 *)REG_ETH_BMR;
  2580. d.bitc.rpbl = data;
  2581. *(volatile U32 *)REG_ETH_BMR = d.all;
  2582. #if GH_ETH_ENABLE_DEBUG_PRINT
  2583. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_RPBL] <-- 0x%08x\n",
  2584. REG_ETH_BMR,d.all,d.all);
  2585. #endif
  2586. }
  2587. GH_INLINE U8 GH_ETH_get_BMR_RPBL(void)
  2588. {
  2589. GH_ETH_BMR_S tmp_value;
  2590. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2591. tmp_value.all = value;
  2592. #if GH_ETH_ENABLE_DEBUG_PRINT
  2593. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_RPBL] --> 0x%08x\n",
  2594. REG_ETH_BMR,value);
  2595. #endif
  2596. return tmp_value.bitc.rpbl;
  2597. }
  2598. GH_INLINE void GH_ETH_set_BMR_USP(U8 data)
  2599. {
  2600. GH_ETH_BMR_S d;
  2601. d.all = *(volatile U32 *)REG_ETH_BMR;
  2602. d.bitc.usp = data;
  2603. *(volatile U32 *)REG_ETH_BMR = d.all;
  2604. #if GH_ETH_ENABLE_DEBUG_PRINT
  2605. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_USP] <-- 0x%08x\n",
  2606. REG_ETH_BMR,d.all,d.all);
  2607. #endif
  2608. }
  2609. GH_INLINE U8 GH_ETH_get_BMR_USP(void)
  2610. {
  2611. GH_ETH_BMR_S tmp_value;
  2612. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2613. tmp_value.all = value;
  2614. #if GH_ETH_ENABLE_DEBUG_PRINT
  2615. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_USP] --> 0x%08x\n",
  2616. REG_ETH_BMR,value);
  2617. #endif
  2618. return tmp_value.bitc.usp;
  2619. }
  2620. GH_INLINE void GH_ETH_set_BMR_PBL4X(U8 data)
  2621. {
  2622. GH_ETH_BMR_S d;
  2623. d.all = *(volatile U32 *)REG_ETH_BMR;
  2624. d.bitc.pbl4x = data;
  2625. *(volatile U32 *)REG_ETH_BMR = d.all;
  2626. #if GH_ETH_ENABLE_DEBUG_PRINT
  2627. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_PBL4X] <-- 0x%08x\n",
  2628. REG_ETH_BMR,d.all,d.all);
  2629. #endif
  2630. }
  2631. GH_INLINE U8 GH_ETH_get_BMR_PBL4X(void)
  2632. {
  2633. GH_ETH_BMR_S tmp_value;
  2634. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2635. tmp_value.all = value;
  2636. #if GH_ETH_ENABLE_DEBUG_PRINT
  2637. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_PBL4X] --> 0x%08x\n",
  2638. REG_ETH_BMR,value);
  2639. #endif
  2640. return tmp_value.bitc.pbl4x;
  2641. }
  2642. GH_INLINE void GH_ETH_set_BMR_AAL(U8 data)
  2643. {
  2644. GH_ETH_BMR_S d;
  2645. d.all = *(volatile U32 *)REG_ETH_BMR;
  2646. d.bitc.aal = data;
  2647. *(volatile U32 *)REG_ETH_BMR = d.all;
  2648. #if GH_ETH_ENABLE_DEBUG_PRINT
  2649. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_BMR_AAL] <-- 0x%08x\n",
  2650. REG_ETH_BMR,d.all,d.all);
  2651. #endif
  2652. }
  2653. GH_INLINE U8 GH_ETH_get_BMR_AAL(void)
  2654. {
  2655. GH_ETH_BMR_S tmp_value;
  2656. U32 value = (*(volatile U32 *)REG_ETH_BMR);
  2657. tmp_value.all = value;
  2658. #if GH_ETH_ENABLE_DEBUG_PRINT
  2659. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_BMR_AAL] --> 0x%08x\n",
  2660. REG_ETH_BMR,value);
  2661. #endif
  2662. return tmp_value.bitc.aal;
  2663. }
  2664. #endif /* GH_INLINE_LEVEL == 0 */
  2665. /*----------------------------------------------------------------------------*/
  2666. /* register ETH_RDLAR (read/write) */
  2667. /*----------------------------------------------------------------------------*/
  2668. #if GH_INLINE_LEVEL == 0
  2669. /*! \brief Writes the register 'ETH_RDLAR'. */
  2670. void GH_ETH_set_RDLAR(U32 data);
  2671. /*! \brief Reads the register 'ETH_RDLAR'. */
  2672. U32 GH_ETH_get_RDLAR(void);
  2673. #else /* GH_INLINE_LEVEL == 0 */
  2674. GH_INLINE void GH_ETH_set_RDLAR(U32 data)
  2675. {
  2676. *(volatile U32 *)REG_ETH_RDLAR = data;
  2677. #if GH_ETH_ENABLE_DEBUG_PRINT
  2678. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_RDLAR] <-- 0x%08x\n",
  2679. REG_ETH_RDLAR,data,data);
  2680. #endif
  2681. }
  2682. GH_INLINE U32 GH_ETH_get_RDLAR(void)
  2683. {
  2684. U32 value = (*(volatile U32 *)REG_ETH_RDLAR);
  2685. #if GH_ETH_ENABLE_DEBUG_PRINT
  2686. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_RDLAR] --> 0x%08x\n",
  2687. REG_ETH_RDLAR,value);
  2688. #endif
  2689. return value;
  2690. }
  2691. #endif /* GH_INLINE_LEVEL == 0 */
  2692. /*----------------------------------------------------------------------------*/
  2693. /* register ETH_TDLAR (read/write) */
  2694. /*----------------------------------------------------------------------------*/
  2695. #if GH_INLINE_LEVEL == 0
  2696. /*! \brief Writes the register 'ETH_TDLAR'. */
  2697. void GH_ETH_set_TDLAR(U32 data);
  2698. /*! \brief Reads the register 'ETH_TDLAR'. */
  2699. U32 GH_ETH_get_TDLAR(void);
  2700. #else /* GH_INLINE_LEVEL == 0 */
  2701. GH_INLINE void GH_ETH_set_TDLAR(U32 data)
  2702. {
  2703. *(volatile U32 *)REG_ETH_TDLAR = data;
  2704. #if GH_ETH_ENABLE_DEBUG_PRINT
  2705. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_TDLAR] <-- 0x%08x\n",
  2706. REG_ETH_TDLAR,data,data);
  2707. #endif
  2708. }
  2709. GH_INLINE U32 GH_ETH_get_TDLAR(void)
  2710. {
  2711. U32 value = (*(volatile U32 *)REG_ETH_TDLAR);
  2712. #if GH_ETH_ENABLE_DEBUG_PRINT
  2713. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_TDLAR] --> 0x%08x\n",
  2714. REG_ETH_TDLAR,value);
  2715. #endif
  2716. return value;
  2717. }
  2718. #endif /* GH_INLINE_LEVEL == 0 */
  2719. /*----------------------------------------------------------------------------*/
  2720. /* register ETH_SR (read/write) */
  2721. /*----------------------------------------------------------------------------*/
  2722. #if GH_INLINE_LEVEL == 0
  2723. /*! \brief Writes the register 'ETH_SR'. */
  2724. void GH_ETH_set_SR(U32 data);
  2725. /*! \brief Reads the register 'ETH_SR'. */
  2726. U32 GH_ETH_get_SR(void);
  2727. /*! \brief Writes the bit group 'TI' of register 'ETH_SR'. */
  2728. void GH_ETH_set_SR_TI(U8 data);
  2729. /*! \brief Reads the bit group 'TI' of register 'ETH_SR'. */
  2730. U8 GH_ETH_get_SR_TI(void);
  2731. /*! \brief Writes the bit group 'TPS' of register 'ETH_SR'. */
  2732. void GH_ETH_set_SR_TPS(U8 data);
  2733. /*! \brief Reads the bit group 'TPS' of register 'ETH_SR'. */
  2734. U8 GH_ETH_get_SR_TPS(void);
  2735. /*! \brief Writes the bit group 'TU' of register 'ETH_SR'. */
  2736. void GH_ETH_set_SR_TU(U8 data);
  2737. /*! \brief Reads the bit group 'TU' of register 'ETH_SR'. */
  2738. U8 GH_ETH_get_SR_TU(void);
  2739. /*! \brief Writes the bit group 'TJT' of register 'ETH_SR'. */
  2740. void GH_ETH_set_SR_TJT(U8 data);
  2741. /*! \brief Reads the bit group 'TJT' of register 'ETH_SR'. */
  2742. U8 GH_ETH_get_SR_TJT(void);
  2743. /*! \brief Writes the bit group 'OVF' of register 'ETH_SR'. */
  2744. void GH_ETH_set_SR_OVF(U8 data);
  2745. /*! \brief Reads the bit group 'OVF' of register 'ETH_SR'. */
  2746. U8 GH_ETH_get_SR_OVF(void);
  2747. /*! \brief Writes the bit group 'UNF' of register 'ETH_SR'. */
  2748. void GH_ETH_set_SR_UNF(U8 data);
  2749. /*! \brief Reads the bit group 'UNF' of register 'ETH_SR'. */
  2750. U8 GH_ETH_get_SR_UNF(void);
  2751. /*! \brief Writes the bit group 'RI' of register 'ETH_SR'. */
  2752. void GH_ETH_set_SR_RI(U8 data);
  2753. /*! \brief Reads the bit group 'RI' of register 'ETH_SR'. */
  2754. U8 GH_ETH_get_SR_RI(void);
  2755. /*! \brief Writes the bit group 'RU' of register 'ETH_SR'. */
  2756. void GH_ETH_set_SR_RU(U8 data);
  2757. /*! \brief Reads the bit group 'RU' of register 'ETH_SR'. */
  2758. U8 GH_ETH_get_SR_RU(void);
  2759. /*! \brief Writes the bit group 'RPS' of register 'ETH_SR'. */
  2760. void GH_ETH_set_SR_RPS(U8 data);
  2761. /*! \brief Reads the bit group 'RPS' of register 'ETH_SR'. */
  2762. U8 GH_ETH_get_SR_RPS(void);
  2763. /*! \brief Writes the bit group 'RWT' of register 'ETH_SR'. */
  2764. void GH_ETH_set_SR_RWT(U8 data);
  2765. /*! \brief Reads the bit group 'RWT' of register 'ETH_SR'. */
  2766. U8 GH_ETH_get_SR_RWT(void);
  2767. /*! \brief Writes the bit group 'ETI' of register 'ETH_SR'. */
  2768. void GH_ETH_set_SR_ETI(U8 data);
  2769. /*! \brief Reads the bit group 'ETI' of register 'ETH_SR'. */
  2770. U8 GH_ETH_get_SR_ETI(void);
  2771. /*! \brief Writes the bit group 'FBE' of register 'ETH_SR'. */
  2772. void GH_ETH_set_SR_FBE(U8 data);
  2773. /*! \brief Reads the bit group 'FBE' of register 'ETH_SR'. */
  2774. U8 GH_ETH_get_SR_FBE(void);
  2775. /*! \brief Writes the bit group 'ERI' of register 'ETH_SR'. */
  2776. void GH_ETH_set_SR_ERI(U8 data);
  2777. /*! \brief Reads the bit group 'ERI' of register 'ETH_SR'. */
  2778. U8 GH_ETH_get_SR_ERI(void);
  2779. /*! \brief Writes the bit group 'AIS' of register 'ETH_SR'. */
  2780. void GH_ETH_set_SR_AIS(U8 data);
  2781. /*! \brief Reads the bit group 'AIS' of register 'ETH_SR'. */
  2782. U8 GH_ETH_get_SR_AIS(void);
  2783. /*! \brief Writes the bit group 'NIS' of register 'ETH_SR'. */
  2784. void GH_ETH_set_SR_NIS(U8 data);
  2785. /*! \brief Reads the bit group 'NIS' of register 'ETH_SR'. */
  2786. U8 GH_ETH_get_SR_NIS(void);
  2787. /*! \brief Writes the bit group 'RS' of register 'ETH_SR'. */
  2788. void GH_ETH_set_SR_RS(U8 data);
  2789. /*! \brief Reads the bit group 'RS' of register 'ETH_SR'. */
  2790. U8 GH_ETH_get_SR_RS(void);
  2791. /*! \brief Writes the bit group 'TS' of register 'ETH_SR'. */
  2792. void GH_ETH_set_SR_TS(U8 data);
  2793. /*! \brief Reads the bit group 'TS' of register 'ETH_SR'. */
  2794. U8 GH_ETH_get_SR_TS(void);
  2795. /*! \brief Writes the bit group 'EB' of register 'ETH_SR'. */
  2796. void GH_ETH_set_SR_EB(U8 data);
  2797. /*! \brief Reads the bit group 'EB' of register 'ETH_SR'. */
  2798. U8 GH_ETH_get_SR_EB(void);
  2799. /*! \brief Writes the bit group 'GLI' of register 'ETH_SR'. */
  2800. void GH_ETH_set_SR_GLI(U8 data);
  2801. /*! \brief Reads the bit group 'GLI' of register 'ETH_SR'. */
  2802. U8 GH_ETH_get_SR_GLI(void);
  2803. /*! \brief Writes the bit group 'GMI' of register 'ETH_SR'. */
  2804. void GH_ETH_set_SR_GMI(U8 data);
  2805. /*! \brief Reads the bit group 'GMI' of register 'ETH_SR'. */
  2806. U8 GH_ETH_get_SR_GMI(void);
  2807. /*! \brief Writes the bit group 'GPI' of register 'ETH_SR'. */
  2808. void GH_ETH_set_SR_GPI(U8 data);
  2809. /*! \brief Reads the bit group 'GPI' of register 'ETH_SR'. */
  2810. U8 GH_ETH_get_SR_GPI(void);
  2811. #else /* GH_INLINE_LEVEL == 0 */
  2812. GH_INLINE void GH_ETH_set_SR(U32 data)
  2813. {
  2814. *(volatile U32 *)REG_ETH_SR = data;
  2815. #if GH_ETH_ENABLE_DEBUG_PRINT
  2816. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR] <-- 0x%08x\n",
  2817. REG_ETH_SR,data,data);
  2818. #endif
  2819. }
  2820. GH_INLINE U32 GH_ETH_get_SR(void)
  2821. {
  2822. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2823. #if GH_ETH_ENABLE_DEBUG_PRINT
  2824. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR] --> 0x%08x\n",
  2825. REG_ETH_SR,value);
  2826. #endif
  2827. return value;
  2828. }
  2829. GH_INLINE void GH_ETH_set_SR_TI(U8 data)
  2830. {
  2831. GH_ETH_SR_S d;
  2832. d.all = *(volatile U32 *)REG_ETH_SR;
  2833. d.bitc.ti = data;
  2834. *(volatile U32 *)REG_ETH_SR = d.all;
  2835. #if GH_ETH_ENABLE_DEBUG_PRINT
  2836. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_TI] <-- 0x%08x\n",
  2837. REG_ETH_SR,d.all,d.all);
  2838. #endif
  2839. }
  2840. GH_INLINE U8 GH_ETH_get_SR_TI(void)
  2841. {
  2842. GH_ETH_SR_S tmp_value;
  2843. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2844. tmp_value.all = value;
  2845. #if GH_ETH_ENABLE_DEBUG_PRINT
  2846. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_TI] --> 0x%08x\n",
  2847. REG_ETH_SR,value);
  2848. #endif
  2849. return tmp_value.bitc.ti;
  2850. }
  2851. GH_INLINE void GH_ETH_set_SR_TPS(U8 data)
  2852. {
  2853. GH_ETH_SR_S d;
  2854. d.all = *(volatile U32 *)REG_ETH_SR;
  2855. d.bitc.tps = data;
  2856. *(volatile U32 *)REG_ETH_SR = d.all;
  2857. #if GH_ETH_ENABLE_DEBUG_PRINT
  2858. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_TPS] <-- 0x%08x\n",
  2859. REG_ETH_SR,d.all,d.all);
  2860. #endif
  2861. }
  2862. GH_INLINE U8 GH_ETH_get_SR_TPS(void)
  2863. {
  2864. GH_ETH_SR_S tmp_value;
  2865. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2866. tmp_value.all = value;
  2867. #if GH_ETH_ENABLE_DEBUG_PRINT
  2868. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_TPS] --> 0x%08x\n",
  2869. REG_ETH_SR,value);
  2870. #endif
  2871. return tmp_value.bitc.tps;
  2872. }
  2873. GH_INLINE void GH_ETH_set_SR_TU(U8 data)
  2874. {
  2875. GH_ETH_SR_S d;
  2876. d.all = *(volatile U32 *)REG_ETH_SR;
  2877. d.bitc.tu = data;
  2878. *(volatile U32 *)REG_ETH_SR = d.all;
  2879. #if GH_ETH_ENABLE_DEBUG_PRINT
  2880. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_TU] <-- 0x%08x\n",
  2881. REG_ETH_SR,d.all,d.all);
  2882. #endif
  2883. }
  2884. GH_INLINE U8 GH_ETH_get_SR_TU(void)
  2885. {
  2886. GH_ETH_SR_S tmp_value;
  2887. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2888. tmp_value.all = value;
  2889. #if GH_ETH_ENABLE_DEBUG_PRINT
  2890. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_TU] --> 0x%08x\n",
  2891. REG_ETH_SR,value);
  2892. #endif
  2893. return tmp_value.bitc.tu;
  2894. }
  2895. GH_INLINE void GH_ETH_set_SR_TJT(U8 data)
  2896. {
  2897. GH_ETH_SR_S d;
  2898. d.all = *(volatile U32 *)REG_ETH_SR;
  2899. d.bitc.tjt = data;
  2900. *(volatile U32 *)REG_ETH_SR = d.all;
  2901. #if GH_ETH_ENABLE_DEBUG_PRINT
  2902. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_TJT] <-- 0x%08x\n",
  2903. REG_ETH_SR,d.all,d.all);
  2904. #endif
  2905. }
  2906. GH_INLINE U8 GH_ETH_get_SR_TJT(void)
  2907. {
  2908. GH_ETH_SR_S tmp_value;
  2909. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2910. tmp_value.all = value;
  2911. #if GH_ETH_ENABLE_DEBUG_PRINT
  2912. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_TJT] --> 0x%08x\n",
  2913. REG_ETH_SR,value);
  2914. #endif
  2915. return tmp_value.bitc.tjt;
  2916. }
  2917. GH_INLINE void GH_ETH_set_SR_OVF(U8 data)
  2918. {
  2919. GH_ETH_SR_S d;
  2920. d.all = *(volatile U32 *)REG_ETH_SR;
  2921. d.bitc.ovf = data;
  2922. *(volatile U32 *)REG_ETH_SR = d.all;
  2923. #if GH_ETH_ENABLE_DEBUG_PRINT
  2924. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_OVF] <-- 0x%08x\n",
  2925. REG_ETH_SR,d.all,d.all);
  2926. #endif
  2927. }
  2928. GH_INLINE U8 GH_ETH_get_SR_OVF(void)
  2929. {
  2930. GH_ETH_SR_S tmp_value;
  2931. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2932. tmp_value.all = value;
  2933. #if GH_ETH_ENABLE_DEBUG_PRINT
  2934. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_OVF] --> 0x%08x\n",
  2935. REG_ETH_SR,value);
  2936. #endif
  2937. return tmp_value.bitc.ovf;
  2938. }
  2939. GH_INLINE void GH_ETH_set_SR_UNF(U8 data)
  2940. {
  2941. GH_ETH_SR_S d;
  2942. d.all = *(volatile U32 *)REG_ETH_SR;
  2943. d.bitc.unf = data;
  2944. *(volatile U32 *)REG_ETH_SR = d.all;
  2945. #if GH_ETH_ENABLE_DEBUG_PRINT
  2946. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_UNF] <-- 0x%08x\n",
  2947. REG_ETH_SR,d.all,d.all);
  2948. #endif
  2949. }
  2950. GH_INLINE U8 GH_ETH_get_SR_UNF(void)
  2951. {
  2952. GH_ETH_SR_S tmp_value;
  2953. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2954. tmp_value.all = value;
  2955. #if GH_ETH_ENABLE_DEBUG_PRINT
  2956. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_UNF] --> 0x%08x\n",
  2957. REG_ETH_SR,value);
  2958. #endif
  2959. return tmp_value.bitc.unf;
  2960. }
  2961. GH_INLINE void GH_ETH_set_SR_RI(U8 data)
  2962. {
  2963. GH_ETH_SR_S d;
  2964. d.all = *(volatile U32 *)REG_ETH_SR;
  2965. d.bitc.ri = data;
  2966. *(volatile U32 *)REG_ETH_SR = d.all;
  2967. #if GH_ETH_ENABLE_DEBUG_PRINT
  2968. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_RI] <-- 0x%08x\n",
  2969. REG_ETH_SR,d.all,d.all);
  2970. #endif
  2971. }
  2972. GH_INLINE U8 GH_ETH_get_SR_RI(void)
  2973. {
  2974. GH_ETH_SR_S tmp_value;
  2975. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2976. tmp_value.all = value;
  2977. #if GH_ETH_ENABLE_DEBUG_PRINT
  2978. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_RI] --> 0x%08x\n",
  2979. REG_ETH_SR,value);
  2980. #endif
  2981. return tmp_value.bitc.ri;
  2982. }
  2983. GH_INLINE void GH_ETH_set_SR_RU(U8 data)
  2984. {
  2985. GH_ETH_SR_S d;
  2986. d.all = *(volatile U32 *)REG_ETH_SR;
  2987. d.bitc.ru = data;
  2988. *(volatile U32 *)REG_ETH_SR = d.all;
  2989. #if GH_ETH_ENABLE_DEBUG_PRINT
  2990. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_RU] <-- 0x%08x\n",
  2991. REG_ETH_SR,d.all,d.all);
  2992. #endif
  2993. }
  2994. GH_INLINE U8 GH_ETH_get_SR_RU(void)
  2995. {
  2996. GH_ETH_SR_S tmp_value;
  2997. U32 value = (*(volatile U32 *)REG_ETH_SR);
  2998. tmp_value.all = value;
  2999. #if GH_ETH_ENABLE_DEBUG_PRINT
  3000. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_RU] --> 0x%08x\n",
  3001. REG_ETH_SR,value);
  3002. #endif
  3003. return tmp_value.bitc.ru;
  3004. }
  3005. GH_INLINE void GH_ETH_set_SR_RPS(U8 data)
  3006. {
  3007. GH_ETH_SR_S d;
  3008. d.all = *(volatile U32 *)REG_ETH_SR;
  3009. d.bitc.rps = data;
  3010. *(volatile U32 *)REG_ETH_SR = d.all;
  3011. #if GH_ETH_ENABLE_DEBUG_PRINT
  3012. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_RPS] <-- 0x%08x\n",
  3013. REG_ETH_SR,d.all,d.all);
  3014. #endif
  3015. }
  3016. GH_INLINE U8 GH_ETH_get_SR_RPS(void)
  3017. {
  3018. GH_ETH_SR_S tmp_value;
  3019. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3020. tmp_value.all = value;
  3021. #if GH_ETH_ENABLE_DEBUG_PRINT
  3022. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_RPS] --> 0x%08x\n",
  3023. REG_ETH_SR,value);
  3024. #endif
  3025. return tmp_value.bitc.rps;
  3026. }
  3027. GH_INLINE void GH_ETH_set_SR_RWT(U8 data)
  3028. {
  3029. GH_ETH_SR_S d;
  3030. d.all = *(volatile U32 *)REG_ETH_SR;
  3031. d.bitc.rwt = data;
  3032. *(volatile U32 *)REG_ETH_SR = d.all;
  3033. #if GH_ETH_ENABLE_DEBUG_PRINT
  3034. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_RWT] <-- 0x%08x\n",
  3035. REG_ETH_SR,d.all,d.all);
  3036. #endif
  3037. }
  3038. GH_INLINE U8 GH_ETH_get_SR_RWT(void)
  3039. {
  3040. GH_ETH_SR_S tmp_value;
  3041. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3042. tmp_value.all = value;
  3043. #if GH_ETH_ENABLE_DEBUG_PRINT
  3044. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_RWT] --> 0x%08x\n",
  3045. REG_ETH_SR,value);
  3046. #endif
  3047. return tmp_value.bitc.rwt;
  3048. }
  3049. GH_INLINE void GH_ETH_set_SR_ETI(U8 data)
  3050. {
  3051. GH_ETH_SR_S d;
  3052. d.all = *(volatile U32 *)REG_ETH_SR;
  3053. d.bitc.eti = data;
  3054. *(volatile U32 *)REG_ETH_SR = d.all;
  3055. #if GH_ETH_ENABLE_DEBUG_PRINT
  3056. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_ETI] <-- 0x%08x\n",
  3057. REG_ETH_SR,d.all,d.all);
  3058. #endif
  3059. }
  3060. GH_INLINE U8 GH_ETH_get_SR_ETI(void)
  3061. {
  3062. GH_ETH_SR_S tmp_value;
  3063. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3064. tmp_value.all = value;
  3065. #if GH_ETH_ENABLE_DEBUG_PRINT
  3066. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_ETI] --> 0x%08x\n",
  3067. REG_ETH_SR,value);
  3068. #endif
  3069. return tmp_value.bitc.eti;
  3070. }
  3071. GH_INLINE void GH_ETH_set_SR_FBE(U8 data)
  3072. {
  3073. GH_ETH_SR_S d;
  3074. d.all = *(volatile U32 *)REG_ETH_SR;
  3075. d.bitc.fbe = data;
  3076. *(volatile U32 *)REG_ETH_SR = d.all;
  3077. #if GH_ETH_ENABLE_DEBUG_PRINT
  3078. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_FBE] <-- 0x%08x\n",
  3079. REG_ETH_SR,d.all,d.all);
  3080. #endif
  3081. }
  3082. GH_INLINE U8 GH_ETH_get_SR_FBE(void)
  3083. {
  3084. GH_ETH_SR_S tmp_value;
  3085. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3086. tmp_value.all = value;
  3087. #if GH_ETH_ENABLE_DEBUG_PRINT
  3088. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_FBE] --> 0x%08x\n",
  3089. REG_ETH_SR,value);
  3090. #endif
  3091. return tmp_value.bitc.fbe;
  3092. }
  3093. GH_INLINE void GH_ETH_set_SR_ERI(U8 data)
  3094. {
  3095. GH_ETH_SR_S d;
  3096. d.all = *(volatile U32 *)REG_ETH_SR;
  3097. d.bitc.eri = data;
  3098. *(volatile U32 *)REG_ETH_SR = d.all;
  3099. #if GH_ETH_ENABLE_DEBUG_PRINT
  3100. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_ERI] <-- 0x%08x\n",
  3101. REG_ETH_SR,d.all,d.all);
  3102. #endif
  3103. }
  3104. GH_INLINE U8 GH_ETH_get_SR_ERI(void)
  3105. {
  3106. GH_ETH_SR_S tmp_value;
  3107. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3108. tmp_value.all = value;
  3109. #if GH_ETH_ENABLE_DEBUG_PRINT
  3110. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_ERI] --> 0x%08x\n",
  3111. REG_ETH_SR,value);
  3112. #endif
  3113. return tmp_value.bitc.eri;
  3114. }
  3115. GH_INLINE void GH_ETH_set_SR_AIS(U8 data)
  3116. {
  3117. GH_ETH_SR_S d;
  3118. d.all = *(volatile U32 *)REG_ETH_SR;
  3119. d.bitc.ais = data;
  3120. *(volatile U32 *)REG_ETH_SR = d.all;
  3121. #if GH_ETH_ENABLE_DEBUG_PRINT
  3122. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_AIS] <-- 0x%08x\n",
  3123. REG_ETH_SR,d.all,d.all);
  3124. #endif
  3125. }
  3126. GH_INLINE U8 GH_ETH_get_SR_AIS(void)
  3127. {
  3128. GH_ETH_SR_S tmp_value;
  3129. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3130. tmp_value.all = value;
  3131. #if GH_ETH_ENABLE_DEBUG_PRINT
  3132. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_AIS] --> 0x%08x\n",
  3133. REG_ETH_SR,value);
  3134. #endif
  3135. return tmp_value.bitc.ais;
  3136. }
  3137. GH_INLINE void GH_ETH_set_SR_NIS(U8 data)
  3138. {
  3139. GH_ETH_SR_S d;
  3140. d.all = *(volatile U32 *)REG_ETH_SR;
  3141. d.bitc.nis = data;
  3142. *(volatile U32 *)REG_ETH_SR = d.all;
  3143. #if GH_ETH_ENABLE_DEBUG_PRINT
  3144. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_NIS] <-- 0x%08x\n",
  3145. REG_ETH_SR,d.all,d.all);
  3146. #endif
  3147. }
  3148. GH_INLINE U8 GH_ETH_get_SR_NIS(void)
  3149. {
  3150. GH_ETH_SR_S tmp_value;
  3151. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3152. tmp_value.all = value;
  3153. #if GH_ETH_ENABLE_DEBUG_PRINT
  3154. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_NIS] --> 0x%08x\n",
  3155. REG_ETH_SR,value);
  3156. #endif
  3157. return tmp_value.bitc.nis;
  3158. }
  3159. GH_INLINE void GH_ETH_set_SR_RS(U8 data)
  3160. {
  3161. GH_ETH_SR_S d;
  3162. d.all = *(volatile U32 *)REG_ETH_SR;
  3163. d.bitc.rs = data;
  3164. *(volatile U32 *)REG_ETH_SR = d.all;
  3165. #if GH_ETH_ENABLE_DEBUG_PRINT
  3166. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_RS] <-- 0x%08x\n",
  3167. REG_ETH_SR,d.all,d.all);
  3168. #endif
  3169. }
  3170. GH_INLINE U8 GH_ETH_get_SR_RS(void)
  3171. {
  3172. GH_ETH_SR_S tmp_value;
  3173. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3174. tmp_value.all = value;
  3175. #if GH_ETH_ENABLE_DEBUG_PRINT
  3176. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_RS] --> 0x%08x\n",
  3177. REG_ETH_SR,value);
  3178. #endif
  3179. return tmp_value.bitc.rs;
  3180. }
  3181. GH_INLINE void GH_ETH_set_SR_TS(U8 data)
  3182. {
  3183. GH_ETH_SR_S d;
  3184. d.all = *(volatile U32 *)REG_ETH_SR;
  3185. d.bitc.ts = data;
  3186. *(volatile U32 *)REG_ETH_SR = d.all;
  3187. #if GH_ETH_ENABLE_DEBUG_PRINT
  3188. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_TS] <-- 0x%08x\n",
  3189. REG_ETH_SR,d.all,d.all);
  3190. #endif
  3191. }
  3192. GH_INLINE U8 GH_ETH_get_SR_TS(void)
  3193. {
  3194. GH_ETH_SR_S tmp_value;
  3195. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3196. tmp_value.all = value;
  3197. #if GH_ETH_ENABLE_DEBUG_PRINT
  3198. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_TS] --> 0x%08x\n",
  3199. REG_ETH_SR,value);
  3200. #endif
  3201. return tmp_value.bitc.ts;
  3202. }
  3203. GH_INLINE void GH_ETH_set_SR_EB(U8 data)
  3204. {
  3205. GH_ETH_SR_S d;
  3206. d.all = *(volatile U32 *)REG_ETH_SR;
  3207. d.bitc.eb = data;
  3208. *(volatile U32 *)REG_ETH_SR = d.all;
  3209. #if GH_ETH_ENABLE_DEBUG_PRINT
  3210. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_EB] <-- 0x%08x\n",
  3211. REG_ETH_SR,d.all,d.all);
  3212. #endif
  3213. }
  3214. GH_INLINE U8 GH_ETH_get_SR_EB(void)
  3215. {
  3216. GH_ETH_SR_S tmp_value;
  3217. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3218. tmp_value.all = value;
  3219. #if GH_ETH_ENABLE_DEBUG_PRINT
  3220. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_EB] --> 0x%08x\n",
  3221. REG_ETH_SR,value);
  3222. #endif
  3223. return tmp_value.bitc.eb;
  3224. }
  3225. GH_INLINE void GH_ETH_set_SR_GLI(U8 data)
  3226. {
  3227. GH_ETH_SR_S d;
  3228. d.all = *(volatile U32 *)REG_ETH_SR;
  3229. d.bitc.gli = data;
  3230. *(volatile U32 *)REG_ETH_SR = d.all;
  3231. #if GH_ETH_ENABLE_DEBUG_PRINT
  3232. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_GLI] <-- 0x%08x\n",
  3233. REG_ETH_SR,d.all,d.all);
  3234. #endif
  3235. }
  3236. GH_INLINE U8 GH_ETH_get_SR_GLI(void)
  3237. {
  3238. GH_ETH_SR_S tmp_value;
  3239. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3240. tmp_value.all = value;
  3241. #if GH_ETH_ENABLE_DEBUG_PRINT
  3242. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_GLI] --> 0x%08x\n",
  3243. REG_ETH_SR,value);
  3244. #endif
  3245. return tmp_value.bitc.gli;
  3246. }
  3247. GH_INLINE void GH_ETH_set_SR_GMI(U8 data)
  3248. {
  3249. GH_ETH_SR_S d;
  3250. d.all = *(volatile U32 *)REG_ETH_SR;
  3251. d.bitc.gmi = data;
  3252. *(volatile U32 *)REG_ETH_SR = d.all;
  3253. #if GH_ETH_ENABLE_DEBUG_PRINT
  3254. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_GMI] <-- 0x%08x\n",
  3255. REG_ETH_SR,d.all,d.all);
  3256. #endif
  3257. }
  3258. GH_INLINE U8 GH_ETH_get_SR_GMI(void)
  3259. {
  3260. GH_ETH_SR_S tmp_value;
  3261. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3262. tmp_value.all = value;
  3263. #if GH_ETH_ENABLE_DEBUG_PRINT
  3264. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_GMI] --> 0x%08x\n",
  3265. REG_ETH_SR,value);
  3266. #endif
  3267. return tmp_value.bitc.gmi;
  3268. }
  3269. GH_INLINE void GH_ETH_set_SR_GPI(U8 data)
  3270. {
  3271. GH_ETH_SR_S d;
  3272. d.all = *(volatile U32 *)REG_ETH_SR;
  3273. d.bitc.gpi = data;
  3274. *(volatile U32 *)REG_ETH_SR = d.all;
  3275. #if GH_ETH_ENABLE_DEBUG_PRINT
  3276. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_SR_GPI] <-- 0x%08x\n",
  3277. REG_ETH_SR,d.all,d.all);
  3278. #endif
  3279. }
  3280. GH_INLINE U8 GH_ETH_get_SR_GPI(void)
  3281. {
  3282. GH_ETH_SR_S tmp_value;
  3283. U32 value = (*(volatile U32 *)REG_ETH_SR);
  3284. tmp_value.all = value;
  3285. #if GH_ETH_ENABLE_DEBUG_PRINT
  3286. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_SR_GPI] --> 0x%08x\n",
  3287. REG_ETH_SR,value);
  3288. #endif
  3289. return tmp_value.bitc.gpi;
  3290. }
  3291. #endif /* GH_INLINE_LEVEL == 0 */
  3292. /*----------------------------------------------------------------------------*/
  3293. /* register ETH_MFBOCR (read/write) */
  3294. /*----------------------------------------------------------------------------*/
  3295. #if GH_INLINE_LEVEL == 0
  3296. /*! \brief Writes the register 'ETH_MFBOCR'. */
  3297. void GH_ETH_set_MFBOCR(U32 data);
  3298. /*! \brief Reads the register 'ETH_MFBOCR'. */
  3299. U32 GH_ETH_get_MFBOCR(void);
  3300. /*! \brief Writes the bit group 'NMFH' of register 'ETH_MFBOCR'. */
  3301. void GH_ETH_set_MFBOCR_NMFH(U16 data);
  3302. /*! \brief Reads the bit group 'NMFH' of register 'ETH_MFBOCR'. */
  3303. U16 GH_ETH_get_MFBOCR_NMFH(void);
  3304. /*! \brief Writes the bit group 'OVMFC' of register 'ETH_MFBOCR'. */
  3305. void GH_ETH_set_MFBOCR_OVMFC(U8 data);
  3306. /*! \brief Reads the bit group 'OVMFC' of register 'ETH_MFBOCR'. */
  3307. U8 GH_ETH_get_MFBOCR_OVMFC(void);
  3308. /*! \brief Writes the bit group 'NMFF' of register 'ETH_MFBOCR'. */
  3309. void GH_ETH_set_MFBOCR_NMFF(U16 data);
  3310. /*! \brief Reads the bit group 'NMFF' of register 'ETH_MFBOCR'. */
  3311. U16 GH_ETH_get_MFBOCR_NMFF(void);
  3312. /*! \brief Writes the bit group 'ONMFF' of register 'ETH_MFBOCR'. */
  3313. void GH_ETH_set_MFBOCR_ONMFF(U8 data);
  3314. /*! \brief Reads the bit group 'ONMFF' of register 'ETH_MFBOCR'. */
  3315. U8 GH_ETH_get_MFBOCR_ONMFF(void);
  3316. #else /* GH_INLINE_LEVEL == 0 */
  3317. GH_INLINE void GH_ETH_set_MFBOCR(U32 data)
  3318. {
  3319. *(volatile U32 *)REG_ETH_MFBOCR = data;
  3320. #if GH_ETH_ENABLE_DEBUG_PRINT
  3321. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFBOCR] <-- 0x%08x\n",
  3322. REG_ETH_MFBOCR,data,data);
  3323. #endif
  3324. }
  3325. GH_INLINE U32 GH_ETH_get_MFBOCR(void)
  3326. {
  3327. U32 value = (*(volatile U32 *)REG_ETH_MFBOCR);
  3328. #if GH_ETH_ENABLE_DEBUG_PRINT
  3329. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFBOCR] --> 0x%08x\n",
  3330. REG_ETH_MFBOCR,value);
  3331. #endif
  3332. return value;
  3333. }
  3334. GH_INLINE void GH_ETH_set_MFBOCR_NMFH(U16 data)
  3335. {
  3336. GH_ETH_MFBOCR_S d;
  3337. d.all = *(volatile U32 *)REG_ETH_MFBOCR;
  3338. d.bitc.nmfh = data;
  3339. *(volatile U32 *)REG_ETH_MFBOCR = d.all;
  3340. #if GH_ETH_ENABLE_DEBUG_PRINT
  3341. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFBOCR_NMFH] <-- 0x%08x\n",
  3342. REG_ETH_MFBOCR,d.all,d.all);
  3343. #endif
  3344. }
  3345. GH_INLINE U16 GH_ETH_get_MFBOCR_NMFH(void)
  3346. {
  3347. GH_ETH_MFBOCR_S tmp_value;
  3348. U32 value = (*(volatile U32 *)REG_ETH_MFBOCR);
  3349. tmp_value.all = value;
  3350. #if GH_ETH_ENABLE_DEBUG_PRINT
  3351. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFBOCR_NMFH] --> 0x%08x\n",
  3352. REG_ETH_MFBOCR,value);
  3353. #endif
  3354. return tmp_value.bitc.nmfh;
  3355. }
  3356. GH_INLINE void GH_ETH_set_MFBOCR_OVMFC(U8 data)
  3357. {
  3358. GH_ETH_MFBOCR_S d;
  3359. d.all = *(volatile U32 *)REG_ETH_MFBOCR;
  3360. d.bitc.ovmfc = data;
  3361. *(volatile U32 *)REG_ETH_MFBOCR = d.all;
  3362. #if GH_ETH_ENABLE_DEBUG_PRINT
  3363. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFBOCR_OVMFC] <-- 0x%08x\n",
  3364. REG_ETH_MFBOCR,d.all,d.all);
  3365. #endif
  3366. }
  3367. GH_INLINE U8 GH_ETH_get_MFBOCR_OVMFC(void)
  3368. {
  3369. GH_ETH_MFBOCR_S tmp_value;
  3370. U32 value = (*(volatile U32 *)REG_ETH_MFBOCR);
  3371. tmp_value.all = value;
  3372. #if GH_ETH_ENABLE_DEBUG_PRINT
  3373. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFBOCR_OVMFC] --> 0x%08x\n",
  3374. REG_ETH_MFBOCR,value);
  3375. #endif
  3376. return tmp_value.bitc.ovmfc;
  3377. }
  3378. GH_INLINE void GH_ETH_set_MFBOCR_NMFF(U16 data)
  3379. {
  3380. GH_ETH_MFBOCR_S d;
  3381. d.all = *(volatile U32 *)REG_ETH_MFBOCR;
  3382. d.bitc.nmff = data;
  3383. *(volatile U32 *)REG_ETH_MFBOCR = d.all;
  3384. #if GH_ETH_ENABLE_DEBUG_PRINT
  3385. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFBOCR_NMFF] <-- 0x%08x\n",
  3386. REG_ETH_MFBOCR,d.all,d.all);
  3387. #endif
  3388. }
  3389. GH_INLINE U16 GH_ETH_get_MFBOCR_NMFF(void)
  3390. {
  3391. GH_ETH_MFBOCR_S tmp_value;
  3392. U32 value = (*(volatile U32 *)REG_ETH_MFBOCR);
  3393. tmp_value.all = value;
  3394. #if GH_ETH_ENABLE_DEBUG_PRINT
  3395. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFBOCR_NMFF] --> 0x%08x\n",
  3396. REG_ETH_MFBOCR,value);
  3397. #endif
  3398. return tmp_value.bitc.nmff;
  3399. }
  3400. GH_INLINE void GH_ETH_set_MFBOCR_ONMFF(U8 data)
  3401. {
  3402. GH_ETH_MFBOCR_S d;
  3403. d.all = *(volatile U32 *)REG_ETH_MFBOCR;
  3404. d.bitc.onmff = data;
  3405. *(volatile U32 *)REG_ETH_MFBOCR = d.all;
  3406. #if GH_ETH_ENABLE_DEBUG_PRINT
  3407. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_MFBOCR_ONMFF] <-- 0x%08x\n",
  3408. REG_ETH_MFBOCR,d.all,d.all);
  3409. #endif
  3410. }
  3411. GH_INLINE U8 GH_ETH_get_MFBOCR_ONMFF(void)
  3412. {
  3413. GH_ETH_MFBOCR_S tmp_value;
  3414. U32 value = (*(volatile U32 *)REG_ETH_MFBOCR);
  3415. tmp_value.all = value;
  3416. #if GH_ETH_ENABLE_DEBUG_PRINT
  3417. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_MFBOCR_ONMFF] --> 0x%08x\n",
  3418. REG_ETH_MFBOCR,value);
  3419. #endif
  3420. return tmp_value.bitc.onmff;
  3421. }
  3422. #endif /* GH_INLINE_LEVEL == 0 */
  3423. /*----------------------------------------------------------------------------*/
  3424. /* register ETH_IER (read/write) */
  3425. /*----------------------------------------------------------------------------*/
  3426. #if GH_INLINE_LEVEL == 0
  3427. /*! \brief Writes the register 'ETH_IER'. */
  3428. void GH_ETH_set_IER(U32 data);
  3429. /*! \brief Reads the register 'ETH_IER'. */
  3430. U32 GH_ETH_get_IER(void);
  3431. /*! \brief Writes the bit group 'TI' of register 'ETH_IER'. */
  3432. void GH_ETH_set_IER_TI(U8 data);
  3433. /*! \brief Reads the bit group 'TI' of register 'ETH_IER'. */
  3434. U8 GH_ETH_get_IER_TI(void);
  3435. /*! \brief Writes the bit group 'TS' of register 'ETH_IER'. */
  3436. void GH_ETH_set_IER_TS(U8 data);
  3437. /*! \brief Reads the bit group 'TS' of register 'ETH_IER'. */
  3438. U8 GH_ETH_get_IER_TS(void);
  3439. /*! \brief Writes the bit group 'TU' of register 'ETH_IER'. */
  3440. void GH_ETH_set_IER_TU(U8 data);
  3441. /*! \brief Reads the bit group 'TU' of register 'ETH_IER'. */
  3442. U8 GH_ETH_get_IER_TU(void);
  3443. /*! \brief Writes the bit group 'TJ' of register 'ETH_IER'. */
  3444. void GH_ETH_set_IER_TJ(U8 data);
  3445. /*! \brief Reads the bit group 'TJ' of register 'ETH_IER'. */
  3446. U8 GH_ETH_get_IER_TJ(void);
  3447. /*! \brief Writes the bit group 'OV' of register 'ETH_IER'. */
  3448. void GH_ETH_set_IER_OV(U8 data);
  3449. /*! \brief Reads the bit group 'OV' of register 'ETH_IER'. */
  3450. U8 GH_ETH_get_IER_OV(void);
  3451. /*! \brief Writes the bit group 'UN' of register 'ETH_IER'. */
  3452. void GH_ETH_set_IER_UN(U8 data);
  3453. /*! \brief Reads the bit group 'UN' of register 'ETH_IER'. */
  3454. U8 GH_ETH_get_IER_UN(void);
  3455. /*! \brief Writes the bit group 'RI' of register 'ETH_IER'. */
  3456. void GH_ETH_set_IER_RI(U8 data);
  3457. /*! \brief Reads the bit group 'RI' of register 'ETH_IER'. */
  3458. U8 GH_ETH_get_IER_RI(void);
  3459. /*! \brief Writes the bit group 'RU' of register 'ETH_IER'. */
  3460. void GH_ETH_set_IER_RU(U8 data);
  3461. /*! \brief Reads the bit group 'RU' of register 'ETH_IER'. */
  3462. U8 GH_ETH_get_IER_RU(void);
  3463. /*! \brief Writes the bit group 'RS' of register 'ETH_IER'. */
  3464. void GH_ETH_set_IER_RS(U8 data);
  3465. /*! \brief Reads the bit group 'RS' of register 'ETH_IER'. */
  3466. U8 GH_ETH_get_IER_RS(void);
  3467. /*! \brief Writes the bit group 'RW' of register 'ETH_IER'. */
  3468. void GH_ETH_set_IER_RW(U8 data);
  3469. /*! \brief Reads the bit group 'RW' of register 'ETH_IER'. */
  3470. U8 GH_ETH_get_IER_RW(void);
  3471. /*! \brief Writes the bit group 'ETE' of register 'ETH_IER'. */
  3472. void GH_ETH_set_IER_ETE(U8 data);
  3473. /*! \brief Reads the bit group 'ETE' of register 'ETH_IER'. */
  3474. U8 GH_ETH_get_IER_ETE(void);
  3475. /*! \brief Writes the bit group 'FBE' of register 'ETH_IER'. */
  3476. void GH_ETH_set_IER_FBE(U8 data);
  3477. /*! \brief Reads the bit group 'FBE' of register 'ETH_IER'. */
  3478. U8 GH_ETH_get_IER_FBE(void);
  3479. /*! \brief Writes the bit group 'ERE' of register 'ETH_IER'. */
  3480. void GH_ETH_set_IER_ERE(U8 data);
  3481. /*! \brief Reads the bit group 'ERE' of register 'ETH_IER'. */
  3482. U8 GH_ETH_get_IER_ERE(void);
  3483. /*! \brief Writes the bit group 'AI' of register 'ETH_IER'. */
  3484. void GH_ETH_set_IER_AI(U8 data);
  3485. /*! \brief Reads the bit group 'AI' of register 'ETH_IER'. */
  3486. U8 GH_ETH_get_IER_AI(void);
  3487. /*! \brief Writes the bit group 'NI' of register 'ETH_IER'. */
  3488. void GH_ETH_set_IER_NI(U8 data);
  3489. /*! \brief Reads the bit group 'NI' of register 'ETH_IER'. */
  3490. U8 GH_ETH_get_IER_NI(void);
  3491. #else /* GH_INLINE_LEVEL == 0 */
  3492. GH_INLINE void GH_ETH_set_IER(U32 data)
  3493. {
  3494. *(volatile U32 *)REG_ETH_IER = data;
  3495. #if GH_ETH_ENABLE_DEBUG_PRINT
  3496. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER] <-- 0x%08x\n",
  3497. REG_ETH_IER,data,data);
  3498. #endif
  3499. }
  3500. GH_INLINE U32 GH_ETH_get_IER(void)
  3501. {
  3502. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3503. #if GH_ETH_ENABLE_DEBUG_PRINT
  3504. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER] --> 0x%08x\n",
  3505. REG_ETH_IER,value);
  3506. #endif
  3507. return value;
  3508. }
  3509. GH_INLINE void GH_ETH_set_IER_TI(U8 data)
  3510. {
  3511. GH_ETH_IER_S d;
  3512. d.all = *(volatile U32 *)REG_ETH_IER;
  3513. d.bitc.ti = data;
  3514. *(volatile U32 *)REG_ETH_IER = d.all;
  3515. #if GH_ETH_ENABLE_DEBUG_PRINT
  3516. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_TI] <-- 0x%08x\n",
  3517. REG_ETH_IER,d.all,d.all);
  3518. #endif
  3519. }
  3520. GH_INLINE U8 GH_ETH_get_IER_TI(void)
  3521. {
  3522. GH_ETH_IER_S tmp_value;
  3523. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3524. tmp_value.all = value;
  3525. #if GH_ETH_ENABLE_DEBUG_PRINT
  3526. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_TI] --> 0x%08x\n",
  3527. REG_ETH_IER,value);
  3528. #endif
  3529. return tmp_value.bitc.ti;
  3530. }
  3531. GH_INLINE void GH_ETH_set_IER_TS(U8 data)
  3532. {
  3533. GH_ETH_IER_S d;
  3534. d.all = *(volatile U32 *)REG_ETH_IER;
  3535. d.bitc.ts = data;
  3536. *(volatile U32 *)REG_ETH_IER = d.all;
  3537. #if GH_ETH_ENABLE_DEBUG_PRINT
  3538. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_TS] <-- 0x%08x\n",
  3539. REG_ETH_IER,d.all,d.all);
  3540. #endif
  3541. }
  3542. GH_INLINE U8 GH_ETH_get_IER_TS(void)
  3543. {
  3544. GH_ETH_IER_S tmp_value;
  3545. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3546. tmp_value.all = value;
  3547. #if GH_ETH_ENABLE_DEBUG_PRINT
  3548. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_TS] --> 0x%08x\n",
  3549. REG_ETH_IER,value);
  3550. #endif
  3551. return tmp_value.bitc.ts;
  3552. }
  3553. GH_INLINE void GH_ETH_set_IER_TU(U8 data)
  3554. {
  3555. GH_ETH_IER_S d;
  3556. d.all = *(volatile U32 *)REG_ETH_IER;
  3557. d.bitc.tu = data;
  3558. *(volatile U32 *)REG_ETH_IER = d.all;
  3559. #if GH_ETH_ENABLE_DEBUG_PRINT
  3560. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_TU] <-- 0x%08x\n",
  3561. REG_ETH_IER,d.all,d.all);
  3562. #endif
  3563. }
  3564. GH_INLINE U8 GH_ETH_get_IER_TU(void)
  3565. {
  3566. GH_ETH_IER_S tmp_value;
  3567. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3568. tmp_value.all = value;
  3569. #if GH_ETH_ENABLE_DEBUG_PRINT
  3570. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_TU] --> 0x%08x\n",
  3571. REG_ETH_IER,value);
  3572. #endif
  3573. return tmp_value.bitc.tu;
  3574. }
  3575. GH_INLINE void GH_ETH_set_IER_TJ(U8 data)
  3576. {
  3577. GH_ETH_IER_S d;
  3578. d.all = *(volatile U32 *)REG_ETH_IER;
  3579. d.bitc.tj = data;
  3580. *(volatile U32 *)REG_ETH_IER = d.all;
  3581. #if GH_ETH_ENABLE_DEBUG_PRINT
  3582. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_TJ] <-- 0x%08x\n",
  3583. REG_ETH_IER,d.all,d.all);
  3584. #endif
  3585. }
  3586. GH_INLINE U8 GH_ETH_get_IER_TJ(void)
  3587. {
  3588. GH_ETH_IER_S tmp_value;
  3589. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3590. tmp_value.all = value;
  3591. #if GH_ETH_ENABLE_DEBUG_PRINT
  3592. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_TJ] --> 0x%08x\n",
  3593. REG_ETH_IER,value);
  3594. #endif
  3595. return tmp_value.bitc.tj;
  3596. }
  3597. GH_INLINE void GH_ETH_set_IER_OV(U8 data)
  3598. {
  3599. GH_ETH_IER_S d;
  3600. d.all = *(volatile U32 *)REG_ETH_IER;
  3601. d.bitc.ov = data;
  3602. *(volatile U32 *)REG_ETH_IER = d.all;
  3603. #if GH_ETH_ENABLE_DEBUG_PRINT
  3604. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_OV] <-- 0x%08x\n",
  3605. REG_ETH_IER,d.all,d.all);
  3606. #endif
  3607. }
  3608. GH_INLINE U8 GH_ETH_get_IER_OV(void)
  3609. {
  3610. GH_ETH_IER_S tmp_value;
  3611. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3612. tmp_value.all = value;
  3613. #if GH_ETH_ENABLE_DEBUG_PRINT
  3614. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_OV] --> 0x%08x\n",
  3615. REG_ETH_IER,value);
  3616. #endif
  3617. return tmp_value.bitc.ov;
  3618. }
  3619. GH_INLINE void GH_ETH_set_IER_UN(U8 data)
  3620. {
  3621. GH_ETH_IER_S d;
  3622. d.all = *(volatile U32 *)REG_ETH_IER;
  3623. d.bitc.un = data;
  3624. *(volatile U32 *)REG_ETH_IER = d.all;
  3625. #if GH_ETH_ENABLE_DEBUG_PRINT
  3626. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_UN] <-- 0x%08x\n",
  3627. REG_ETH_IER,d.all,d.all);
  3628. #endif
  3629. }
  3630. GH_INLINE U8 GH_ETH_get_IER_UN(void)
  3631. {
  3632. GH_ETH_IER_S tmp_value;
  3633. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3634. tmp_value.all = value;
  3635. #if GH_ETH_ENABLE_DEBUG_PRINT
  3636. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_UN] --> 0x%08x\n",
  3637. REG_ETH_IER,value);
  3638. #endif
  3639. return tmp_value.bitc.un;
  3640. }
  3641. GH_INLINE void GH_ETH_set_IER_RI(U8 data)
  3642. {
  3643. GH_ETH_IER_S d;
  3644. d.all = *(volatile U32 *)REG_ETH_IER;
  3645. d.bitc.ri = data;
  3646. *(volatile U32 *)REG_ETH_IER = d.all;
  3647. #if GH_ETH_ENABLE_DEBUG_PRINT
  3648. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_RI] <-- 0x%08x\n",
  3649. REG_ETH_IER,d.all,d.all);
  3650. #endif
  3651. }
  3652. GH_INLINE U8 GH_ETH_get_IER_RI(void)
  3653. {
  3654. GH_ETH_IER_S tmp_value;
  3655. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3656. tmp_value.all = value;
  3657. #if GH_ETH_ENABLE_DEBUG_PRINT
  3658. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_RI] --> 0x%08x\n",
  3659. REG_ETH_IER,value);
  3660. #endif
  3661. return tmp_value.bitc.ri;
  3662. }
  3663. GH_INLINE void GH_ETH_set_IER_RU(U8 data)
  3664. {
  3665. GH_ETH_IER_S d;
  3666. d.all = *(volatile U32 *)REG_ETH_IER;
  3667. d.bitc.ru = data;
  3668. *(volatile U32 *)REG_ETH_IER = d.all;
  3669. #if GH_ETH_ENABLE_DEBUG_PRINT
  3670. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_RU] <-- 0x%08x\n",
  3671. REG_ETH_IER,d.all,d.all);
  3672. #endif
  3673. }
  3674. GH_INLINE U8 GH_ETH_get_IER_RU(void)
  3675. {
  3676. GH_ETH_IER_S tmp_value;
  3677. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3678. tmp_value.all = value;
  3679. #if GH_ETH_ENABLE_DEBUG_PRINT
  3680. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_RU] --> 0x%08x\n",
  3681. REG_ETH_IER,value);
  3682. #endif
  3683. return tmp_value.bitc.ru;
  3684. }
  3685. GH_INLINE void GH_ETH_set_IER_RS(U8 data)
  3686. {
  3687. GH_ETH_IER_S d;
  3688. d.all = *(volatile U32 *)REG_ETH_IER;
  3689. d.bitc.rs = data;
  3690. *(volatile U32 *)REG_ETH_IER = d.all;
  3691. #if GH_ETH_ENABLE_DEBUG_PRINT
  3692. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_RS] <-- 0x%08x\n",
  3693. REG_ETH_IER,d.all,d.all);
  3694. #endif
  3695. }
  3696. GH_INLINE U8 GH_ETH_get_IER_RS(void)
  3697. {
  3698. GH_ETH_IER_S tmp_value;
  3699. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3700. tmp_value.all = value;
  3701. #if GH_ETH_ENABLE_DEBUG_PRINT
  3702. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_RS] --> 0x%08x\n",
  3703. REG_ETH_IER,value);
  3704. #endif
  3705. return tmp_value.bitc.rs;
  3706. }
  3707. GH_INLINE void GH_ETH_set_IER_RW(U8 data)
  3708. {
  3709. GH_ETH_IER_S d;
  3710. d.all = *(volatile U32 *)REG_ETH_IER;
  3711. d.bitc.rw = data;
  3712. *(volatile U32 *)REG_ETH_IER = d.all;
  3713. #if GH_ETH_ENABLE_DEBUG_PRINT
  3714. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_RW] <-- 0x%08x\n",
  3715. REG_ETH_IER,d.all,d.all);
  3716. #endif
  3717. }
  3718. GH_INLINE U8 GH_ETH_get_IER_RW(void)
  3719. {
  3720. GH_ETH_IER_S tmp_value;
  3721. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3722. tmp_value.all = value;
  3723. #if GH_ETH_ENABLE_DEBUG_PRINT
  3724. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_RW] --> 0x%08x\n",
  3725. REG_ETH_IER,value);
  3726. #endif
  3727. return tmp_value.bitc.rw;
  3728. }
  3729. GH_INLINE void GH_ETH_set_IER_ETE(U8 data)
  3730. {
  3731. GH_ETH_IER_S d;
  3732. d.all = *(volatile U32 *)REG_ETH_IER;
  3733. d.bitc.ete = data;
  3734. *(volatile U32 *)REG_ETH_IER = d.all;
  3735. #if GH_ETH_ENABLE_DEBUG_PRINT
  3736. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_ETE] <-- 0x%08x\n",
  3737. REG_ETH_IER,d.all,d.all);
  3738. #endif
  3739. }
  3740. GH_INLINE U8 GH_ETH_get_IER_ETE(void)
  3741. {
  3742. GH_ETH_IER_S tmp_value;
  3743. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3744. tmp_value.all = value;
  3745. #if GH_ETH_ENABLE_DEBUG_PRINT
  3746. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_ETE] --> 0x%08x\n",
  3747. REG_ETH_IER,value);
  3748. #endif
  3749. return tmp_value.bitc.ete;
  3750. }
  3751. GH_INLINE void GH_ETH_set_IER_FBE(U8 data)
  3752. {
  3753. GH_ETH_IER_S d;
  3754. d.all = *(volatile U32 *)REG_ETH_IER;
  3755. d.bitc.fbe = data;
  3756. *(volatile U32 *)REG_ETH_IER = d.all;
  3757. #if GH_ETH_ENABLE_DEBUG_PRINT
  3758. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_FBE] <-- 0x%08x\n",
  3759. REG_ETH_IER,d.all,d.all);
  3760. #endif
  3761. }
  3762. GH_INLINE U8 GH_ETH_get_IER_FBE(void)
  3763. {
  3764. GH_ETH_IER_S tmp_value;
  3765. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3766. tmp_value.all = value;
  3767. #if GH_ETH_ENABLE_DEBUG_PRINT
  3768. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_FBE] --> 0x%08x\n",
  3769. REG_ETH_IER,value);
  3770. #endif
  3771. return tmp_value.bitc.fbe;
  3772. }
  3773. GH_INLINE void GH_ETH_set_IER_ERE(U8 data)
  3774. {
  3775. GH_ETH_IER_S d;
  3776. d.all = *(volatile U32 *)REG_ETH_IER;
  3777. d.bitc.ere = data;
  3778. *(volatile U32 *)REG_ETH_IER = d.all;
  3779. #if GH_ETH_ENABLE_DEBUG_PRINT
  3780. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_ERE] <-- 0x%08x\n",
  3781. REG_ETH_IER,d.all,d.all);
  3782. #endif
  3783. }
  3784. GH_INLINE U8 GH_ETH_get_IER_ERE(void)
  3785. {
  3786. GH_ETH_IER_S tmp_value;
  3787. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3788. tmp_value.all = value;
  3789. #if GH_ETH_ENABLE_DEBUG_PRINT
  3790. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_ERE] --> 0x%08x\n",
  3791. REG_ETH_IER,value);
  3792. #endif
  3793. return tmp_value.bitc.ere;
  3794. }
  3795. GH_INLINE void GH_ETH_set_IER_AI(U8 data)
  3796. {
  3797. GH_ETH_IER_S d;
  3798. d.all = *(volatile U32 *)REG_ETH_IER;
  3799. d.bitc.ai = data;
  3800. *(volatile U32 *)REG_ETH_IER = d.all;
  3801. #if GH_ETH_ENABLE_DEBUG_PRINT
  3802. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_AI] <-- 0x%08x\n",
  3803. REG_ETH_IER,d.all,d.all);
  3804. #endif
  3805. }
  3806. GH_INLINE U8 GH_ETH_get_IER_AI(void)
  3807. {
  3808. GH_ETH_IER_S tmp_value;
  3809. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3810. tmp_value.all = value;
  3811. #if GH_ETH_ENABLE_DEBUG_PRINT
  3812. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_AI] --> 0x%08x\n",
  3813. REG_ETH_IER,value);
  3814. #endif
  3815. return tmp_value.bitc.ai;
  3816. }
  3817. GH_INLINE void GH_ETH_set_IER_NI(U8 data)
  3818. {
  3819. GH_ETH_IER_S d;
  3820. d.all = *(volatile U32 *)REG_ETH_IER;
  3821. d.bitc.ni = data;
  3822. *(volatile U32 *)REG_ETH_IER = d.all;
  3823. #if GH_ETH_ENABLE_DEBUG_PRINT
  3824. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_IER_NI] <-- 0x%08x\n",
  3825. REG_ETH_IER,d.all,d.all);
  3826. #endif
  3827. }
  3828. GH_INLINE U8 GH_ETH_get_IER_NI(void)
  3829. {
  3830. GH_ETH_IER_S tmp_value;
  3831. U32 value = (*(volatile U32 *)REG_ETH_IER);
  3832. tmp_value.all = value;
  3833. #if GH_ETH_ENABLE_DEBUG_PRINT
  3834. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_IER_NI] --> 0x%08x\n",
  3835. REG_ETH_IER,value);
  3836. #endif
  3837. return tmp_value.bitc.ni;
  3838. }
  3839. #endif /* GH_INLINE_LEVEL == 0 */
  3840. /*----------------------------------------------------------------------------*/
  3841. /* register ETH_OMR (read/write) */
  3842. /*----------------------------------------------------------------------------*/
  3843. #if GH_INLINE_LEVEL == 0
  3844. /*! \brief Writes the register 'ETH_OMR'. */
  3845. void GH_ETH_set_OMR(U32 data);
  3846. /*! \brief Reads the register 'ETH_OMR'. */
  3847. U32 GH_ETH_get_OMR(void);
  3848. /*! \brief Writes the bit group 'SR' of register 'ETH_OMR'. */
  3849. void GH_ETH_set_OMR_SR(U8 data);
  3850. /*! \brief Reads the bit group 'SR' of register 'ETH_OMR'. */
  3851. U8 GH_ETH_get_OMR_SR(void);
  3852. /*! \brief Writes the bit group 'OSF' of register 'ETH_OMR'. */
  3853. void GH_ETH_set_OMR_OSF(U8 data);
  3854. /*! \brief Reads the bit group 'OSF' of register 'ETH_OMR'. */
  3855. U8 GH_ETH_get_OMR_OSF(void);
  3856. /*! \brief Writes the bit group 'RTC' of register 'ETH_OMR'. */
  3857. void GH_ETH_set_OMR_RTC(U8 data);
  3858. /*! \brief Reads the bit group 'RTC' of register 'ETH_OMR'. */
  3859. U8 GH_ETH_get_OMR_RTC(void);
  3860. /*! \brief Writes the bit group 'FUF' of register 'ETH_OMR'. */
  3861. void GH_ETH_set_OMR_FUF(U8 data);
  3862. /*! \brief Reads the bit group 'FUF' of register 'ETH_OMR'. */
  3863. U8 GH_ETH_get_OMR_FUF(void);
  3864. /*! \brief Writes the bit group 'FEF' of register 'ETH_OMR'. */
  3865. void GH_ETH_set_OMR_FEF(U8 data);
  3866. /*! \brief Reads the bit group 'FEF' of register 'ETH_OMR'. */
  3867. U8 GH_ETH_get_OMR_FEF(void);
  3868. /*! \brief Writes the bit group 'EFC' of register 'ETH_OMR'. */
  3869. void GH_ETH_set_OMR_EFC(U8 data);
  3870. /*! \brief Reads the bit group 'EFC' of register 'ETH_OMR'. */
  3871. U8 GH_ETH_get_OMR_EFC(void);
  3872. /*! \brief Writes the bit group 'RFA' of register 'ETH_OMR'. */
  3873. void GH_ETH_set_OMR_RFA(U8 data);
  3874. /*! \brief Reads the bit group 'RFA' of register 'ETH_OMR'. */
  3875. U8 GH_ETH_get_OMR_RFA(void);
  3876. /*! \brief Writes the bit group 'RFD' of register 'ETH_OMR'. */
  3877. void GH_ETH_set_OMR_RFD(U8 data);
  3878. /*! \brief Reads the bit group 'RFD' of register 'ETH_OMR'. */
  3879. U8 GH_ETH_get_OMR_RFD(void);
  3880. /*! \brief Writes the bit group 'ST' of register 'ETH_OMR'. */
  3881. void GH_ETH_set_OMR_ST(U8 data);
  3882. /*! \brief Reads the bit group 'ST' of register 'ETH_OMR'. */
  3883. U8 GH_ETH_get_OMR_ST(void);
  3884. /*! \brief Writes the bit group 'TTC' of register 'ETH_OMR'. */
  3885. void GH_ETH_set_OMR_TTC(U8 data);
  3886. /*! \brief Reads the bit group 'TTC' of register 'ETH_OMR'. */
  3887. U8 GH_ETH_get_OMR_TTC(void);
  3888. /*! \brief Writes the bit group 'FTF' of register 'ETH_OMR'. */
  3889. void GH_ETH_set_OMR_FTF(U8 data);
  3890. /*! \brief Reads the bit group 'FTF' of register 'ETH_OMR'. */
  3891. U8 GH_ETH_get_OMR_FTF(void);
  3892. /*! \brief Writes the bit group 'SF' of register 'ETH_OMR'. */
  3893. void GH_ETH_set_OMR_SF(U8 data);
  3894. /*! \brief Reads the bit group 'SF' of register 'ETH_OMR'. */
  3895. U8 GH_ETH_get_OMR_SF(void);
  3896. #else /* GH_INLINE_LEVEL == 0 */
  3897. GH_INLINE void GH_ETH_set_OMR(U32 data)
  3898. {
  3899. *(volatile U32 *)REG_ETH_OMR = data;
  3900. #if GH_ETH_ENABLE_DEBUG_PRINT
  3901. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR] <-- 0x%08x\n",
  3902. REG_ETH_OMR,data,data);
  3903. #endif
  3904. }
  3905. GH_INLINE U32 GH_ETH_get_OMR(void)
  3906. {
  3907. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  3908. #if GH_ETH_ENABLE_DEBUG_PRINT
  3909. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR] --> 0x%08x\n",
  3910. REG_ETH_OMR,value);
  3911. #endif
  3912. return value;
  3913. }
  3914. GH_INLINE void GH_ETH_set_OMR_SR(U8 data)
  3915. {
  3916. GH_ETH_OMR_S d;
  3917. d.all = *(volatile U32 *)REG_ETH_OMR;
  3918. d.bitc.sr = data;
  3919. *(volatile U32 *)REG_ETH_OMR = d.all;
  3920. #if GH_ETH_ENABLE_DEBUG_PRINT
  3921. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_SR] <-- 0x%08x\n",
  3922. REG_ETH_OMR,d.all,d.all);
  3923. #endif
  3924. }
  3925. GH_INLINE U8 GH_ETH_get_OMR_SR(void)
  3926. {
  3927. GH_ETH_OMR_S tmp_value;
  3928. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  3929. tmp_value.all = value;
  3930. #if GH_ETH_ENABLE_DEBUG_PRINT
  3931. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_SR] --> 0x%08x\n",
  3932. REG_ETH_OMR,value);
  3933. #endif
  3934. return tmp_value.bitc.sr;
  3935. }
  3936. GH_INLINE void GH_ETH_set_OMR_OSF(U8 data)
  3937. {
  3938. GH_ETH_OMR_S d;
  3939. d.all = *(volatile U32 *)REG_ETH_OMR;
  3940. d.bitc.osf = data;
  3941. *(volatile U32 *)REG_ETH_OMR = d.all;
  3942. #if GH_ETH_ENABLE_DEBUG_PRINT
  3943. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_OSF] <-- 0x%08x\n",
  3944. REG_ETH_OMR,d.all,d.all);
  3945. #endif
  3946. }
  3947. GH_INLINE U8 GH_ETH_get_OMR_OSF(void)
  3948. {
  3949. GH_ETH_OMR_S tmp_value;
  3950. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  3951. tmp_value.all = value;
  3952. #if GH_ETH_ENABLE_DEBUG_PRINT
  3953. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_OSF] --> 0x%08x\n",
  3954. REG_ETH_OMR,value);
  3955. #endif
  3956. return tmp_value.bitc.osf;
  3957. }
  3958. GH_INLINE void GH_ETH_set_OMR_RTC(U8 data)
  3959. {
  3960. GH_ETH_OMR_S d;
  3961. d.all = *(volatile U32 *)REG_ETH_OMR;
  3962. d.bitc.rtc = data;
  3963. *(volatile U32 *)REG_ETH_OMR = d.all;
  3964. #if GH_ETH_ENABLE_DEBUG_PRINT
  3965. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_RTC] <-- 0x%08x\n",
  3966. REG_ETH_OMR,d.all,d.all);
  3967. #endif
  3968. }
  3969. GH_INLINE U8 GH_ETH_get_OMR_RTC(void)
  3970. {
  3971. GH_ETH_OMR_S tmp_value;
  3972. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  3973. tmp_value.all = value;
  3974. #if GH_ETH_ENABLE_DEBUG_PRINT
  3975. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_RTC] --> 0x%08x\n",
  3976. REG_ETH_OMR,value);
  3977. #endif
  3978. return tmp_value.bitc.rtc;
  3979. }
  3980. GH_INLINE void GH_ETH_set_OMR_FUF(U8 data)
  3981. {
  3982. GH_ETH_OMR_S d;
  3983. d.all = *(volatile U32 *)REG_ETH_OMR;
  3984. d.bitc.fuf = data;
  3985. *(volatile U32 *)REG_ETH_OMR = d.all;
  3986. #if GH_ETH_ENABLE_DEBUG_PRINT
  3987. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_FUF] <-- 0x%08x\n",
  3988. REG_ETH_OMR,d.all,d.all);
  3989. #endif
  3990. }
  3991. GH_INLINE U8 GH_ETH_get_OMR_FUF(void)
  3992. {
  3993. GH_ETH_OMR_S tmp_value;
  3994. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  3995. tmp_value.all = value;
  3996. #if GH_ETH_ENABLE_DEBUG_PRINT
  3997. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_FUF] --> 0x%08x\n",
  3998. REG_ETH_OMR,value);
  3999. #endif
  4000. return tmp_value.bitc.fuf;
  4001. }
  4002. GH_INLINE void GH_ETH_set_OMR_FEF(U8 data)
  4003. {
  4004. GH_ETH_OMR_S d;
  4005. d.all = *(volatile U32 *)REG_ETH_OMR;
  4006. d.bitc.fef = data;
  4007. *(volatile U32 *)REG_ETH_OMR = d.all;
  4008. #if GH_ETH_ENABLE_DEBUG_PRINT
  4009. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_FEF] <-- 0x%08x\n",
  4010. REG_ETH_OMR,d.all,d.all);
  4011. #endif
  4012. }
  4013. GH_INLINE U8 GH_ETH_get_OMR_FEF(void)
  4014. {
  4015. GH_ETH_OMR_S tmp_value;
  4016. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4017. tmp_value.all = value;
  4018. #if GH_ETH_ENABLE_DEBUG_PRINT
  4019. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_FEF] --> 0x%08x\n",
  4020. REG_ETH_OMR,value);
  4021. #endif
  4022. return tmp_value.bitc.fef;
  4023. }
  4024. GH_INLINE void GH_ETH_set_OMR_EFC(U8 data)
  4025. {
  4026. GH_ETH_OMR_S d;
  4027. d.all = *(volatile U32 *)REG_ETH_OMR;
  4028. d.bitc.efc = data;
  4029. *(volatile U32 *)REG_ETH_OMR = d.all;
  4030. #if GH_ETH_ENABLE_DEBUG_PRINT
  4031. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_EFC] <-- 0x%08x\n",
  4032. REG_ETH_OMR,d.all,d.all);
  4033. #endif
  4034. }
  4035. GH_INLINE U8 GH_ETH_get_OMR_EFC(void)
  4036. {
  4037. GH_ETH_OMR_S tmp_value;
  4038. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4039. tmp_value.all = value;
  4040. #if GH_ETH_ENABLE_DEBUG_PRINT
  4041. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_EFC] --> 0x%08x\n",
  4042. REG_ETH_OMR,value);
  4043. #endif
  4044. return tmp_value.bitc.efc;
  4045. }
  4046. GH_INLINE void GH_ETH_set_OMR_RFA(U8 data)
  4047. {
  4048. GH_ETH_OMR_S d;
  4049. d.all = *(volatile U32 *)REG_ETH_OMR;
  4050. d.bitc.rfa = data;
  4051. *(volatile U32 *)REG_ETH_OMR = d.all;
  4052. #if GH_ETH_ENABLE_DEBUG_PRINT
  4053. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_RFA] <-- 0x%08x\n",
  4054. REG_ETH_OMR,d.all,d.all);
  4055. #endif
  4056. }
  4057. GH_INLINE U8 GH_ETH_get_OMR_RFA(void)
  4058. {
  4059. GH_ETH_OMR_S tmp_value;
  4060. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4061. tmp_value.all = value;
  4062. #if GH_ETH_ENABLE_DEBUG_PRINT
  4063. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_RFA] --> 0x%08x\n",
  4064. REG_ETH_OMR,value);
  4065. #endif
  4066. return tmp_value.bitc.rfa;
  4067. }
  4068. GH_INLINE void GH_ETH_set_OMR_RFD(U8 data)
  4069. {
  4070. GH_ETH_OMR_S d;
  4071. d.all = *(volatile U32 *)REG_ETH_OMR;
  4072. d.bitc.rfd = data;
  4073. *(volatile U32 *)REG_ETH_OMR = d.all;
  4074. #if GH_ETH_ENABLE_DEBUG_PRINT
  4075. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_RFD] <-- 0x%08x\n",
  4076. REG_ETH_OMR,d.all,d.all);
  4077. #endif
  4078. }
  4079. GH_INLINE U8 GH_ETH_get_OMR_RFD(void)
  4080. {
  4081. GH_ETH_OMR_S tmp_value;
  4082. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4083. tmp_value.all = value;
  4084. #if GH_ETH_ENABLE_DEBUG_PRINT
  4085. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_RFD] --> 0x%08x\n",
  4086. REG_ETH_OMR,value);
  4087. #endif
  4088. return tmp_value.bitc.rfd;
  4089. }
  4090. GH_INLINE void GH_ETH_set_OMR_ST(U8 data)
  4091. {
  4092. GH_ETH_OMR_S d;
  4093. d.all = *(volatile U32 *)REG_ETH_OMR;
  4094. d.bitc.st = data;
  4095. *(volatile U32 *)REG_ETH_OMR = d.all;
  4096. #if GH_ETH_ENABLE_DEBUG_PRINT
  4097. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_ST] <-- 0x%08x\n",
  4098. REG_ETH_OMR,d.all,d.all);
  4099. #endif
  4100. }
  4101. GH_INLINE U8 GH_ETH_get_OMR_ST(void)
  4102. {
  4103. GH_ETH_OMR_S tmp_value;
  4104. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4105. tmp_value.all = value;
  4106. #if GH_ETH_ENABLE_DEBUG_PRINT
  4107. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_ST] --> 0x%08x\n",
  4108. REG_ETH_OMR,value);
  4109. #endif
  4110. return tmp_value.bitc.st;
  4111. }
  4112. GH_INLINE void GH_ETH_set_OMR_TTC(U8 data)
  4113. {
  4114. GH_ETH_OMR_S d;
  4115. d.all = *(volatile U32 *)REG_ETH_OMR;
  4116. d.bitc.ttc = data;
  4117. *(volatile U32 *)REG_ETH_OMR = d.all;
  4118. #if GH_ETH_ENABLE_DEBUG_PRINT
  4119. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_TTC] <-- 0x%08x\n",
  4120. REG_ETH_OMR,d.all,d.all);
  4121. #endif
  4122. }
  4123. GH_INLINE U8 GH_ETH_get_OMR_TTC(void)
  4124. {
  4125. GH_ETH_OMR_S tmp_value;
  4126. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4127. tmp_value.all = value;
  4128. #if GH_ETH_ENABLE_DEBUG_PRINT
  4129. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_TTC] --> 0x%08x\n",
  4130. REG_ETH_OMR,value);
  4131. #endif
  4132. return tmp_value.bitc.ttc;
  4133. }
  4134. GH_INLINE void GH_ETH_set_OMR_FTF(U8 data)
  4135. {
  4136. GH_ETH_OMR_S d;
  4137. d.all = *(volatile U32 *)REG_ETH_OMR;
  4138. d.bitc.ftf = data;
  4139. *(volatile U32 *)REG_ETH_OMR = d.all;
  4140. #if GH_ETH_ENABLE_DEBUG_PRINT
  4141. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_FTF] <-- 0x%08x\n",
  4142. REG_ETH_OMR,d.all,d.all);
  4143. #endif
  4144. }
  4145. GH_INLINE U8 GH_ETH_get_OMR_FTF(void)
  4146. {
  4147. GH_ETH_OMR_S tmp_value;
  4148. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4149. tmp_value.all = value;
  4150. #if GH_ETH_ENABLE_DEBUG_PRINT
  4151. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_FTF] --> 0x%08x\n",
  4152. REG_ETH_OMR,value);
  4153. #endif
  4154. return tmp_value.bitc.ftf;
  4155. }
  4156. GH_INLINE void GH_ETH_set_OMR_SF(U8 data)
  4157. {
  4158. GH_ETH_OMR_S d;
  4159. d.all = *(volatile U32 *)REG_ETH_OMR;
  4160. d.bitc.sf = data;
  4161. *(volatile U32 *)REG_ETH_OMR = d.all;
  4162. #if GH_ETH_ENABLE_DEBUG_PRINT
  4163. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_OMR_SF] <-- 0x%08x\n",
  4164. REG_ETH_OMR,d.all,d.all);
  4165. #endif
  4166. }
  4167. GH_INLINE U8 GH_ETH_get_OMR_SF(void)
  4168. {
  4169. GH_ETH_OMR_S tmp_value;
  4170. U32 value = (*(volatile U32 *)REG_ETH_OMR);
  4171. tmp_value.all = value;
  4172. #if GH_ETH_ENABLE_DEBUG_PRINT
  4173. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_OMR_SF] --> 0x%08x\n",
  4174. REG_ETH_OMR,value);
  4175. #endif
  4176. return tmp_value.bitc.sf;
  4177. }
  4178. #endif /* GH_INLINE_LEVEL == 0 */
  4179. /*----------------------------------------------------------------------------*/
  4180. /* register ETH_CHTBAR (read/write) */
  4181. /*----------------------------------------------------------------------------*/
  4182. #if GH_INLINE_LEVEL == 0
  4183. /*! \brief Writes the register 'ETH_CHTBAR'. */
  4184. void GH_ETH_set_CHTBAR(U32 data);
  4185. /*! \brief Reads the register 'ETH_CHTBAR'. */
  4186. U32 GH_ETH_get_CHTBAR(void);
  4187. #else /* GH_INLINE_LEVEL == 0 */
  4188. GH_INLINE void GH_ETH_set_CHTBAR(U32 data)
  4189. {
  4190. *(volatile U32 *)REG_ETH_CHTBAR = data;
  4191. #if GH_ETH_ENABLE_DEBUG_PRINT
  4192. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_CHTBAR] <-- 0x%08x\n",
  4193. REG_ETH_CHTBAR,data,data);
  4194. #endif
  4195. }
  4196. GH_INLINE U32 GH_ETH_get_CHTBAR(void)
  4197. {
  4198. U32 value = (*(volatile U32 *)REG_ETH_CHTBAR);
  4199. #if GH_ETH_ENABLE_DEBUG_PRINT
  4200. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_CHTBAR] --> 0x%08x\n",
  4201. REG_ETH_CHTBAR,value);
  4202. #endif
  4203. return value;
  4204. }
  4205. #endif /* GH_INLINE_LEVEL == 0 */
  4206. /*----------------------------------------------------------------------------*/
  4207. /* register ETH_CHRBAR (read/write) */
  4208. /*----------------------------------------------------------------------------*/
  4209. #if GH_INLINE_LEVEL == 0
  4210. /*! \brief Writes the register 'ETH_CHRBAR'. */
  4211. void GH_ETH_set_CHRBAR(U32 data);
  4212. /*! \brief Reads the register 'ETH_CHRBAR'. */
  4213. U32 GH_ETH_get_CHRBAR(void);
  4214. #else /* GH_INLINE_LEVEL == 0 */
  4215. GH_INLINE void GH_ETH_set_CHRBAR(U32 data)
  4216. {
  4217. *(volatile U32 *)REG_ETH_CHRBAR = data;
  4218. #if GH_ETH_ENABLE_DEBUG_PRINT
  4219. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_CHRBAR] <-- 0x%08x\n",
  4220. REG_ETH_CHRBAR,data,data);
  4221. #endif
  4222. }
  4223. GH_INLINE U32 GH_ETH_get_CHRBAR(void)
  4224. {
  4225. U32 value = (*(volatile U32 *)REG_ETH_CHRBAR);
  4226. #if GH_ETH_ENABLE_DEBUG_PRINT
  4227. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_CHRBAR] --> 0x%08x\n",
  4228. REG_ETH_CHRBAR,value);
  4229. #endif
  4230. return value;
  4231. }
  4232. #endif /* GH_INLINE_LEVEL == 0 */
  4233. /*----------------------------------------------------------------------------*/
  4234. /* register ETH_CHTDR (read/write) */
  4235. /*----------------------------------------------------------------------------*/
  4236. #if GH_INLINE_LEVEL == 0
  4237. /*! \brief Writes the register 'ETH_CHTDR'. */
  4238. void GH_ETH_set_CHTDR(U32 data);
  4239. /*! \brief Reads the register 'ETH_CHTDR'. */
  4240. U32 GH_ETH_get_CHTDR(void);
  4241. #else /* GH_INLINE_LEVEL == 0 */
  4242. GH_INLINE void GH_ETH_set_CHTDR(U32 data)
  4243. {
  4244. *(volatile U32 *)REG_ETH_CHTDR = data;
  4245. #if GH_ETH_ENABLE_DEBUG_PRINT
  4246. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_CHTDR] <-- 0x%08x\n",
  4247. REG_ETH_CHTDR,data,data);
  4248. #endif
  4249. }
  4250. GH_INLINE U32 GH_ETH_get_CHTDR(void)
  4251. {
  4252. U32 value = (*(volatile U32 *)REG_ETH_CHTDR);
  4253. #if GH_ETH_ENABLE_DEBUG_PRINT
  4254. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_CHTDR] --> 0x%08x\n",
  4255. REG_ETH_CHTDR,value);
  4256. #endif
  4257. return value;
  4258. }
  4259. #endif /* GH_INLINE_LEVEL == 0 */
  4260. /*----------------------------------------------------------------------------*/
  4261. /* register ETH_CHRDR (read/write) */
  4262. /*----------------------------------------------------------------------------*/
  4263. #if GH_INLINE_LEVEL == 0
  4264. /*! \brief Writes the register 'ETH_CHRDR'. */
  4265. void GH_ETH_set_CHRDR(U32 data);
  4266. /*! \brief Reads the register 'ETH_CHRDR'. */
  4267. U32 GH_ETH_get_CHRDR(void);
  4268. #else /* GH_INLINE_LEVEL == 0 */
  4269. GH_INLINE void GH_ETH_set_CHRDR(U32 data)
  4270. {
  4271. *(volatile U32 *)REG_ETH_CHRDR = data;
  4272. #if GH_ETH_ENABLE_DEBUG_PRINT
  4273. GH_ETH_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_ETH_set_CHRDR] <-- 0x%08x\n",
  4274. REG_ETH_CHRDR,data,data);
  4275. #endif
  4276. }
  4277. GH_INLINE U32 GH_ETH_get_CHRDR(void)
  4278. {
  4279. U32 value = (*(volatile U32 *)REG_ETH_CHRDR);
  4280. #if GH_ETH_ENABLE_DEBUG_PRINT
  4281. GH_ETH_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_ETH_get_CHRDR] --> 0x%08x\n",
  4282. REG_ETH_CHRDR,value);
  4283. #endif
  4284. return value;
  4285. }
  4286. #endif /* GH_INLINE_LEVEL == 0 */
  4287. /*----------------------------------------------------------------------------*/
  4288. /* init function */
  4289. /*----------------------------------------------------------------------------*/
  4290. /*! \brief Initialises the registers and mirror variables. */
  4291. void GH_ETH_init(void);
  4292. #ifdef __cplusplus
  4293. }
  4294. #endif
  4295. #endif /* _GH_ETH_H */
  4296. /*----------------------------------------------------------------------------*/
  4297. /* end of file */
  4298. /*----------------------------------------------------------------------------*/