gh_vo_i80.h 91 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261
  1. /*!
  2. *******************************************************************************
  3. **
  4. ** \file gh_vo_i80.h
  5. **
  6. ** \brief VO I80 access function..
  7. **
  8. ** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
  9. **
  10. ** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
  11. ** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
  12. ** OMMISSIONS.
  13. **
  14. ** \note Do not modify this file as it is generated automatically.
  15. **
  16. ******************************************************************************/
  17. #ifndef _GH_VO_I80_H
  18. #define _GH_VO_I80_H
  19. #ifdef __LINUX__
  20. #include "reg4linux.h"
  21. #else
  22. #define FIO_ADDRESS(block,address) (address)
  23. #define FIO_MOFFSET(block,moffset) (moffset)
  24. #endif
  25. #ifndef __LINUX__
  26. #include "gtypes.h" /* global type definitions */
  27. #include "gh_lib_cfg.h" /* configuration */
  28. #endif
  29. #define GH_VO_I80_ENABLE_DEBUG_PRINT 0
  30. #ifdef __LINUX__
  31. #define GH_VO_I80_DEBUG_PRINT_FUNCTION printk
  32. #else
  33. #define GH_VO_I80_DEBUG_PRINT_FUNCTION printf
  34. #endif
  35. #ifndef __LINUX__
  36. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  37. #include <stdio.h>
  38. #endif
  39. #endif
  40. /* check configuration */
  41. #ifndef GH_INLINE_LEVEL
  42. #error "GH_INLINE_LEVEL is not defined!"
  43. #endif
  44. #if GH_INLINE_LEVEL > 2
  45. #error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
  46. #endif
  47. #ifndef GH_INLINE
  48. #error "GH_INLINE is not defined!"
  49. #endif
  50. /* disable inlining for debugging */
  51. #ifdef DEBUG
  52. #undef GH_INLINE_LEVEL
  53. #define GH_INLINE_LEVEL 0
  54. #endif
  55. /*----------------------------------------------------------------------------*/
  56. /* registers */
  57. /*----------------------------------------------------------------------------*/
  58. #define REG_VO_I80_DATA_FORMAT FIO_ADDRESS(VO_I80,0x90004C00) /* read/write */
  59. #define REG_VO_I80_PIC_RESOLUTION FIO_ADDRESS(VO_I80,0x90004C04) /* read/write */
  60. #define REG_VO_I80_PIXEL_RDWRCMD FIO_ADDRESS(VO_I80,0x90004C08) /* read/write */
  61. #define REG_VO_I80_CMD_FORMAT FIO_ADDRESS(VO_I80,0x90004C0C) /* read/write */
  62. #define REG_VO_I80_LCD_RST_PARA1 FIO_ADDRESS(VO_I80,0x90004C10) /* read/write */
  63. #define REG_VO_I80_LCD_RST_PARA2 FIO_ADDRESS(VO_I80,0x90004C14) /* read/write */
  64. #define REG_VO_I80_DELAY_PARA FIO_ADDRESS(VO_I80,0x90004C18) /* read/write */
  65. #define REG_VO_I80_TWR_TIMING FIO_ADDRESS(VO_I80,0x90004C1C) /* read/write */
  66. #define REG_VO_I80_TRD_TIMING FIO_ADDRESS(VO_I80,0x90004C20) /* read/write */
  67. #define REG_VO_I80_TCS_TIMING FIO_ADDRESS(VO_I80,0x90004C24) /* read/write */
  68. #define REG_VO_I80_POLAR_CTRL FIO_ADDRESS(VO_I80,0x90004C28) /* read/write */
  69. #define REG_VO_I80_CTRL FIO_ADDRESS(VO_I80,0x90004C2C) /* read/write */
  70. #define REG_VO_I80_FRAME_COUNTER FIO_ADDRESS(VO_I80,0x90004C30) /* read */
  71. #define REG_VO_I80_I80_STATE FIO_ADDRESS(VO_I80,0x90004C34) /* read */
  72. #define REG_VO_I80_CMD_SRAM_STATE FIO_ADDRESS(VO_I80,0x90004C38) /* read/write */
  73. #define REG_VO_I80_TCSREF_WT_TIMING FIO_ADDRESS(VO_I80,0x90004C3C) /* read/write */
  74. #define REG_VO_I80_TCSREF_RD_TIMING FIO_ADDRESS(VO_I80,0x90004C40) /* read/write */
  75. #define REG_VO_I80_TODH_TIMING FIO_ADDRESS(VO_I80,0x90004C44) /* read/write */
  76. #define REG_VO_I80_LCD_STATE FIO_ADDRESS(VO_I80,0x90004C48) /* read/write */
  77. #define REG_VO_I80_LCD_STATE0 FIO_ADDRESS(VO_I80,0x90004C4C) /* read */
  78. #define REG_VO_I80_LCD_STATE1 FIO_ADDRESS(VO_I80,0x90004C50) /* read */
  79. #define REG_VO_I80_LCD_STATE2 FIO_ADDRESS(VO_I80,0x90004C54) /* read */
  80. #define REG_VO_I80_LCD_STATE3 FIO_ADDRESS(VO_I80,0x90004C58) /* read */
  81. #define REG_VO_I80_LCD_STATE4 FIO_ADDRESS(VO_I80,0x90004C5C) /* read */
  82. #define REG_VO_I80_SRAM_CMDPARA FIO_ADDRESS(VO_I80,0x90004C80) /* read/write */
  83. /*----------------------------------------------------------------------------*/
  84. /* bit group structures */
  85. /*----------------------------------------------------------------------------*/
  86. typedef union { /* VO_I80_Data_Format */
  87. U32 all;
  88. struct {
  89. U32 data_width : 3;
  90. U32 : 13;
  91. U32 color_format : 2;
  92. U32 data_transfer_format : 1;
  93. U32 : 13;
  94. } bitc;
  95. } GH_VO_I80_DATA_FORMAT_S;
  96. typedef union { /* VO_I80_Pic_Resolution */
  97. U32 all;
  98. struct {
  99. U32 width : 10;
  100. U32 : 6;
  101. U32 height : 10;
  102. U32 : 6;
  103. } bitc;
  104. } GH_VO_I80_PIC_RESOLUTION_S;
  105. typedef union { /* VO_I80_Pixel_RdWrcmd */
  106. U32 all;
  107. struct {
  108. U32 pixel_wrcmd : 16;
  109. U32 pixel_rdcmd : 16;
  110. } bitc;
  111. } GH_VO_I80_PIXEL_RDWRCMD_S;
  112. typedef union { /* VO_I80_Cmd_Format */
  113. U32 all;
  114. struct {
  115. U32 cmd_width : 1;
  116. U32 cmd_transfer_format : 1;
  117. U32 : 30;
  118. } bitc;
  119. } GH_VO_I80_CMD_FORMAT_S;
  120. typedef union { /* VO_I80_Lcd_Rst_Para1 */
  121. U32 all;
  122. struct {
  123. U32 lcdrst_first_hlevel : 11;
  124. U32 : 5;
  125. U32 lcdrst_en : 1;
  126. U32 : 15;
  127. } bitc;
  128. } GH_VO_I80_LCD_RST_PARA1_S;
  129. typedef union { /* VO_I80_Lcd_Rst_Para2 */
  130. U32 all;
  131. struct {
  132. U32 lcdrst_level : 11;
  133. U32 : 5;
  134. U32 lcdrst_hsetup : 11;
  135. U32 : 5;
  136. } bitc;
  137. } GH_VO_I80_LCD_RST_PARA2_S;
  138. typedef union { /* VO_I80_Delay_Para */
  139. U32 all;
  140. struct {
  141. U32 delay_cmd : 16;
  142. U32 delay_time : 11;
  143. U32 delay_cmd_en : 1;
  144. U32 : 4;
  145. } bitc;
  146. } GH_VO_I80_DELAY_PARA_S;
  147. typedef union { /* VO_I80_Twr_Timing */
  148. U32 all;
  149. struct {
  150. U32 twrl : 9;
  151. U32 : 7;
  152. U32 twrh : 9;
  153. U32 : 7;
  154. } bitc;
  155. } GH_VO_I80_TWR_TIMING_S;
  156. typedef union { /* VO_I80_Trd_Timing */
  157. U32 all;
  158. struct {
  159. U32 trdl : 9;
  160. U32 : 7;
  161. U32 trdh : 9;
  162. U32 : 7;
  163. } bitc;
  164. } GH_VO_I80_TRD_TIMING_S;
  165. typedef union { /* VO_I80_Tcs_Timing */
  166. U32 all;
  167. struct {
  168. U32 tas : 6;
  169. U32 cs_ref : 1;
  170. U32 : 25;
  171. } bitc;
  172. } GH_VO_I80_TCS_TIMING_S;
  173. typedef union { /* VO_I80_Polar_Ctrl */
  174. U32 all;
  175. struct {
  176. U32 wr_polar : 1;
  177. U32 rd_polar : 1;
  178. U32 lcdrst_polar : 1;
  179. U32 vsync_polar : 1;
  180. U32 cs_polar : 1;
  181. U32 dc_polar : 1;
  182. U32 : 26;
  183. } bitc;
  184. } GH_VO_I80_POLAR_CTRL_S;
  185. typedef union { /* VO_I80_Ctrl */
  186. U32 all;
  187. struct {
  188. U32 cfg_end : 1;
  189. U32 : 1;
  190. U32 module_en : 1;
  191. U32 : 29;
  192. } bitc;
  193. } GH_VO_I80_CTRL_S;
  194. typedef union { /* VO_I80_Frame_Counter */
  195. U32 all;
  196. struct {
  197. U32 frame_cnt_out : 16;
  198. U32 frame_cnt_in : 16;
  199. } bitc;
  200. } GH_VO_I80_FRAME_COUNTER_S;
  201. typedef union { /* VO_I80_I80_State */
  202. U32 all;
  203. struct {
  204. U32 cmd_err : 1;
  205. U32 sram_overflow : 1;
  206. U32 frame_head_err : 1;
  207. U32 : 29;
  208. } bitc;
  209. } GH_VO_I80_I80_STATE_S;
  210. typedef union { /* VO_I80_Cmd_Sram_State */
  211. U32 all;
  212. struct {
  213. U32 sram_state : 1;
  214. U32 : 7;
  215. U32 rd_para_num : 4;
  216. U32 : 4;
  217. U32 cmd_para_num : 8;
  218. U32 : 8;
  219. } bitc;
  220. } GH_VO_I80_CMD_SRAM_STATE_S;
  221. typedef union { /* VO_I80_Tcsref_Wt_Timing */
  222. U32 all;
  223. struct {
  224. U32 pwcsh_wt : 9;
  225. U32 : 7;
  226. U32 pwcsl_wt : 9;
  227. U32 : 7;
  228. } bitc;
  229. } GH_VO_I80_TCSREF_WT_TIMING_S;
  230. typedef union { /* VO_I80_Tcsref_Rd_Timing */
  231. U32 all;
  232. struct {
  233. U32 pwcsh_rd : 9;
  234. U32 : 7;
  235. U32 pwcsl_rd : 9;
  236. U32 : 7;
  237. } bitc;
  238. } GH_VO_I80_TCSREF_RD_TIMING_S;
  239. typedef union { /* VO_I80_Todh_Timing */
  240. U32 all;
  241. struct {
  242. U32 todh : 9;
  243. U32 : 23;
  244. } bitc;
  245. } GH_VO_I80_TODH_TIMING_S;
  246. typedef union { /* VO_I80_Lcd_State */
  247. U32 all;
  248. struct {
  249. U32 rdcmd_para_en : 1;
  250. U32 : 31;
  251. } bitc;
  252. } GH_VO_I80_LCD_STATE_S;
  253. typedef union { /* VO_I80_Lcd_State0 */
  254. U32 all;
  255. struct {
  256. U32 lcd_para1 : 16;
  257. U32 lcd_para0 : 16;
  258. } bitc;
  259. } GH_VO_I80_LCD_STATE0_S;
  260. typedef union { /* VO_I80_Lcd_State1 */
  261. U32 all;
  262. struct {
  263. U32 lcd_para3 : 16;
  264. U32 lcd_para2 : 16;
  265. } bitc;
  266. } GH_VO_I80_LCD_STATE1_S;
  267. typedef union { /* VO_I80_Lcd_State2 */
  268. U32 all;
  269. struct {
  270. U32 lcd_para5 : 16;
  271. U32 lcd_para4 : 16;
  272. } bitc;
  273. } GH_VO_I80_LCD_STATE2_S;
  274. typedef union { /* VO_I80_Lcd_State3 */
  275. U32 all;
  276. struct {
  277. U32 lcd_para7 : 16;
  278. U32 lcd_para6 : 16;
  279. } bitc;
  280. } GH_VO_I80_LCD_STATE3_S;
  281. typedef union { /* VO_I80_Lcd_State4 */
  282. U32 all;
  283. struct {
  284. U32 lcd_para9 : 16;
  285. U32 lcd_para8 : 16;
  286. } bitc;
  287. } GH_VO_I80_LCD_STATE4_S;
  288. /*----------------------------------------------------------------------------*/
  289. /* mirror variables */
  290. /*----------------------------------------------------------------------------*/
  291. #ifdef __cplusplus
  292. extern "C" {
  293. #endif
  294. /*----------------------------------------------------------------------------*/
  295. /* register VO_I80_Data_Format (read/write) */
  296. /*----------------------------------------------------------------------------*/
  297. #if GH_INLINE_LEVEL == 0
  298. /*! \brief Writes the register 'VO_I80_Data_Format'. */
  299. void GH_VO_I80_set_Data_Format(U32 data);
  300. /*! \brief Reads the register 'VO_I80_Data_Format'. */
  301. U32 GH_VO_I80_get_Data_Format(void);
  302. /*! \brief Writes the bit group 'data_width' of register 'VO_I80_Data_Format'. */
  303. void GH_VO_I80_set_Data_Format_data_width(U8 data);
  304. /*! \brief Reads the bit group 'data_width' of register 'VO_I80_Data_Format'. */
  305. U8 GH_VO_I80_get_Data_Format_data_width(void);
  306. /*! \brief Writes the bit group 'color_format' of register 'VO_I80_Data_Format'. */
  307. void GH_VO_I80_set_Data_Format_color_format(U8 data);
  308. /*! \brief Reads the bit group 'color_format' of register 'VO_I80_Data_Format'. */
  309. U8 GH_VO_I80_get_Data_Format_color_format(void);
  310. /*! \brief Writes the bit group 'data_transfer_format' of register 'VO_I80_Data_Format'. */
  311. void GH_VO_I80_set_Data_Format_data_transfer_format(U8 data);
  312. /*! \brief Reads the bit group 'data_transfer_format' of register 'VO_I80_Data_Format'. */
  313. U8 GH_VO_I80_get_Data_Format_data_transfer_format(void);
  314. #else /* GH_INLINE_LEVEL == 0 */
  315. GH_INLINE void GH_VO_I80_set_Data_Format(U32 data)
  316. {
  317. *(volatile U32 *)REG_VO_I80_DATA_FORMAT = data;
  318. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  319. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Data_Format] <-- 0x%08x\n",
  320. REG_VO_I80_DATA_FORMAT,data,data);
  321. #endif
  322. }
  323. GH_INLINE U32 GH_VO_I80_get_Data_Format(void)
  324. {
  325. U32 value = (*(volatile U32 *)REG_VO_I80_DATA_FORMAT);
  326. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  327. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Data_Format] --> 0x%08x\n",
  328. REG_VO_I80_DATA_FORMAT,value);
  329. #endif
  330. return value;
  331. }
  332. GH_INLINE void GH_VO_I80_set_Data_Format_data_width(U8 data)
  333. {
  334. GH_VO_I80_DATA_FORMAT_S d;
  335. d.all = *(volatile U32 *)REG_VO_I80_DATA_FORMAT;
  336. d.bitc.data_width = data;
  337. *(volatile U32 *)REG_VO_I80_DATA_FORMAT = d.all;
  338. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  339. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Data_Format_data_width] <-- 0x%08x\n",
  340. REG_VO_I80_DATA_FORMAT,d.all,d.all);
  341. #endif
  342. }
  343. GH_INLINE U8 GH_VO_I80_get_Data_Format_data_width(void)
  344. {
  345. GH_VO_I80_DATA_FORMAT_S tmp_value;
  346. U32 value = (*(volatile U32 *)REG_VO_I80_DATA_FORMAT);
  347. tmp_value.all = value;
  348. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  349. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Data_Format_data_width] --> 0x%08x\n",
  350. REG_VO_I80_DATA_FORMAT,value);
  351. #endif
  352. return tmp_value.bitc.data_width;
  353. }
  354. GH_INLINE void GH_VO_I80_set_Data_Format_color_format(U8 data)
  355. {
  356. GH_VO_I80_DATA_FORMAT_S d;
  357. d.all = *(volatile U32 *)REG_VO_I80_DATA_FORMAT;
  358. d.bitc.color_format = data;
  359. *(volatile U32 *)REG_VO_I80_DATA_FORMAT = d.all;
  360. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  361. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Data_Format_color_format] <-- 0x%08x\n",
  362. REG_VO_I80_DATA_FORMAT,d.all,d.all);
  363. #endif
  364. }
  365. GH_INLINE U8 GH_VO_I80_get_Data_Format_color_format(void)
  366. {
  367. GH_VO_I80_DATA_FORMAT_S tmp_value;
  368. U32 value = (*(volatile U32 *)REG_VO_I80_DATA_FORMAT);
  369. tmp_value.all = value;
  370. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  371. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Data_Format_color_format] --> 0x%08x\n",
  372. REG_VO_I80_DATA_FORMAT,value);
  373. #endif
  374. return tmp_value.bitc.color_format;
  375. }
  376. GH_INLINE void GH_VO_I80_set_Data_Format_data_transfer_format(U8 data)
  377. {
  378. GH_VO_I80_DATA_FORMAT_S d;
  379. d.all = *(volatile U32 *)REG_VO_I80_DATA_FORMAT;
  380. d.bitc.data_transfer_format = data;
  381. *(volatile U32 *)REG_VO_I80_DATA_FORMAT = d.all;
  382. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  383. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Data_Format_data_transfer_format] <-- 0x%08x\n",
  384. REG_VO_I80_DATA_FORMAT,d.all,d.all);
  385. #endif
  386. }
  387. GH_INLINE U8 GH_VO_I80_get_Data_Format_data_transfer_format(void)
  388. {
  389. GH_VO_I80_DATA_FORMAT_S tmp_value;
  390. U32 value = (*(volatile U32 *)REG_VO_I80_DATA_FORMAT);
  391. tmp_value.all = value;
  392. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  393. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Data_Format_data_transfer_format] --> 0x%08x\n",
  394. REG_VO_I80_DATA_FORMAT,value);
  395. #endif
  396. return tmp_value.bitc.data_transfer_format;
  397. }
  398. #endif /* GH_INLINE_LEVEL == 0 */
  399. /*----------------------------------------------------------------------------*/
  400. /* register VO_I80_Pic_Resolution (read/write) */
  401. /*----------------------------------------------------------------------------*/
  402. #if GH_INLINE_LEVEL == 0
  403. /*! \brief Writes the register 'VO_I80_Pic_Resolution'. */
  404. void GH_VO_I80_set_Pic_Resolution(U32 data);
  405. /*! \brief Reads the register 'VO_I80_Pic_Resolution'. */
  406. U32 GH_VO_I80_get_Pic_Resolution(void);
  407. /*! \brief Writes the bit group 'width' of register 'VO_I80_Pic_Resolution'. */
  408. void GH_VO_I80_set_Pic_Resolution_width(U16 data);
  409. /*! \brief Reads the bit group 'width' of register 'VO_I80_Pic_Resolution'. */
  410. U16 GH_VO_I80_get_Pic_Resolution_width(void);
  411. /*! \brief Writes the bit group 'height' of register 'VO_I80_Pic_Resolution'. */
  412. void GH_VO_I80_set_Pic_Resolution_height(U16 data);
  413. /*! \brief Reads the bit group 'height' of register 'VO_I80_Pic_Resolution'. */
  414. U16 GH_VO_I80_get_Pic_Resolution_height(void);
  415. #else /* GH_INLINE_LEVEL == 0 */
  416. GH_INLINE void GH_VO_I80_set_Pic_Resolution(U32 data)
  417. {
  418. *(volatile U32 *)REG_VO_I80_PIC_RESOLUTION = data;
  419. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  420. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Pic_Resolution] <-- 0x%08x\n",
  421. REG_VO_I80_PIC_RESOLUTION,data,data);
  422. #endif
  423. }
  424. GH_INLINE U32 GH_VO_I80_get_Pic_Resolution(void)
  425. {
  426. U32 value = (*(volatile U32 *)REG_VO_I80_PIC_RESOLUTION);
  427. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  428. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Pic_Resolution] --> 0x%08x\n",
  429. REG_VO_I80_PIC_RESOLUTION,value);
  430. #endif
  431. return value;
  432. }
  433. GH_INLINE void GH_VO_I80_set_Pic_Resolution_width(U16 data)
  434. {
  435. GH_VO_I80_PIC_RESOLUTION_S d;
  436. d.all = *(volatile U32 *)REG_VO_I80_PIC_RESOLUTION;
  437. d.bitc.width = data;
  438. *(volatile U32 *)REG_VO_I80_PIC_RESOLUTION = d.all;
  439. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  440. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Pic_Resolution_width] <-- 0x%08x\n",
  441. REG_VO_I80_PIC_RESOLUTION,d.all,d.all);
  442. #endif
  443. }
  444. GH_INLINE U16 GH_VO_I80_get_Pic_Resolution_width(void)
  445. {
  446. GH_VO_I80_PIC_RESOLUTION_S tmp_value;
  447. U32 value = (*(volatile U32 *)REG_VO_I80_PIC_RESOLUTION);
  448. tmp_value.all = value;
  449. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  450. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Pic_Resolution_width] --> 0x%08x\n",
  451. REG_VO_I80_PIC_RESOLUTION,value);
  452. #endif
  453. return tmp_value.bitc.width;
  454. }
  455. GH_INLINE void GH_VO_I80_set_Pic_Resolution_height(U16 data)
  456. {
  457. GH_VO_I80_PIC_RESOLUTION_S d;
  458. d.all = *(volatile U32 *)REG_VO_I80_PIC_RESOLUTION;
  459. d.bitc.height = data;
  460. *(volatile U32 *)REG_VO_I80_PIC_RESOLUTION = d.all;
  461. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  462. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Pic_Resolution_height] <-- 0x%08x\n",
  463. REG_VO_I80_PIC_RESOLUTION,d.all,d.all);
  464. #endif
  465. }
  466. GH_INLINE U16 GH_VO_I80_get_Pic_Resolution_height(void)
  467. {
  468. GH_VO_I80_PIC_RESOLUTION_S tmp_value;
  469. U32 value = (*(volatile U32 *)REG_VO_I80_PIC_RESOLUTION);
  470. tmp_value.all = value;
  471. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  472. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Pic_Resolution_height] --> 0x%08x\n",
  473. REG_VO_I80_PIC_RESOLUTION,value);
  474. #endif
  475. return tmp_value.bitc.height;
  476. }
  477. #endif /* GH_INLINE_LEVEL == 0 */
  478. /*----------------------------------------------------------------------------*/
  479. /* register VO_I80_Pixel_RdWrcmd (read/write) */
  480. /*----------------------------------------------------------------------------*/
  481. #if GH_INLINE_LEVEL == 0
  482. /*! \brief Writes the register 'VO_I80_Pixel_RdWrcmd'. */
  483. void GH_VO_I80_set_Pixel_RdWrcmd(U32 data);
  484. /*! \brief Reads the register 'VO_I80_Pixel_RdWrcmd'. */
  485. U32 GH_VO_I80_get_Pixel_RdWrcmd(void);
  486. /*! \brief Writes the bit group 'pixel_wrcmd' of register 'VO_I80_Pixel_RdWrcmd'. */
  487. void GH_VO_I80_set_Pixel_RdWrcmd_pixel_wrcmd(U16 data);
  488. /*! \brief Reads the bit group 'pixel_wrcmd' of register 'VO_I80_Pixel_RdWrcmd'. */
  489. U16 GH_VO_I80_get_Pixel_RdWrcmd_pixel_wrcmd(void);
  490. /*! \brief Writes the bit group 'pixel_rdcmd' of register 'VO_I80_Pixel_RdWrcmd'. */
  491. void GH_VO_I80_set_Pixel_RdWrcmd_pixel_rdcmd(U16 data);
  492. /*! \brief Reads the bit group 'pixel_rdcmd' of register 'VO_I80_Pixel_RdWrcmd'. */
  493. U16 GH_VO_I80_get_Pixel_RdWrcmd_pixel_rdcmd(void);
  494. #else /* GH_INLINE_LEVEL == 0 */
  495. GH_INLINE void GH_VO_I80_set_Pixel_RdWrcmd(U32 data)
  496. {
  497. *(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD = data;
  498. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  499. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Pixel_RdWrcmd] <-- 0x%08x\n",
  500. REG_VO_I80_PIXEL_RDWRCMD,data,data);
  501. #endif
  502. }
  503. GH_INLINE U32 GH_VO_I80_get_Pixel_RdWrcmd(void)
  504. {
  505. U32 value = (*(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD);
  506. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  507. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Pixel_RdWrcmd] --> 0x%08x\n",
  508. REG_VO_I80_PIXEL_RDWRCMD,value);
  509. #endif
  510. return value;
  511. }
  512. GH_INLINE void GH_VO_I80_set_Pixel_RdWrcmd_pixel_wrcmd(U16 data)
  513. {
  514. GH_VO_I80_PIXEL_RDWRCMD_S d;
  515. d.all = *(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD;
  516. d.bitc.pixel_wrcmd = data;
  517. *(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD = d.all;
  518. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  519. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Pixel_RdWrcmd_pixel_wrcmd] <-- 0x%08x\n",
  520. REG_VO_I80_PIXEL_RDWRCMD,d.all,d.all);
  521. #endif
  522. }
  523. GH_INLINE U16 GH_VO_I80_get_Pixel_RdWrcmd_pixel_wrcmd(void)
  524. {
  525. GH_VO_I80_PIXEL_RDWRCMD_S tmp_value;
  526. U32 value = (*(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD);
  527. tmp_value.all = value;
  528. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  529. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Pixel_RdWrcmd_pixel_wrcmd] --> 0x%08x\n",
  530. REG_VO_I80_PIXEL_RDWRCMD,value);
  531. #endif
  532. return tmp_value.bitc.pixel_wrcmd;
  533. }
  534. GH_INLINE void GH_VO_I80_set_Pixel_RdWrcmd_pixel_rdcmd(U16 data)
  535. {
  536. GH_VO_I80_PIXEL_RDWRCMD_S d;
  537. d.all = *(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD;
  538. d.bitc.pixel_rdcmd = data;
  539. *(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD = d.all;
  540. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  541. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Pixel_RdWrcmd_pixel_rdcmd] <-- 0x%08x\n",
  542. REG_VO_I80_PIXEL_RDWRCMD,d.all,d.all);
  543. #endif
  544. }
  545. GH_INLINE U16 GH_VO_I80_get_Pixel_RdWrcmd_pixel_rdcmd(void)
  546. {
  547. GH_VO_I80_PIXEL_RDWRCMD_S tmp_value;
  548. U32 value = (*(volatile U32 *)REG_VO_I80_PIXEL_RDWRCMD);
  549. tmp_value.all = value;
  550. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  551. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Pixel_RdWrcmd_pixel_rdcmd] --> 0x%08x\n",
  552. REG_VO_I80_PIXEL_RDWRCMD,value);
  553. #endif
  554. return tmp_value.bitc.pixel_rdcmd;
  555. }
  556. #endif /* GH_INLINE_LEVEL == 0 */
  557. /*----------------------------------------------------------------------------*/
  558. /* register VO_I80_Cmd_Format (read/write) */
  559. /*----------------------------------------------------------------------------*/
  560. #if GH_INLINE_LEVEL == 0
  561. /*! \brief Writes the register 'VO_I80_Cmd_Format'. */
  562. void GH_VO_I80_set_Cmd_Format(U32 data);
  563. /*! \brief Reads the register 'VO_I80_Cmd_Format'. */
  564. U32 GH_VO_I80_get_Cmd_Format(void);
  565. /*! \brief Writes the bit group 'cmd_width' of register 'VO_I80_Cmd_Format'. */
  566. void GH_VO_I80_set_Cmd_Format_cmd_width(U8 data);
  567. /*! \brief Reads the bit group 'cmd_width' of register 'VO_I80_Cmd_Format'. */
  568. U8 GH_VO_I80_get_Cmd_Format_cmd_width(void);
  569. /*! \brief Writes the bit group 'cmd_transfer_format' of register 'VO_I80_Cmd_Format'. */
  570. void GH_VO_I80_set_Cmd_Format_cmd_transfer_format(U8 data);
  571. /*! \brief Reads the bit group 'cmd_transfer_format' of register 'VO_I80_Cmd_Format'. */
  572. U8 GH_VO_I80_get_Cmd_Format_cmd_transfer_format(void);
  573. #else /* GH_INLINE_LEVEL == 0 */
  574. GH_INLINE void GH_VO_I80_set_Cmd_Format(U32 data)
  575. {
  576. *(volatile U32 *)REG_VO_I80_CMD_FORMAT = data;
  577. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  578. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Cmd_Format] <-- 0x%08x\n",
  579. REG_VO_I80_CMD_FORMAT,data,data);
  580. #endif
  581. }
  582. GH_INLINE U32 GH_VO_I80_get_Cmd_Format(void)
  583. {
  584. U32 value = (*(volatile U32 *)REG_VO_I80_CMD_FORMAT);
  585. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  586. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Cmd_Format] --> 0x%08x\n",
  587. REG_VO_I80_CMD_FORMAT,value);
  588. #endif
  589. return value;
  590. }
  591. GH_INLINE void GH_VO_I80_set_Cmd_Format_cmd_width(U8 data)
  592. {
  593. GH_VO_I80_CMD_FORMAT_S d;
  594. d.all = *(volatile U32 *)REG_VO_I80_CMD_FORMAT;
  595. d.bitc.cmd_width = data;
  596. *(volatile U32 *)REG_VO_I80_CMD_FORMAT = d.all;
  597. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  598. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Cmd_Format_cmd_width] <-- 0x%08x\n",
  599. REG_VO_I80_CMD_FORMAT,d.all,d.all);
  600. #endif
  601. }
  602. GH_INLINE U8 GH_VO_I80_get_Cmd_Format_cmd_width(void)
  603. {
  604. GH_VO_I80_CMD_FORMAT_S tmp_value;
  605. U32 value = (*(volatile U32 *)REG_VO_I80_CMD_FORMAT);
  606. tmp_value.all = value;
  607. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  608. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Cmd_Format_cmd_width] --> 0x%08x\n",
  609. REG_VO_I80_CMD_FORMAT,value);
  610. #endif
  611. return tmp_value.bitc.cmd_width;
  612. }
  613. GH_INLINE void GH_VO_I80_set_Cmd_Format_cmd_transfer_format(U8 data)
  614. {
  615. GH_VO_I80_CMD_FORMAT_S d;
  616. d.all = *(volatile U32 *)REG_VO_I80_CMD_FORMAT;
  617. d.bitc.cmd_transfer_format = data;
  618. *(volatile U32 *)REG_VO_I80_CMD_FORMAT = d.all;
  619. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  620. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Cmd_Format_cmd_transfer_format] <-- 0x%08x\n",
  621. REG_VO_I80_CMD_FORMAT,d.all,d.all);
  622. #endif
  623. }
  624. GH_INLINE U8 GH_VO_I80_get_Cmd_Format_cmd_transfer_format(void)
  625. {
  626. GH_VO_I80_CMD_FORMAT_S tmp_value;
  627. U32 value = (*(volatile U32 *)REG_VO_I80_CMD_FORMAT);
  628. tmp_value.all = value;
  629. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  630. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Cmd_Format_cmd_transfer_format] --> 0x%08x\n",
  631. REG_VO_I80_CMD_FORMAT,value);
  632. #endif
  633. return tmp_value.bitc.cmd_transfer_format;
  634. }
  635. #endif /* GH_INLINE_LEVEL == 0 */
  636. /*----------------------------------------------------------------------------*/
  637. /* register VO_I80_Lcd_Rst_Para1 (read/write) */
  638. /*----------------------------------------------------------------------------*/
  639. #if GH_INLINE_LEVEL == 0
  640. /*! \brief Writes the register 'VO_I80_Lcd_Rst_Para1'. */
  641. void GH_VO_I80_set_Lcd_Rst_Para1(U32 data);
  642. /*! \brief Reads the register 'VO_I80_Lcd_Rst_Para1'. */
  643. U32 GH_VO_I80_get_Lcd_Rst_Para1(void);
  644. /*! \brief Writes the bit group 'lcdrst_first_hlevel' of register 'VO_I80_Lcd_Rst_Para1'. */
  645. void GH_VO_I80_set_Lcd_Rst_Para1_lcdrst_first_hlevel(U16 data);
  646. /*! \brief Reads the bit group 'lcdrst_first_hlevel' of register 'VO_I80_Lcd_Rst_Para1'. */
  647. U16 GH_VO_I80_get_Lcd_Rst_Para1_lcdrst_first_hlevel(void);
  648. /*! \brief Writes the bit group 'lcdrst_en' of register 'VO_I80_Lcd_Rst_Para1'. */
  649. void GH_VO_I80_set_Lcd_Rst_Para1_lcdrst_en(U8 data);
  650. /*! \brief Reads the bit group 'lcdrst_en' of register 'VO_I80_Lcd_Rst_Para1'. */
  651. U8 GH_VO_I80_get_Lcd_Rst_Para1_lcdrst_en(void);
  652. #else /* GH_INLINE_LEVEL == 0 */
  653. GH_INLINE void GH_VO_I80_set_Lcd_Rst_Para1(U32 data)
  654. {
  655. *(volatile U32 *)REG_VO_I80_LCD_RST_PARA1 = data;
  656. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  657. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_Rst_Para1] <-- 0x%08x\n",
  658. REG_VO_I80_LCD_RST_PARA1,data,data);
  659. #endif
  660. }
  661. GH_INLINE U32 GH_VO_I80_get_Lcd_Rst_Para1(void)
  662. {
  663. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_RST_PARA1);
  664. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  665. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_Rst_Para1] --> 0x%08x\n",
  666. REG_VO_I80_LCD_RST_PARA1,value);
  667. #endif
  668. return value;
  669. }
  670. GH_INLINE void GH_VO_I80_set_Lcd_Rst_Para1_lcdrst_first_hlevel(U16 data)
  671. {
  672. GH_VO_I80_LCD_RST_PARA1_S d;
  673. d.all = *(volatile U32 *)REG_VO_I80_LCD_RST_PARA1;
  674. d.bitc.lcdrst_first_hlevel = data;
  675. *(volatile U32 *)REG_VO_I80_LCD_RST_PARA1 = d.all;
  676. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  677. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_Rst_Para1_lcdrst_first_hlevel] <-- 0x%08x\n",
  678. REG_VO_I80_LCD_RST_PARA1,d.all,d.all);
  679. #endif
  680. }
  681. GH_INLINE U16 GH_VO_I80_get_Lcd_Rst_Para1_lcdrst_first_hlevel(void)
  682. {
  683. GH_VO_I80_LCD_RST_PARA1_S tmp_value;
  684. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_RST_PARA1);
  685. tmp_value.all = value;
  686. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  687. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_Rst_Para1_lcdrst_first_hlevel] --> 0x%08x\n",
  688. REG_VO_I80_LCD_RST_PARA1,value);
  689. #endif
  690. return tmp_value.bitc.lcdrst_first_hlevel;
  691. }
  692. GH_INLINE void GH_VO_I80_set_Lcd_Rst_Para1_lcdrst_en(U8 data)
  693. {
  694. GH_VO_I80_LCD_RST_PARA1_S d;
  695. d.all = *(volatile U32 *)REG_VO_I80_LCD_RST_PARA1;
  696. d.bitc.lcdrst_en = data;
  697. *(volatile U32 *)REG_VO_I80_LCD_RST_PARA1 = d.all;
  698. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  699. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_Rst_Para1_lcdrst_en] <-- 0x%08x\n",
  700. REG_VO_I80_LCD_RST_PARA1,d.all,d.all);
  701. #endif
  702. }
  703. GH_INLINE U8 GH_VO_I80_get_Lcd_Rst_Para1_lcdrst_en(void)
  704. {
  705. GH_VO_I80_LCD_RST_PARA1_S tmp_value;
  706. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_RST_PARA1);
  707. tmp_value.all = value;
  708. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  709. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_Rst_Para1_lcdrst_en] --> 0x%08x\n",
  710. REG_VO_I80_LCD_RST_PARA1,value);
  711. #endif
  712. return tmp_value.bitc.lcdrst_en;
  713. }
  714. #endif /* GH_INLINE_LEVEL == 0 */
  715. /*----------------------------------------------------------------------------*/
  716. /* register VO_I80_Lcd_Rst_Para2 (read/write) */
  717. /*----------------------------------------------------------------------------*/
  718. #if GH_INLINE_LEVEL == 0
  719. /*! \brief Writes the register 'VO_I80_Lcd_Rst_Para2'. */
  720. void GH_VO_I80_set_Lcd_Rst_Para2(U32 data);
  721. /*! \brief Reads the register 'VO_I80_Lcd_Rst_Para2'. */
  722. U32 GH_VO_I80_get_Lcd_Rst_Para2(void);
  723. /*! \brief Writes the bit group 'lcdrst_level' of register 'VO_I80_Lcd_Rst_Para2'. */
  724. void GH_VO_I80_set_Lcd_Rst_Para2_lcdrst_level(U16 data);
  725. /*! \brief Reads the bit group 'lcdrst_level' of register 'VO_I80_Lcd_Rst_Para2'. */
  726. U16 GH_VO_I80_get_Lcd_Rst_Para2_lcdrst_level(void);
  727. /*! \brief Writes the bit group 'lcdrst_hsetup' of register 'VO_I80_Lcd_Rst_Para2'. */
  728. void GH_VO_I80_set_Lcd_Rst_Para2_lcdrst_hsetup(U16 data);
  729. /*! \brief Reads the bit group 'lcdrst_hsetup' of register 'VO_I80_Lcd_Rst_Para2'. */
  730. U16 GH_VO_I80_get_Lcd_Rst_Para2_lcdrst_hsetup(void);
  731. #else /* GH_INLINE_LEVEL == 0 */
  732. GH_INLINE void GH_VO_I80_set_Lcd_Rst_Para2(U32 data)
  733. {
  734. *(volatile U32 *)REG_VO_I80_LCD_RST_PARA2 = data;
  735. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  736. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_Rst_Para2] <-- 0x%08x\n",
  737. REG_VO_I80_LCD_RST_PARA2,data,data);
  738. #endif
  739. }
  740. GH_INLINE U32 GH_VO_I80_get_Lcd_Rst_Para2(void)
  741. {
  742. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_RST_PARA2);
  743. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  744. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_Rst_Para2] --> 0x%08x\n",
  745. REG_VO_I80_LCD_RST_PARA2,value);
  746. #endif
  747. return value;
  748. }
  749. GH_INLINE void GH_VO_I80_set_Lcd_Rst_Para2_lcdrst_level(U16 data)
  750. {
  751. GH_VO_I80_LCD_RST_PARA2_S d;
  752. d.all = *(volatile U32 *)REG_VO_I80_LCD_RST_PARA2;
  753. d.bitc.lcdrst_level = data;
  754. *(volatile U32 *)REG_VO_I80_LCD_RST_PARA2 = d.all;
  755. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  756. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_Rst_Para2_lcdrst_level] <-- 0x%08x\n",
  757. REG_VO_I80_LCD_RST_PARA2,d.all,d.all);
  758. #endif
  759. }
  760. GH_INLINE U16 GH_VO_I80_get_Lcd_Rst_Para2_lcdrst_level(void)
  761. {
  762. GH_VO_I80_LCD_RST_PARA2_S tmp_value;
  763. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_RST_PARA2);
  764. tmp_value.all = value;
  765. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  766. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_Rst_Para2_lcdrst_level] --> 0x%08x\n",
  767. REG_VO_I80_LCD_RST_PARA2,value);
  768. #endif
  769. return tmp_value.bitc.lcdrst_level;
  770. }
  771. GH_INLINE void GH_VO_I80_set_Lcd_Rst_Para2_lcdrst_hsetup(U16 data)
  772. {
  773. GH_VO_I80_LCD_RST_PARA2_S d;
  774. d.all = *(volatile U32 *)REG_VO_I80_LCD_RST_PARA2;
  775. d.bitc.lcdrst_hsetup = data;
  776. *(volatile U32 *)REG_VO_I80_LCD_RST_PARA2 = d.all;
  777. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  778. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_Rst_Para2_lcdrst_hsetup] <-- 0x%08x\n",
  779. REG_VO_I80_LCD_RST_PARA2,d.all,d.all);
  780. #endif
  781. }
  782. GH_INLINE U16 GH_VO_I80_get_Lcd_Rst_Para2_lcdrst_hsetup(void)
  783. {
  784. GH_VO_I80_LCD_RST_PARA2_S tmp_value;
  785. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_RST_PARA2);
  786. tmp_value.all = value;
  787. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  788. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_Rst_Para2_lcdrst_hsetup] --> 0x%08x\n",
  789. REG_VO_I80_LCD_RST_PARA2,value);
  790. #endif
  791. return tmp_value.bitc.lcdrst_hsetup;
  792. }
  793. #endif /* GH_INLINE_LEVEL == 0 */
  794. /*----------------------------------------------------------------------------*/
  795. /* register VO_I80_Delay_Para (read/write) */
  796. /*----------------------------------------------------------------------------*/
  797. #if GH_INLINE_LEVEL == 0
  798. /*! \brief Writes the register 'VO_I80_Delay_Para'. */
  799. void GH_VO_I80_set_Delay_Para(U32 data);
  800. /*! \brief Reads the register 'VO_I80_Delay_Para'. */
  801. U32 GH_VO_I80_get_Delay_Para(void);
  802. /*! \brief Writes the bit group 'delay_cmd' of register 'VO_I80_Delay_Para'. */
  803. void GH_VO_I80_set_Delay_Para_delay_cmd(U16 data);
  804. /*! \brief Reads the bit group 'delay_cmd' of register 'VO_I80_Delay_Para'. */
  805. U16 GH_VO_I80_get_Delay_Para_delay_cmd(void);
  806. /*! \brief Writes the bit group 'delay_time' of register 'VO_I80_Delay_Para'. */
  807. void GH_VO_I80_set_Delay_Para_delay_time(U16 data);
  808. /*! \brief Reads the bit group 'delay_time' of register 'VO_I80_Delay_Para'. */
  809. U16 GH_VO_I80_get_Delay_Para_delay_time(void);
  810. /*! \brief Writes the bit group 'delay_cmd_en' of register 'VO_I80_Delay_Para'. */
  811. void GH_VO_I80_set_Delay_Para_delay_cmd_en(U8 data);
  812. /*! \brief Reads the bit group 'delay_cmd_en' of register 'VO_I80_Delay_Para'. */
  813. U8 GH_VO_I80_get_Delay_Para_delay_cmd_en(void);
  814. #else /* GH_INLINE_LEVEL == 0 */
  815. GH_INLINE void GH_VO_I80_set_Delay_Para(U32 data)
  816. {
  817. *(volatile U32 *)REG_VO_I80_DELAY_PARA = data;
  818. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  819. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Delay_Para] <-- 0x%08x\n",
  820. REG_VO_I80_DELAY_PARA,data,data);
  821. #endif
  822. }
  823. GH_INLINE U32 GH_VO_I80_get_Delay_Para(void)
  824. {
  825. U32 value = (*(volatile U32 *)REG_VO_I80_DELAY_PARA);
  826. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  827. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Delay_Para] --> 0x%08x\n",
  828. REG_VO_I80_DELAY_PARA,value);
  829. #endif
  830. return value;
  831. }
  832. GH_INLINE void GH_VO_I80_set_Delay_Para_delay_cmd(U16 data)
  833. {
  834. GH_VO_I80_DELAY_PARA_S d;
  835. d.all = *(volatile U32 *)REG_VO_I80_DELAY_PARA;
  836. d.bitc.delay_cmd = data;
  837. *(volatile U32 *)REG_VO_I80_DELAY_PARA = d.all;
  838. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  839. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Delay_Para_delay_cmd] <-- 0x%08x\n",
  840. REG_VO_I80_DELAY_PARA,d.all,d.all);
  841. #endif
  842. }
  843. GH_INLINE U16 GH_VO_I80_get_Delay_Para_delay_cmd(void)
  844. {
  845. GH_VO_I80_DELAY_PARA_S tmp_value;
  846. U32 value = (*(volatile U32 *)REG_VO_I80_DELAY_PARA);
  847. tmp_value.all = value;
  848. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  849. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Delay_Para_delay_cmd] --> 0x%08x\n",
  850. REG_VO_I80_DELAY_PARA,value);
  851. #endif
  852. return tmp_value.bitc.delay_cmd;
  853. }
  854. GH_INLINE void GH_VO_I80_set_Delay_Para_delay_time(U16 data)
  855. {
  856. GH_VO_I80_DELAY_PARA_S d;
  857. d.all = *(volatile U32 *)REG_VO_I80_DELAY_PARA;
  858. d.bitc.delay_time = data;
  859. *(volatile U32 *)REG_VO_I80_DELAY_PARA = d.all;
  860. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  861. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Delay_Para_delay_time] <-- 0x%08x\n",
  862. REG_VO_I80_DELAY_PARA,d.all,d.all);
  863. #endif
  864. }
  865. GH_INLINE U16 GH_VO_I80_get_Delay_Para_delay_time(void)
  866. {
  867. GH_VO_I80_DELAY_PARA_S tmp_value;
  868. U32 value = (*(volatile U32 *)REG_VO_I80_DELAY_PARA);
  869. tmp_value.all = value;
  870. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  871. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Delay_Para_delay_time] --> 0x%08x\n",
  872. REG_VO_I80_DELAY_PARA,value);
  873. #endif
  874. return tmp_value.bitc.delay_time;
  875. }
  876. GH_INLINE void GH_VO_I80_set_Delay_Para_delay_cmd_en(U8 data)
  877. {
  878. GH_VO_I80_DELAY_PARA_S d;
  879. d.all = *(volatile U32 *)REG_VO_I80_DELAY_PARA;
  880. d.bitc.delay_cmd_en = data;
  881. *(volatile U32 *)REG_VO_I80_DELAY_PARA = d.all;
  882. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  883. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Delay_Para_delay_cmd_en] <-- 0x%08x\n",
  884. REG_VO_I80_DELAY_PARA,d.all,d.all);
  885. #endif
  886. }
  887. GH_INLINE U8 GH_VO_I80_get_Delay_Para_delay_cmd_en(void)
  888. {
  889. GH_VO_I80_DELAY_PARA_S tmp_value;
  890. U32 value = (*(volatile U32 *)REG_VO_I80_DELAY_PARA);
  891. tmp_value.all = value;
  892. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  893. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Delay_Para_delay_cmd_en] --> 0x%08x\n",
  894. REG_VO_I80_DELAY_PARA,value);
  895. #endif
  896. return tmp_value.bitc.delay_cmd_en;
  897. }
  898. #endif /* GH_INLINE_LEVEL == 0 */
  899. /*----------------------------------------------------------------------------*/
  900. /* register VO_I80_Twr_Timing (read/write) */
  901. /*----------------------------------------------------------------------------*/
  902. #if GH_INLINE_LEVEL == 0
  903. /*! \brief Writes the register 'VO_I80_Twr_Timing'. */
  904. void GH_VO_I80_set_Twr_Timing(U32 data);
  905. /*! \brief Reads the register 'VO_I80_Twr_Timing'. */
  906. U32 GH_VO_I80_get_Twr_Timing(void);
  907. /*! \brief Writes the bit group 'twrl' of register 'VO_I80_Twr_Timing'. */
  908. void GH_VO_I80_set_Twr_Timing_twrl(U16 data);
  909. /*! \brief Reads the bit group 'twrl' of register 'VO_I80_Twr_Timing'. */
  910. U16 GH_VO_I80_get_Twr_Timing_twrl(void);
  911. /*! \brief Writes the bit group 'twrh' of register 'VO_I80_Twr_Timing'. */
  912. void GH_VO_I80_set_Twr_Timing_twrh(U16 data);
  913. /*! \brief Reads the bit group 'twrh' of register 'VO_I80_Twr_Timing'. */
  914. U16 GH_VO_I80_get_Twr_Timing_twrh(void);
  915. #else /* GH_INLINE_LEVEL == 0 */
  916. GH_INLINE void GH_VO_I80_set_Twr_Timing(U32 data)
  917. {
  918. *(volatile U32 *)REG_VO_I80_TWR_TIMING = data;
  919. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  920. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Twr_Timing] <-- 0x%08x\n",
  921. REG_VO_I80_TWR_TIMING,data,data);
  922. #endif
  923. }
  924. GH_INLINE U32 GH_VO_I80_get_Twr_Timing(void)
  925. {
  926. U32 value = (*(volatile U32 *)REG_VO_I80_TWR_TIMING);
  927. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  928. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Twr_Timing] --> 0x%08x\n",
  929. REG_VO_I80_TWR_TIMING,value);
  930. #endif
  931. return value;
  932. }
  933. GH_INLINE void GH_VO_I80_set_Twr_Timing_twrl(U16 data)
  934. {
  935. GH_VO_I80_TWR_TIMING_S d;
  936. d.all = *(volatile U32 *)REG_VO_I80_TWR_TIMING;
  937. d.bitc.twrl = data;
  938. *(volatile U32 *)REG_VO_I80_TWR_TIMING = d.all;
  939. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  940. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Twr_Timing_twrl] <-- 0x%08x\n",
  941. REG_VO_I80_TWR_TIMING,d.all,d.all);
  942. #endif
  943. }
  944. GH_INLINE U16 GH_VO_I80_get_Twr_Timing_twrl(void)
  945. {
  946. GH_VO_I80_TWR_TIMING_S tmp_value;
  947. U32 value = (*(volatile U32 *)REG_VO_I80_TWR_TIMING);
  948. tmp_value.all = value;
  949. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  950. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Twr_Timing_twrl] --> 0x%08x\n",
  951. REG_VO_I80_TWR_TIMING,value);
  952. #endif
  953. return tmp_value.bitc.twrl;
  954. }
  955. GH_INLINE void GH_VO_I80_set_Twr_Timing_twrh(U16 data)
  956. {
  957. GH_VO_I80_TWR_TIMING_S d;
  958. d.all = *(volatile U32 *)REG_VO_I80_TWR_TIMING;
  959. d.bitc.twrh = data;
  960. *(volatile U32 *)REG_VO_I80_TWR_TIMING = d.all;
  961. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  962. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Twr_Timing_twrh] <-- 0x%08x\n",
  963. REG_VO_I80_TWR_TIMING,d.all,d.all);
  964. #endif
  965. }
  966. GH_INLINE U16 GH_VO_I80_get_Twr_Timing_twrh(void)
  967. {
  968. GH_VO_I80_TWR_TIMING_S tmp_value;
  969. U32 value = (*(volatile U32 *)REG_VO_I80_TWR_TIMING);
  970. tmp_value.all = value;
  971. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  972. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Twr_Timing_twrh] --> 0x%08x\n",
  973. REG_VO_I80_TWR_TIMING,value);
  974. #endif
  975. return tmp_value.bitc.twrh;
  976. }
  977. #endif /* GH_INLINE_LEVEL == 0 */
  978. /*----------------------------------------------------------------------------*/
  979. /* register VO_I80_Trd_Timing (read/write) */
  980. /*----------------------------------------------------------------------------*/
  981. #if GH_INLINE_LEVEL == 0
  982. /*! \brief Writes the register 'VO_I80_Trd_Timing'. */
  983. void GH_VO_I80_set_Trd_Timing(U32 data);
  984. /*! \brief Reads the register 'VO_I80_Trd_Timing'. */
  985. U32 GH_VO_I80_get_Trd_Timing(void);
  986. /*! \brief Writes the bit group 'trdl' of register 'VO_I80_Trd_Timing'. */
  987. void GH_VO_I80_set_Trd_Timing_trdl(U16 data);
  988. /*! \brief Reads the bit group 'trdl' of register 'VO_I80_Trd_Timing'. */
  989. U16 GH_VO_I80_get_Trd_Timing_trdl(void);
  990. /*! \brief Writes the bit group 'trdh' of register 'VO_I80_Trd_Timing'. */
  991. void GH_VO_I80_set_Trd_Timing_trdh(U16 data);
  992. /*! \brief Reads the bit group 'trdh' of register 'VO_I80_Trd_Timing'. */
  993. U16 GH_VO_I80_get_Trd_Timing_trdh(void);
  994. #else /* GH_INLINE_LEVEL == 0 */
  995. GH_INLINE void GH_VO_I80_set_Trd_Timing(U32 data)
  996. {
  997. *(volatile U32 *)REG_VO_I80_TRD_TIMING = data;
  998. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  999. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Trd_Timing] <-- 0x%08x\n",
  1000. REG_VO_I80_TRD_TIMING,data,data);
  1001. #endif
  1002. }
  1003. GH_INLINE U32 GH_VO_I80_get_Trd_Timing(void)
  1004. {
  1005. U32 value = (*(volatile U32 *)REG_VO_I80_TRD_TIMING);
  1006. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1007. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Trd_Timing] --> 0x%08x\n",
  1008. REG_VO_I80_TRD_TIMING,value);
  1009. #endif
  1010. return value;
  1011. }
  1012. GH_INLINE void GH_VO_I80_set_Trd_Timing_trdl(U16 data)
  1013. {
  1014. GH_VO_I80_TRD_TIMING_S d;
  1015. d.all = *(volatile U32 *)REG_VO_I80_TRD_TIMING;
  1016. d.bitc.trdl = data;
  1017. *(volatile U32 *)REG_VO_I80_TRD_TIMING = d.all;
  1018. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1019. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Trd_Timing_trdl] <-- 0x%08x\n",
  1020. REG_VO_I80_TRD_TIMING,d.all,d.all);
  1021. #endif
  1022. }
  1023. GH_INLINE U16 GH_VO_I80_get_Trd_Timing_trdl(void)
  1024. {
  1025. GH_VO_I80_TRD_TIMING_S tmp_value;
  1026. U32 value = (*(volatile U32 *)REG_VO_I80_TRD_TIMING);
  1027. tmp_value.all = value;
  1028. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1029. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Trd_Timing_trdl] --> 0x%08x\n",
  1030. REG_VO_I80_TRD_TIMING,value);
  1031. #endif
  1032. return tmp_value.bitc.trdl;
  1033. }
  1034. GH_INLINE void GH_VO_I80_set_Trd_Timing_trdh(U16 data)
  1035. {
  1036. GH_VO_I80_TRD_TIMING_S d;
  1037. d.all = *(volatile U32 *)REG_VO_I80_TRD_TIMING;
  1038. d.bitc.trdh = data;
  1039. *(volatile U32 *)REG_VO_I80_TRD_TIMING = d.all;
  1040. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1041. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Trd_Timing_trdh] <-- 0x%08x\n",
  1042. REG_VO_I80_TRD_TIMING,d.all,d.all);
  1043. #endif
  1044. }
  1045. GH_INLINE U16 GH_VO_I80_get_Trd_Timing_trdh(void)
  1046. {
  1047. GH_VO_I80_TRD_TIMING_S tmp_value;
  1048. U32 value = (*(volatile U32 *)REG_VO_I80_TRD_TIMING);
  1049. tmp_value.all = value;
  1050. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1051. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Trd_Timing_trdh] --> 0x%08x\n",
  1052. REG_VO_I80_TRD_TIMING,value);
  1053. #endif
  1054. return tmp_value.bitc.trdh;
  1055. }
  1056. #endif /* GH_INLINE_LEVEL == 0 */
  1057. /*----------------------------------------------------------------------------*/
  1058. /* register VO_I80_Tcs_Timing (read/write) */
  1059. /*----------------------------------------------------------------------------*/
  1060. #if GH_INLINE_LEVEL == 0
  1061. /*! \brief Writes the register 'VO_I80_Tcs_Timing'. */
  1062. void GH_VO_I80_set_Tcs_Timing(U32 data);
  1063. /*! \brief Reads the register 'VO_I80_Tcs_Timing'. */
  1064. U32 GH_VO_I80_get_Tcs_Timing(void);
  1065. /*! \brief Writes the bit group 'tas' of register 'VO_I80_Tcs_Timing'. */
  1066. void GH_VO_I80_set_Tcs_Timing_tas(U8 data);
  1067. /*! \brief Reads the bit group 'tas' of register 'VO_I80_Tcs_Timing'. */
  1068. U8 GH_VO_I80_get_Tcs_Timing_tas(void);
  1069. /*! \brief Writes the bit group 'cs_ref' of register 'VO_I80_Tcs_Timing'. */
  1070. void GH_VO_I80_set_Tcs_Timing_cs_ref(U8 data);
  1071. /*! \brief Reads the bit group 'cs_ref' of register 'VO_I80_Tcs_Timing'. */
  1072. U8 GH_VO_I80_get_Tcs_Timing_cs_ref(void);
  1073. #else /* GH_INLINE_LEVEL == 0 */
  1074. GH_INLINE void GH_VO_I80_set_Tcs_Timing(U32 data)
  1075. {
  1076. *(volatile U32 *)REG_VO_I80_TCS_TIMING = data;
  1077. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1078. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcs_Timing] <-- 0x%08x\n",
  1079. REG_VO_I80_TCS_TIMING,data,data);
  1080. #endif
  1081. }
  1082. GH_INLINE U32 GH_VO_I80_get_Tcs_Timing(void)
  1083. {
  1084. U32 value = (*(volatile U32 *)REG_VO_I80_TCS_TIMING);
  1085. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1086. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcs_Timing] --> 0x%08x\n",
  1087. REG_VO_I80_TCS_TIMING,value);
  1088. #endif
  1089. return value;
  1090. }
  1091. GH_INLINE void GH_VO_I80_set_Tcs_Timing_tas(U8 data)
  1092. {
  1093. GH_VO_I80_TCS_TIMING_S d;
  1094. d.all = *(volatile U32 *)REG_VO_I80_TCS_TIMING;
  1095. d.bitc.tas = data;
  1096. *(volatile U32 *)REG_VO_I80_TCS_TIMING = d.all;
  1097. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1098. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcs_Timing_tas] <-- 0x%08x\n",
  1099. REG_VO_I80_TCS_TIMING,d.all,d.all);
  1100. #endif
  1101. }
  1102. GH_INLINE U8 GH_VO_I80_get_Tcs_Timing_tas(void)
  1103. {
  1104. GH_VO_I80_TCS_TIMING_S tmp_value;
  1105. U32 value = (*(volatile U32 *)REG_VO_I80_TCS_TIMING);
  1106. tmp_value.all = value;
  1107. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1108. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcs_Timing_tas] --> 0x%08x\n",
  1109. REG_VO_I80_TCS_TIMING,value);
  1110. #endif
  1111. return tmp_value.bitc.tas;
  1112. }
  1113. GH_INLINE void GH_VO_I80_set_Tcs_Timing_cs_ref(U8 data)
  1114. {
  1115. GH_VO_I80_TCS_TIMING_S d;
  1116. d.all = *(volatile U32 *)REG_VO_I80_TCS_TIMING;
  1117. d.bitc.cs_ref = data;
  1118. *(volatile U32 *)REG_VO_I80_TCS_TIMING = d.all;
  1119. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1120. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcs_Timing_cs_ref] <-- 0x%08x\n",
  1121. REG_VO_I80_TCS_TIMING,d.all,d.all);
  1122. #endif
  1123. }
  1124. GH_INLINE U8 GH_VO_I80_get_Tcs_Timing_cs_ref(void)
  1125. {
  1126. GH_VO_I80_TCS_TIMING_S tmp_value;
  1127. U32 value = (*(volatile U32 *)REG_VO_I80_TCS_TIMING);
  1128. tmp_value.all = value;
  1129. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1130. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcs_Timing_cs_ref] --> 0x%08x\n",
  1131. REG_VO_I80_TCS_TIMING,value);
  1132. #endif
  1133. return tmp_value.bitc.cs_ref;
  1134. }
  1135. #endif /* GH_INLINE_LEVEL == 0 */
  1136. /*----------------------------------------------------------------------------*/
  1137. /* register VO_I80_Polar_Ctrl (read/write) */
  1138. /*----------------------------------------------------------------------------*/
  1139. #if GH_INLINE_LEVEL == 0
  1140. /*! \brief Writes the register 'VO_I80_Polar_Ctrl'. */
  1141. void GH_VO_I80_set_Polar_Ctrl(U32 data);
  1142. /*! \brief Reads the register 'VO_I80_Polar_Ctrl'. */
  1143. U32 GH_VO_I80_get_Polar_Ctrl(void);
  1144. /*! \brief Writes the bit group 'wr_polar' of register 'VO_I80_Polar_Ctrl'. */
  1145. void GH_VO_I80_set_Polar_Ctrl_wr_polar(U8 data);
  1146. /*! \brief Reads the bit group 'wr_polar' of register 'VO_I80_Polar_Ctrl'. */
  1147. U8 GH_VO_I80_get_Polar_Ctrl_wr_polar(void);
  1148. /*! \brief Writes the bit group 'rd_polar' of register 'VO_I80_Polar_Ctrl'. */
  1149. void GH_VO_I80_set_Polar_Ctrl_rd_polar(U8 data);
  1150. /*! \brief Reads the bit group 'rd_polar' of register 'VO_I80_Polar_Ctrl'. */
  1151. U8 GH_VO_I80_get_Polar_Ctrl_rd_polar(void);
  1152. /*! \brief Writes the bit group 'lcdrst_polar' of register 'VO_I80_Polar_Ctrl'. */
  1153. void GH_VO_I80_set_Polar_Ctrl_lcdrst_polar(U8 data);
  1154. /*! \brief Reads the bit group 'lcdrst_polar' of register 'VO_I80_Polar_Ctrl'. */
  1155. U8 GH_VO_I80_get_Polar_Ctrl_lcdrst_polar(void);
  1156. /*! \brief Writes the bit group 'vsync_polar' of register 'VO_I80_Polar_Ctrl'. */
  1157. void GH_VO_I80_set_Polar_Ctrl_vsync_polar(U8 data);
  1158. /*! \brief Reads the bit group 'vsync_polar' of register 'VO_I80_Polar_Ctrl'. */
  1159. U8 GH_VO_I80_get_Polar_Ctrl_vsync_polar(void);
  1160. /*! \brief Writes the bit group 'cs_polar' of register 'VO_I80_Polar_Ctrl'. */
  1161. void GH_VO_I80_set_Polar_Ctrl_cs_polar(U8 data);
  1162. /*! \brief Reads the bit group 'cs_polar' of register 'VO_I80_Polar_Ctrl'. */
  1163. U8 GH_VO_I80_get_Polar_Ctrl_cs_polar(void);
  1164. /*! \brief Writes the bit group 'dc_polar' of register 'VO_I80_Polar_Ctrl'. */
  1165. void GH_VO_I80_set_Polar_Ctrl_dc_polar(U8 data);
  1166. /*! \brief Reads the bit group 'dc_polar' of register 'VO_I80_Polar_Ctrl'. */
  1167. U8 GH_VO_I80_get_Polar_Ctrl_dc_polar(void);
  1168. #else /* GH_INLINE_LEVEL == 0 */
  1169. GH_INLINE void GH_VO_I80_set_Polar_Ctrl(U32 data)
  1170. {
  1171. *(volatile U32 *)REG_VO_I80_POLAR_CTRL = data;
  1172. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1173. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Polar_Ctrl] <-- 0x%08x\n",
  1174. REG_VO_I80_POLAR_CTRL,data,data);
  1175. #endif
  1176. }
  1177. GH_INLINE U32 GH_VO_I80_get_Polar_Ctrl(void)
  1178. {
  1179. U32 value = (*(volatile U32 *)REG_VO_I80_POLAR_CTRL);
  1180. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1181. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Polar_Ctrl] --> 0x%08x\n",
  1182. REG_VO_I80_POLAR_CTRL,value);
  1183. #endif
  1184. return value;
  1185. }
  1186. GH_INLINE void GH_VO_I80_set_Polar_Ctrl_wr_polar(U8 data)
  1187. {
  1188. GH_VO_I80_POLAR_CTRL_S d;
  1189. d.all = *(volatile U32 *)REG_VO_I80_POLAR_CTRL;
  1190. d.bitc.wr_polar = data;
  1191. *(volatile U32 *)REG_VO_I80_POLAR_CTRL = d.all;
  1192. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1193. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Polar_Ctrl_wr_polar] <-- 0x%08x\n",
  1194. REG_VO_I80_POLAR_CTRL,d.all,d.all);
  1195. #endif
  1196. }
  1197. GH_INLINE U8 GH_VO_I80_get_Polar_Ctrl_wr_polar(void)
  1198. {
  1199. GH_VO_I80_POLAR_CTRL_S tmp_value;
  1200. U32 value = (*(volatile U32 *)REG_VO_I80_POLAR_CTRL);
  1201. tmp_value.all = value;
  1202. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1203. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Polar_Ctrl_wr_polar] --> 0x%08x\n",
  1204. REG_VO_I80_POLAR_CTRL,value);
  1205. #endif
  1206. return tmp_value.bitc.wr_polar;
  1207. }
  1208. GH_INLINE void GH_VO_I80_set_Polar_Ctrl_rd_polar(U8 data)
  1209. {
  1210. GH_VO_I80_POLAR_CTRL_S d;
  1211. d.all = *(volatile U32 *)REG_VO_I80_POLAR_CTRL;
  1212. d.bitc.rd_polar = data;
  1213. *(volatile U32 *)REG_VO_I80_POLAR_CTRL = d.all;
  1214. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1215. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Polar_Ctrl_rd_polar] <-- 0x%08x\n",
  1216. REG_VO_I80_POLAR_CTRL,d.all,d.all);
  1217. #endif
  1218. }
  1219. GH_INLINE U8 GH_VO_I80_get_Polar_Ctrl_rd_polar(void)
  1220. {
  1221. GH_VO_I80_POLAR_CTRL_S tmp_value;
  1222. U32 value = (*(volatile U32 *)REG_VO_I80_POLAR_CTRL);
  1223. tmp_value.all = value;
  1224. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1225. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Polar_Ctrl_rd_polar] --> 0x%08x\n",
  1226. REG_VO_I80_POLAR_CTRL,value);
  1227. #endif
  1228. return tmp_value.bitc.rd_polar;
  1229. }
  1230. GH_INLINE void GH_VO_I80_set_Polar_Ctrl_lcdrst_polar(U8 data)
  1231. {
  1232. GH_VO_I80_POLAR_CTRL_S d;
  1233. d.all = *(volatile U32 *)REG_VO_I80_POLAR_CTRL;
  1234. d.bitc.lcdrst_polar = data;
  1235. *(volatile U32 *)REG_VO_I80_POLAR_CTRL = d.all;
  1236. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1237. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Polar_Ctrl_lcdrst_polar] <-- 0x%08x\n",
  1238. REG_VO_I80_POLAR_CTRL,d.all,d.all);
  1239. #endif
  1240. }
  1241. GH_INLINE U8 GH_VO_I80_get_Polar_Ctrl_lcdrst_polar(void)
  1242. {
  1243. GH_VO_I80_POLAR_CTRL_S tmp_value;
  1244. U32 value = (*(volatile U32 *)REG_VO_I80_POLAR_CTRL);
  1245. tmp_value.all = value;
  1246. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1247. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Polar_Ctrl_lcdrst_polar] --> 0x%08x\n",
  1248. REG_VO_I80_POLAR_CTRL,value);
  1249. #endif
  1250. return tmp_value.bitc.lcdrst_polar;
  1251. }
  1252. GH_INLINE void GH_VO_I80_set_Polar_Ctrl_vsync_polar(U8 data)
  1253. {
  1254. GH_VO_I80_POLAR_CTRL_S d;
  1255. d.all = *(volatile U32 *)REG_VO_I80_POLAR_CTRL;
  1256. d.bitc.vsync_polar = data;
  1257. *(volatile U32 *)REG_VO_I80_POLAR_CTRL = d.all;
  1258. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1259. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Polar_Ctrl_vsync_polar] <-- 0x%08x\n",
  1260. REG_VO_I80_POLAR_CTRL,d.all,d.all);
  1261. #endif
  1262. }
  1263. GH_INLINE U8 GH_VO_I80_get_Polar_Ctrl_vsync_polar(void)
  1264. {
  1265. GH_VO_I80_POLAR_CTRL_S tmp_value;
  1266. U32 value = (*(volatile U32 *)REG_VO_I80_POLAR_CTRL);
  1267. tmp_value.all = value;
  1268. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1269. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Polar_Ctrl_vsync_polar] --> 0x%08x\n",
  1270. REG_VO_I80_POLAR_CTRL,value);
  1271. #endif
  1272. return tmp_value.bitc.vsync_polar;
  1273. }
  1274. GH_INLINE void GH_VO_I80_set_Polar_Ctrl_cs_polar(U8 data)
  1275. {
  1276. GH_VO_I80_POLAR_CTRL_S d;
  1277. d.all = *(volatile U32 *)REG_VO_I80_POLAR_CTRL;
  1278. d.bitc.cs_polar = data;
  1279. *(volatile U32 *)REG_VO_I80_POLAR_CTRL = d.all;
  1280. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1281. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Polar_Ctrl_cs_polar] <-- 0x%08x\n",
  1282. REG_VO_I80_POLAR_CTRL,d.all,d.all);
  1283. #endif
  1284. }
  1285. GH_INLINE U8 GH_VO_I80_get_Polar_Ctrl_cs_polar(void)
  1286. {
  1287. GH_VO_I80_POLAR_CTRL_S tmp_value;
  1288. U32 value = (*(volatile U32 *)REG_VO_I80_POLAR_CTRL);
  1289. tmp_value.all = value;
  1290. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1291. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Polar_Ctrl_cs_polar] --> 0x%08x\n",
  1292. REG_VO_I80_POLAR_CTRL,value);
  1293. #endif
  1294. return tmp_value.bitc.cs_polar;
  1295. }
  1296. GH_INLINE void GH_VO_I80_set_Polar_Ctrl_dc_polar(U8 data)
  1297. {
  1298. GH_VO_I80_POLAR_CTRL_S d;
  1299. d.all = *(volatile U32 *)REG_VO_I80_POLAR_CTRL;
  1300. d.bitc.dc_polar = data;
  1301. *(volatile U32 *)REG_VO_I80_POLAR_CTRL = d.all;
  1302. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1303. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Polar_Ctrl_dc_polar] <-- 0x%08x\n",
  1304. REG_VO_I80_POLAR_CTRL,d.all,d.all);
  1305. #endif
  1306. }
  1307. GH_INLINE U8 GH_VO_I80_get_Polar_Ctrl_dc_polar(void)
  1308. {
  1309. GH_VO_I80_POLAR_CTRL_S tmp_value;
  1310. U32 value = (*(volatile U32 *)REG_VO_I80_POLAR_CTRL);
  1311. tmp_value.all = value;
  1312. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1313. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Polar_Ctrl_dc_polar] --> 0x%08x\n",
  1314. REG_VO_I80_POLAR_CTRL,value);
  1315. #endif
  1316. return tmp_value.bitc.dc_polar;
  1317. }
  1318. #endif /* GH_INLINE_LEVEL == 0 */
  1319. /*----------------------------------------------------------------------------*/
  1320. /* register VO_I80_Ctrl (read/write) */
  1321. /*----------------------------------------------------------------------------*/
  1322. #if GH_INLINE_LEVEL == 0
  1323. /*! \brief Writes the register 'VO_I80_Ctrl'. */
  1324. void GH_VO_I80_set_Ctrl(U32 data);
  1325. /*! \brief Reads the register 'VO_I80_Ctrl'. */
  1326. U32 GH_VO_I80_get_Ctrl(void);
  1327. /*! \brief Writes the bit group 'cfg_end' of register 'VO_I80_Ctrl'. */
  1328. void GH_VO_I80_set_Ctrl_cfg_end(U8 data);
  1329. /*! \brief Reads the bit group 'cfg_end' of register 'VO_I80_Ctrl'. */
  1330. U8 GH_VO_I80_get_Ctrl_cfg_end(void);
  1331. /*! \brief Writes the bit group 'module_en' of register 'VO_I80_Ctrl'. */
  1332. void GH_VO_I80_set_Ctrl_module_en(U8 data);
  1333. /*! \brief Reads the bit group 'module_en' of register 'VO_I80_Ctrl'. */
  1334. U8 GH_VO_I80_get_Ctrl_module_en(void);
  1335. #else /* GH_INLINE_LEVEL == 0 */
  1336. GH_INLINE void GH_VO_I80_set_Ctrl(U32 data)
  1337. {
  1338. *(volatile U32 *)REG_VO_I80_CTRL = data;
  1339. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1340. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Ctrl] <-- 0x%08x\n",
  1341. REG_VO_I80_CTRL,data,data);
  1342. #endif
  1343. }
  1344. GH_INLINE U32 GH_VO_I80_get_Ctrl(void)
  1345. {
  1346. U32 value = (*(volatile U32 *)REG_VO_I80_CTRL);
  1347. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1348. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Ctrl] --> 0x%08x\n",
  1349. REG_VO_I80_CTRL,value);
  1350. #endif
  1351. return value;
  1352. }
  1353. GH_INLINE void GH_VO_I80_set_Ctrl_cfg_end(U8 data)
  1354. {
  1355. GH_VO_I80_CTRL_S d;
  1356. d.all = *(volatile U32 *)REG_VO_I80_CTRL;
  1357. d.bitc.cfg_end = data;
  1358. *(volatile U32 *)REG_VO_I80_CTRL = d.all;
  1359. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1360. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Ctrl_cfg_end] <-- 0x%08x\n",
  1361. REG_VO_I80_CTRL,d.all,d.all);
  1362. #endif
  1363. }
  1364. GH_INLINE U8 GH_VO_I80_get_Ctrl_cfg_end(void)
  1365. {
  1366. GH_VO_I80_CTRL_S tmp_value;
  1367. U32 value = (*(volatile U32 *)REG_VO_I80_CTRL);
  1368. tmp_value.all = value;
  1369. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1370. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Ctrl_cfg_end] --> 0x%08x\n",
  1371. REG_VO_I80_CTRL,value);
  1372. #endif
  1373. return tmp_value.bitc.cfg_end;
  1374. }
  1375. GH_INLINE void GH_VO_I80_set_Ctrl_module_en(U8 data)
  1376. {
  1377. GH_VO_I80_CTRL_S d;
  1378. d.all = *(volatile U32 *)REG_VO_I80_CTRL;
  1379. d.bitc.module_en = data;
  1380. *(volatile U32 *)REG_VO_I80_CTRL = d.all;
  1381. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1382. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Ctrl_module_en] <-- 0x%08x\n",
  1383. REG_VO_I80_CTRL,d.all,d.all);
  1384. #endif
  1385. }
  1386. GH_INLINE U8 GH_VO_I80_get_Ctrl_module_en(void)
  1387. {
  1388. GH_VO_I80_CTRL_S tmp_value;
  1389. U32 value = (*(volatile U32 *)REG_VO_I80_CTRL);
  1390. tmp_value.all = value;
  1391. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1392. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Ctrl_module_en] --> 0x%08x\n",
  1393. REG_VO_I80_CTRL,value);
  1394. #endif
  1395. return tmp_value.bitc.module_en;
  1396. }
  1397. #endif /* GH_INLINE_LEVEL == 0 */
  1398. /*----------------------------------------------------------------------------*/
  1399. /* register VO_I80_Frame_Counter (read) */
  1400. /*----------------------------------------------------------------------------*/
  1401. #if GH_INLINE_LEVEL == 0
  1402. /*! \brief Reads the register 'VO_I80_Frame_Counter'. */
  1403. U32 GH_VO_I80_get_Frame_Counter(void);
  1404. /*! \brief Reads the bit group 'frame_cnt_out' of register 'VO_I80_Frame_Counter'. */
  1405. U16 GH_VO_I80_get_Frame_Counter_frame_cnt_out(void);
  1406. /*! \brief Reads the bit group 'frame_cnt_in' of register 'VO_I80_Frame_Counter'. */
  1407. U16 GH_VO_I80_get_Frame_Counter_frame_cnt_in(void);
  1408. #else /* GH_INLINE_LEVEL == 0 */
  1409. GH_INLINE U32 GH_VO_I80_get_Frame_Counter(void)
  1410. {
  1411. U32 value = (*(volatile U32 *)REG_VO_I80_FRAME_COUNTER);
  1412. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1413. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Frame_Counter] --> 0x%08x\n",
  1414. REG_VO_I80_FRAME_COUNTER,value);
  1415. #endif
  1416. return value;
  1417. }
  1418. GH_INLINE U16 GH_VO_I80_get_Frame_Counter_frame_cnt_out(void)
  1419. {
  1420. GH_VO_I80_FRAME_COUNTER_S tmp_value;
  1421. U32 value = (*(volatile U32 *)REG_VO_I80_FRAME_COUNTER);
  1422. tmp_value.all = value;
  1423. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1424. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Frame_Counter_frame_cnt_out] --> 0x%08x\n",
  1425. REG_VO_I80_FRAME_COUNTER,value);
  1426. #endif
  1427. return tmp_value.bitc.frame_cnt_out;
  1428. }
  1429. GH_INLINE U16 GH_VO_I80_get_Frame_Counter_frame_cnt_in(void)
  1430. {
  1431. GH_VO_I80_FRAME_COUNTER_S tmp_value;
  1432. U32 value = (*(volatile U32 *)REG_VO_I80_FRAME_COUNTER);
  1433. tmp_value.all = value;
  1434. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1435. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Frame_Counter_frame_cnt_in] --> 0x%08x\n",
  1436. REG_VO_I80_FRAME_COUNTER,value);
  1437. #endif
  1438. return tmp_value.bitc.frame_cnt_in;
  1439. }
  1440. #endif /* GH_INLINE_LEVEL == 0 */
  1441. /*----------------------------------------------------------------------------*/
  1442. /* register VO_I80_I80_State (read) */
  1443. /*----------------------------------------------------------------------------*/
  1444. #if GH_INLINE_LEVEL == 0
  1445. /*! \brief Reads the register 'VO_I80_I80_State'. */
  1446. U32 GH_VO_I80_get_I80_State(void);
  1447. /*! \brief Reads the bit group 'cmd_err' of register 'VO_I80_I80_State'. */
  1448. U8 GH_VO_I80_get_I80_State_cmd_err(void);
  1449. /*! \brief Reads the bit group 'sram_overflow' of register 'VO_I80_I80_State'. */
  1450. U8 GH_VO_I80_get_I80_State_sram_overflow(void);
  1451. /*! \brief Reads the bit group 'frame_head_err' of register 'VO_I80_I80_State'. */
  1452. U8 GH_VO_I80_get_I80_State_frame_head_err(void);
  1453. #else /* GH_INLINE_LEVEL == 0 */
  1454. GH_INLINE U32 GH_VO_I80_get_I80_State(void)
  1455. {
  1456. U32 value = (*(volatile U32 *)REG_VO_I80_I80_STATE);
  1457. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1458. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_I80_State] --> 0x%08x\n",
  1459. REG_VO_I80_I80_STATE,value);
  1460. #endif
  1461. return value;
  1462. }
  1463. GH_INLINE U8 GH_VO_I80_get_I80_State_cmd_err(void)
  1464. {
  1465. GH_VO_I80_I80_STATE_S tmp_value;
  1466. U32 value = (*(volatile U32 *)REG_VO_I80_I80_STATE);
  1467. tmp_value.all = value;
  1468. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1469. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_I80_State_cmd_err] --> 0x%08x\n",
  1470. REG_VO_I80_I80_STATE,value);
  1471. #endif
  1472. return tmp_value.bitc.cmd_err;
  1473. }
  1474. GH_INLINE U8 GH_VO_I80_get_I80_State_sram_overflow(void)
  1475. {
  1476. GH_VO_I80_I80_STATE_S tmp_value;
  1477. U32 value = (*(volatile U32 *)REG_VO_I80_I80_STATE);
  1478. tmp_value.all = value;
  1479. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1480. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_I80_State_sram_overflow] --> 0x%08x\n",
  1481. REG_VO_I80_I80_STATE,value);
  1482. #endif
  1483. return tmp_value.bitc.sram_overflow;
  1484. }
  1485. GH_INLINE U8 GH_VO_I80_get_I80_State_frame_head_err(void)
  1486. {
  1487. GH_VO_I80_I80_STATE_S tmp_value;
  1488. U32 value = (*(volatile U32 *)REG_VO_I80_I80_STATE);
  1489. tmp_value.all = value;
  1490. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1491. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_I80_State_frame_head_err] --> 0x%08x\n",
  1492. REG_VO_I80_I80_STATE,value);
  1493. #endif
  1494. return tmp_value.bitc.frame_head_err;
  1495. }
  1496. #endif /* GH_INLINE_LEVEL == 0 */
  1497. /*----------------------------------------------------------------------------*/
  1498. /* register VO_I80_Cmd_Sram_State (read/write) */
  1499. /*----------------------------------------------------------------------------*/
  1500. #if GH_INLINE_LEVEL == 0
  1501. /*! \brief Writes the register 'VO_I80_Cmd_Sram_State'. */
  1502. void GH_VO_I80_set_Cmd_Sram_State(U32 data);
  1503. /*! \brief Reads the register 'VO_I80_Cmd_Sram_State'. */
  1504. U32 GH_VO_I80_get_Cmd_Sram_State(void);
  1505. /*! \brief Writes the bit group 'sram_state' of register 'VO_I80_Cmd_Sram_State'. */
  1506. void GH_VO_I80_set_Cmd_Sram_State_sram_state(U8 data);
  1507. /*! \brief Reads the bit group 'sram_state' of register 'VO_I80_Cmd_Sram_State'. */
  1508. U8 GH_VO_I80_get_Cmd_Sram_State_sram_state(void);
  1509. /*! \brief Writes the bit group 'rd_para_num' of register 'VO_I80_Cmd_Sram_State'. */
  1510. void GH_VO_I80_set_Cmd_Sram_State_rd_para_num(U8 data);
  1511. /*! \brief Reads the bit group 'rd_para_num' of register 'VO_I80_Cmd_Sram_State'. */
  1512. U8 GH_VO_I80_get_Cmd_Sram_State_rd_para_num(void);
  1513. /*! \brief Writes the bit group 'cmd_para_num' of register 'VO_I80_Cmd_Sram_State'. */
  1514. void GH_VO_I80_set_Cmd_Sram_State_cmd_para_num(U8 data);
  1515. /*! \brief Reads the bit group 'cmd_para_num' of register 'VO_I80_Cmd_Sram_State'. */
  1516. U8 GH_VO_I80_get_Cmd_Sram_State_cmd_para_num(void);
  1517. #else /* GH_INLINE_LEVEL == 0 */
  1518. GH_INLINE void GH_VO_I80_set_Cmd_Sram_State(U32 data)
  1519. {
  1520. *(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE = data;
  1521. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1522. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Cmd_Sram_State] <-- 0x%08x\n",
  1523. REG_VO_I80_CMD_SRAM_STATE,data,data);
  1524. #endif
  1525. }
  1526. GH_INLINE U32 GH_VO_I80_get_Cmd_Sram_State(void)
  1527. {
  1528. U32 value = (*(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE);
  1529. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1530. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Cmd_Sram_State] --> 0x%08x\n",
  1531. REG_VO_I80_CMD_SRAM_STATE,value);
  1532. #endif
  1533. return value;
  1534. }
  1535. GH_INLINE void GH_VO_I80_set_Cmd_Sram_State_sram_state(U8 data)
  1536. {
  1537. GH_VO_I80_CMD_SRAM_STATE_S d;
  1538. d.all = *(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE;
  1539. d.bitc.sram_state = data;
  1540. *(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE = d.all;
  1541. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1542. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Cmd_Sram_State_sram_state] <-- 0x%08x\n",
  1543. REG_VO_I80_CMD_SRAM_STATE,d.all,d.all);
  1544. #endif
  1545. }
  1546. GH_INLINE U8 GH_VO_I80_get_Cmd_Sram_State_sram_state(void)
  1547. {
  1548. GH_VO_I80_CMD_SRAM_STATE_S tmp_value;
  1549. U32 value = (*(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE);
  1550. tmp_value.all = value;
  1551. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1552. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Cmd_Sram_State_sram_state] --> 0x%08x\n",
  1553. REG_VO_I80_CMD_SRAM_STATE,value);
  1554. #endif
  1555. return tmp_value.bitc.sram_state;
  1556. }
  1557. GH_INLINE void GH_VO_I80_set_Cmd_Sram_State_rd_para_num(U8 data)
  1558. {
  1559. GH_VO_I80_CMD_SRAM_STATE_S d;
  1560. d.all = *(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE;
  1561. d.bitc.rd_para_num = data;
  1562. *(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE = d.all;
  1563. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1564. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Cmd_Sram_State_rd_para_num] <-- 0x%08x\n",
  1565. REG_VO_I80_CMD_SRAM_STATE,d.all,d.all);
  1566. #endif
  1567. }
  1568. GH_INLINE U8 GH_VO_I80_get_Cmd_Sram_State_rd_para_num(void)
  1569. {
  1570. GH_VO_I80_CMD_SRAM_STATE_S tmp_value;
  1571. U32 value = (*(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE);
  1572. tmp_value.all = value;
  1573. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1574. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Cmd_Sram_State_rd_para_num] --> 0x%08x\n",
  1575. REG_VO_I80_CMD_SRAM_STATE,value);
  1576. #endif
  1577. return tmp_value.bitc.rd_para_num;
  1578. }
  1579. GH_INLINE void GH_VO_I80_set_Cmd_Sram_State_cmd_para_num(U8 data)
  1580. {
  1581. GH_VO_I80_CMD_SRAM_STATE_S d;
  1582. d.all = *(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE;
  1583. d.bitc.cmd_para_num = data;
  1584. *(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE = d.all;
  1585. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1586. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Cmd_Sram_State_cmd_para_num] <-- 0x%08x\n",
  1587. REG_VO_I80_CMD_SRAM_STATE,d.all,d.all);
  1588. #endif
  1589. }
  1590. GH_INLINE U8 GH_VO_I80_get_Cmd_Sram_State_cmd_para_num(void)
  1591. {
  1592. GH_VO_I80_CMD_SRAM_STATE_S tmp_value;
  1593. U32 value = (*(volatile U32 *)REG_VO_I80_CMD_SRAM_STATE);
  1594. tmp_value.all = value;
  1595. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1596. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Cmd_Sram_State_cmd_para_num] --> 0x%08x\n",
  1597. REG_VO_I80_CMD_SRAM_STATE,value);
  1598. #endif
  1599. return tmp_value.bitc.cmd_para_num;
  1600. }
  1601. #endif /* GH_INLINE_LEVEL == 0 */
  1602. /*----------------------------------------------------------------------------*/
  1603. /* register VO_I80_Tcsref_Wt_Timing (read/write) */
  1604. /*----------------------------------------------------------------------------*/
  1605. #if GH_INLINE_LEVEL == 0
  1606. /*! \brief Writes the register 'VO_I80_Tcsref_Wt_Timing'. */
  1607. void GH_VO_I80_set_Tcsref_Wt_Timing(U32 data);
  1608. /*! \brief Reads the register 'VO_I80_Tcsref_Wt_Timing'. */
  1609. U32 GH_VO_I80_get_Tcsref_Wt_Timing(void);
  1610. /*! \brief Writes the bit group 'pwcsh_wt' of register 'VO_I80_Tcsref_Wt_Timing'. */
  1611. void GH_VO_I80_set_Tcsref_Wt_Timing_pwcsh_wt(U16 data);
  1612. /*! \brief Reads the bit group 'pwcsh_wt' of register 'VO_I80_Tcsref_Wt_Timing'. */
  1613. U16 GH_VO_I80_get_Tcsref_Wt_Timing_pwcsh_wt(void);
  1614. /*! \brief Writes the bit group 'pwcsl_wt' of register 'VO_I80_Tcsref_Wt_Timing'. */
  1615. void GH_VO_I80_set_Tcsref_Wt_Timing_pwcsl_wt(U16 data);
  1616. /*! \brief Reads the bit group 'pwcsl_wt' of register 'VO_I80_Tcsref_Wt_Timing'. */
  1617. U16 GH_VO_I80_get_Tcsref_Wt_Timing_pwcsl_wt(void);
  1618. #else /* GH_INLINE_LEVEL == 0 */
  1619. GH_INLINE void GH_VO_I80_set_Tcsref_Wt_Timing(U32 data)
  1620. {
  1621. *(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING = data;
  1622. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1623. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcsref_Wt_Timing] <-- 0x%08x\n",
  1624. REG_VO_I80_TCSREF_WT_TIMING,data,data);
  1625. #endif
  1626. }
  1627. GH_INLINE U32 GH_VO_I80_get_Tcsref_Wt_Timing(void)
  1628. {
  1629. U32 value = (*(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING);
  1630. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1631. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcsref_Wt_Timing] --> 0x%08x\n",
  1632. REG_VO_I80_TCSREF_WT_TIMING,value);
  1633. #endif
  1634. return value;
  1635. }
  1636. GH_INLINE void GH_VO_I80_set_Tcsref_Wt_Timing_pwcsh_wt(U16 data)
  1637. {
  1638. GH_VO_I80_TCSREF_WT_TIMING_S d;
  1639. d.all = *(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING;
  1640. d.bitc.pwcsh_wt = data;
  1641. *(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING = d.all;
  1642. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1643. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcsref_Wt_Timing_pwcsh_wt] <-- 0x%08x\n",
  1644. REG_VO_I80_TCSREF_WT_TIMING,d.all,d.all);
  1645. #endif
  1646. }
  1647. GH_INLINE U16 GH_VO_I80_get_Tcsref_Wt_Timing_pwcsh_wt(void)
  1648. {
  1649. GH_VO_I80_TCSREF_WT_TIMING_S tmp_value;
  1650. U32 value = (*(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING);
  1651. tmp_value.all = value;
  1652. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1653. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcsref_Wt_Timing_pwcsh_wt] --> 0x%08x\n",
  1654. REG_VO_I80_TCSREF_WT_TIMING,value);
  1655. #endif
  1656. return tmp_value.bitc.pwcsh_wt;
  1657. }
  1658. GH_INLINE void GH_VO_I80_set_Tcsref_Wt_Timing_pwcsl_wt(U16 data)
  1659. {
  1660. GH_VO_I80_TCSREF_WT_TIMING_S d;
  1661. d.all = *(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING;
  1662. d.bitc.pwcsl_wt = data;
  1663. *(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING = d.all;
  1664. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1665. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcsref_Wt_Timing_pwcsl_wt] <-- 0x%08x\n",
  1666. REG_VO_I80_TCSREF_WT_TIMING,d.all,d.all);
  1667. #endif
  1668. }
  1669. GH_INLINE U16 GH_VO_I80_get_Tcsref_Wt_Timing_pwcsl_wt(void)
  1670. {
  1671. GH_VO_I80_TCSREF_WT_TIMING_S tmp_value;
  1672. U32 value = (*(volatile U32 *)REG_VO_I80_TCSREF_WT_TIMING);
  1673. tmp_value.all = value;
  1674. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1675. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcsref_Wt_Timing_pwcsl_wt] --> 0x%08x\n",
  1676. REG_VO_I80_TCSREF_WT_TIMING,value);
  1677. #endif
  1678. return tmp_value.bitc.pwcsl_wt;
  1679. }
  1680. #endif /* GH_INLINE_LEVEL == 0 */
  1681. /*----------------------------------------------------------------------------*/
  1682. /* register VO_I80_Tcsref_Rd_Timing (read/write) */
  1683. /*----------------------------------------------------------------------------*/
  1684. #if GH_INLINE_LEVEL == 0
  1685. /*! \brief Writes the register 'VO_I80_Tcsref_Rd_Timing'. */
  1686. void GH_VO_I80_set_Tcsref_Rd_Timing(U32 data);
  1687. /*! \brief Reads the register 'VO_I80_Tcsref_Rd_Timing'. */
  1688. U32 GH_VO_I80_get_Tcsref_Rd_Timing(void);
  1689. /*! \brief Writes the bit group 'pwcsh_rd' of register 'VO_I80_Tcsref_Rd_Timing'. */
  1690. void GH_VO_I80_set_Tcsref_Rd_Timing_pwcsh_rd(U16 data);
  1691. /*! \brief Reads the bit group 'pwcsh_rd' of register 'VO_I80_Tcsref_Rd_Timing'. */
  1692. U16 GH_VO_I80_get_Tcsref_Rd_Timing_pwcsh_rd(void);
  1693. /*! \brief Writes the bit group 'pwcsl_rd' of register 'VO_I80_Tcsref_Rd_Timing'. */
  1694. void GH_VO_I80_set_Tcsref_Rd_Timing_pwcsl_rd(U16 data);
  1695. /*! \brief Reads the bit group 'pwcsl_rd' of register 'VO_I80_Tcsref_Rd_Timing'. */
  1696. U16 GH_VO_I80_get_Tcsref_Rd_Timing_pwcsl_rd(void);
  1697. #else /* GH_INLINE_LEVEL == 0 */
  1698. GH_INLINE void GH_VO_I80_set_Tcsref_Rd_Timing(U32 data)
  1699. {
  1700. *(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING = data;
  1701. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1702. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcsref_Rd_Timing] <-- 0x%08x\n",
  1703. REG_VO_I80_TCSREF_RD_TIMING,data,data);
  1704. #endif
  1705. }
  1706. GH_INLINE U32 GH_VO_I80_get_Tcsref_Rd_Timing(void)
  1707. {
  1708. U32 value = (*(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING);
  1709. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1710. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcsref_Rd_Timing] --> 0x%08x\n",
  1711. REG_VO_I80_TCSREF_RD_TIMING,value);
  1712. #endif
  1713. return value;
  1714. }
  1715. GH_INLINE void GH_VO_I80_set_Tcsref_Rd_Timing_pwcsh_rd(U16 data)
  1716. {
  1717. GH_VO_I80_TCSREF_RD_TIMING_S d;
  1718. d.all = *(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING;
  1719. d.bitc.pwcsh_rd = data;
  1720. *(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING = d.all;
  1721. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1722. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcsref_Rd_Timing_pwcsh_rd] <-- 0x%08x\n",
  1723. REG_VO_I80_TCSREF_RD_TIMING,d.all,d.all);
  1724. #endif
  1725. }
  1726. GH_INLINE U16 GH_VO_I80_get_Tcsref_Rd_Timing_pwcsh_rd(void)
  1727. {
  1728. GH_VO_I80_TCSREF_RD_TIMING_S tmp_value;
  1729. U32 value = (*(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING);
  1730. tmp_value.all = value;
  1731. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1732. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcsref_Rd_Timing_pwcsh_rd] --> 0x%08x\n",
  1733. REG_VO_I80_TCSREF_RD_TIMING,value);
  1734. #endif
  1735. return tmp_value.bitc.pwcsh_rd;
  1736. }
  1737. GH_INLINE void GH_VO_I80_set_Tcsref_Rd_Timing_pwcsl_rd(U16 data)
  1738. {
  1739. GH_VO_I80_TCSREF_RD_TIMING_S d;
  1740. d.all = *(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING;
  1741. d.bitc.pwcsl_rd = data;
  1742. *(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING = d.all;
  1743. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1744. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Tcsref_Rd_Timing_pwcsl_rd] <-- 0x%08x\n",
  1745. REG_VO_I80_TCSREF_RD_TIMING,d.all,d.all);
  1746. #endif
  1747. }
  1748. GH_INLINE U16 GH_VO_I80_get_Tcsref_Rd_Timing_pwcsl_rd(void)
  1749. {
  1750. GH_VO_I80_TCSREF_RD_TIMING_S tmp_value;
  1751. U32 value = (*(volatile U32 *)REG_VO_I80_TCSREF_RD_TIMING);
  1752. tmp_value.all = value;
  1753. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1754. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Tcsref_Rd_Timing_pwcsl_rd] --> 0x%08x\n",
  1755. REG_VO_I80_TCSREF_RD_TIMING,value);
  1756. #endif
  1757. return tmp_value.bitc.pwcsl_rd;
  1758. }
  1759. #endif /* GH_INLINE_LEVEL == 0 */
  1760. /*----------------------------------------------------------------------------*/
  1761. /* register VO_I80_Todh_Timing (read/write) */
  1762. /*----------------------------------------------------------------------------*/
  1763. #if GH_INLINE_LEVEL == 0
  1764. /*! \brief Writes the register 'VO_I80_Todh_Timing'. */
  1765. void GH_VO_I80_set_Todh_Timing(U32 data);
  1766. /*! \brief Reads the register 'VO_I80_Todh_Timing'. */
  1767. U32 GH_VO_I80_get_Todh_Timing(void);
  1768. /*! \brief Writes the bit group 'todh' of register 'VO_I80_Todh_Timing'. */
  1769. void GH_VO_I80_set_Todh_Timing_todh(U16 data);
  1770. /*! \brief Reads the bit group 'todh' of register 'VO_I80_Todh_Timing'. */
  1771. U16 GH_VO_I80_get_Todh_Timing_todh(void);
  1772. #else /* GH_INLINE_LEVEL == 0 */
  1773. GH_INLINE void GH_VO_I80_set_Todh_Timing(U32 data)
  1774. {
  1775. *(volatile U32 *)REG_VO_I80_TODH_TIMING = data;
  1776. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1777. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Todh_Timing] <-- 0x%08x\n",
  1778. REG_VO_I80_TODH_TIMING,data,data);
  1779. #endif
  1780. }
  1781. GH_INLINE U32 GH_VO_I80_get_Todh_Timing(void)
  1782. {
  1783. U32 value = (*(volatile U32 *)REG_VO_I80_TODH_TIMING);
  1784. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1785. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Todh_Timing] --> 0x%08x\n",
  1786. REG_VO_I80_TODH_TIMING,value);
  1787. #endif
  1788. return value;
  1789. }
  1790. GH_INLINE void GH_VO_I80_set_Todh_Timing_todh(U16 data)
  1791. {
  1792. GH_VO_I80_TODH_TIMING_S d;
  1793. d.all = *(volatile U32 *)REG_VO_I80_TODH_TIMING;
  1794. d.bitc.todh = data;
  1795. *(volatile U32 *)REG_VO_I80_TODH_TIMING = d.all;
  1796. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1797. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Todh_Timing_todh] <-- 0x%08x\n",
  1798. REG_VO_I80_TODH_TIMING,d.all,d.all);
  1799. #endif
  1800. }
  1801. GH_INLINE U16 GH_VO_I80_get_Todh_Timing_todh(void)
  1802. {
  1803. GH_VO_I80_TODH_TIMING_S tmp_value;
  1804. U32 value = (*(volatile U32 *)REG_VO_I80_TODH_TIMING);
  1805. tmp_value.all = value;
  1806. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1807. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Todh_Timing_todh] --> 0x%08x\n",
  1808. REG_VO_I80_TODH_TIMING,value);
  1809. #endif
  1810. return tmp_value.bitc.todh;
  1811. }
  1812. #endif /* GH_INLINE_LEVEL == 0 */
  1813. /*----------------------------------------------------------------------------*/
  1814. /* register VO_I80_Lcd_State (read/write) */
  1815. /*----------------------------------------------------------------------------*/
  1816. #if GH_INLINE_LEVEL == 0
  1817. /*! \brief Writes the register 'VO_I80_Lcd_State'. */
  1818. void GH_VO_I80_set_Lcd_State(U32 data);
  1819. /*! \brief Reads the register 'VO_I80_Lcd_State'. */
  1820. U32 GH_VO_I80_get_Lcd_State(void);
  1821. /*! \brief Writes the bit group 'rdcmd_para_en' of register 'VO_I80_Lcd_State'. */
  1822. void GH_VO_I80_set_Lcd_State_rdcmd_para_en(U8 data);
  1823. /*! \brief Reads the bit group 'rdcmd_para_en' of register 'VO_I80_Lcd_State'. */
  1824. U8 GH_VO_I80_get_Lcd_State_rdcmd_para_en(void);
  1825. #else /* GH_INLINE_LEVEL == 0 */
  1826. GH_INLINE void GH_VO_I80_set_Lcd_State(U32 data)
  1827. {
  1828. *(volatile U32 *)REG_VO_I80_LCD_STATE = data;
  1829. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1830. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_State] <-- 0x%08x\n",
  1831. REG_VO_I80_LCD_STATE,data,data);
  1832. #endif
  1833. }
  1834. GH_INLINE U32 GH_VO_I80_get_Lcd_State(void)
  1835. {
  1836. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE);
  1837. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1838. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State] --> 0x%08x\n",
  1839. REG_VO_I80_LCD_STATE,value);
  1840. #endif
  1841. return value;
  1842. }
  1843. GH_INLINE void GH_VO_I80_set_Lcd_State_rdcmd_para_en(U8 data)
  1844. {
  1845. GH_VO_I80_LCD_STATE_S d;
  1846. d.all = *(volatile U32 *)REG_VO_I80_LCD_STATE;
  1847. d.bitc.rdcmd_para_en = data;
  1848. *(volatile U32 *)REG_VO_I80_LCD_STATE = d.all;
  1849. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1850. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Lcd_State_rdcmd_para_en] <-- 0x%08x\n",
  1851. REG_VO_I80_LCD_STATE,d.all,d.all);
  1852. #endif
  1853. }
  1854. GH_INLINE U8 GH_VO_I80_get_Lcd_State_rdcmd_para_en(void)
  1855. {
  1856. GH_VO_I80_LCD_STATE_S tmp_value;
  1857. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE);
  1858. tmp_value.all = value;
  1859. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1860. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State_rdcmd_para_en] --> 0x%08x\n",
  1861. REG_VO_I80_LCD_STATE,value);
  1862. #endif
  1863. return tmp_value.bitc.rdcmd_para_en;
  1864. }
  1865. #endif /* GH_INLINE_LEVEL == 0 */
  1866. /*----------------------------------------------------------------------------*/
  1867. /* register VO_I80_Lcd_State0 (read) */
  1868. /*----------------------------------------------------------------------------*/
  1869. #if GH_INLINE_LEVEL == 0
  1870. /*! \brief Reads the register 'VO_I80_Lcd_State0'. */
  1871. U32 GH_VO_I80_get_Lcd_State0(void);
  1872. /*! \brief Reads the bit group 'lcd_para1' of register 'VO_I80_Lcd_State0'. */
  1873. U16 GH_VO_I80_get_Lcd_State0_lcd_para1(void);
  1874. /*! \brief Reads the bit group 'lcd_para0' of register 'VO_I80_Lcd_State0'. */
  1875. U16 GH_VO_I80_get_Lcd_State0_lcd_para0(void);
  1876. #else /* GH_INLINE_LEVEL == 0 */
  1877. GH_INLINE U32 GH_VO_I80_get_Lcd_State0(void)
  1878. {
  1879. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE0);
  1880. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1881. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State0] --> 0x%08x\n",
  1882. REG_VO_I80_LCD_STATE0,value);
  1883. #endif
  1884. return value;
  1885. }
  1886. GH_INLINE U16 GH_VO_I80_get_Lcd_State0_lcd_para1(void)
  1887. {
  1888. GH_VO_I80_LCD_STATE0_S tmp_value;
  1889. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE0);
  1890. tmp_value.all = value;
  1891. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1892. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State0_lcd_para1] --> 0x%08x\n",
  1893. REG_VO_I80_LCD_STATE0,value);
  1894. #endif
  1895. return tmp_value.bitc.lcd_para1;
  1896. }
  1897. GH_INLINE U16 GH_VO_I80_get_Lcd_State0_lcd_para0(void)
  1898. {
  1899. GH_VO_I80_LCD_STATE0_S tmp_value;
  1900. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE0);
  1901. tmp_value.all = value;
  1902. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1903. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State0_lcd_para0] --> 0x%08x\n",
  1904. REG_VO_I80_LCD_STATE0,value);
  1905. #endif
  1906. return tmp_value.bitc.lcd_para0;
  1907. }
  1908. #endif /* GH_INLINE_LEVEL == 0 */
  1909. /*----------------------------------------------------------------------------*/
  1910. /* register VO_I80_Lcd_State1 (read) */
  1911. /*----------------------------------------------------------------------------*/
  1912. #if GH_INLINE_LEVEL == 0
  1913. /*! \brief Reads the register 'VO_I80_Lcd_State1'. */
  1914. U32 GH_VO_I80_get_Lcd_State1(void);
  1915. /*! \brief Reads the bit group 'lcd_para3' of register 'VO_I80_Lcd_State1'. */
  1916. U16 GH_VO_I80_get_Lcd_State1_lcd_para3(void);
  1917. /*! \brief Reads the bit group 'lcd_para2' of register 'VO_I80_Lcd_State1'. */
  1918. U16 GH_VO_I80_get_Lcd_State1_lcd_para2(void);
  1919. #else /* GH_INLINE_LEVEL == 0 */
  1920. GH_INLINE U32 GH_VO_I80_get_Lcd_State1(void)
  1921. {
  1922. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE1);
  1923. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1924. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State1] --> 0x%08x\n",
  1925. REG_VO_I80_LCD_STATE1,value);
  1926. #endif
  1927. return value;
  1928. }
  1929. GH_INLINE U16 GH_VO_I80_get_Lcd_State1_lcd_para3(void)
  1930. {
  1931. GH_VO_I80_LCD_STATE1_S tmp_value;
  1932. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE1);
  1933. tmp_value.all = value;
  1934. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1935. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State1_lcd_para3] --> 0x%08x\n",
  1936. REG_VO_I80_LCD_STATE1,value);
  1937. #endif
  1938. return tmp_value.bitc.lcd_para3;
  1939. }
  1940. GH_INLINE U16 GH_VO_I80_get_Lcd_State1_lcd_para2(void)
  1941. {
  1942. GH_VO_I80_LCD_STATE1_S tmp_value;
  1943. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE1);
  1944. tmp_value.all = value;
  1945. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1946. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State1_lcd_para2] --> 0x%08x\n",
  1947. REG_VO_I80_LCD_STATE1,value);
  1948. #endif
  1949. return tmp_value.bitc.lcd_para2;
  1950. }
  1951. #endif /* GH_INLINE_LEVEL == 0 */
  1952. /*----------------------------------------------------------------------------*/
  1953. /* register VO_I80_Lcd_State2 (read) */
  1954. /*----------------------------------------------------------------------------*/
  1955. #if GH_INLINE_LEVEL == 0
  1956. /*! \brief Reads the register 'VO_I80_Lcd_State2'. */
  1957. U32 GH_VO_I80_get_Lcd_State2(void);
  1958. /*! \brief Reads the bit group 'lcd_para5' of register 'VO_I80_Lcd_State2'. */
  1959. U16 GH_VO_I80_get_Lcd_State2_lcd_para5(void);
  1960. /*! \brief Reads the bit group 'lcd_para4' of register 'VO_I80_Lcd_State2'. */
  1961. U16 GH_VO_I80_get_Lcd_State2_lcd_para4(void);
  1962. #else /* GH_INLINE_LEVEL == 0 */
  1963. GH_INLINE U32 GH_VO_I80_get_Lcd_State2(void)
  1964. {
  1965. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE2);
  1966. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1967. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State2] --> 0x%08x\n",
  1968. REG_VO_I80_LCD_STATE2,value);
  1969. #endif
  1970. return value;
  1971. }
  1972. GH_INLINE U16 GH_VO_I80_get_Lcd_State2_lcd_para5(void)
  1973. {
  1974. GH_VO_I80_LCD_STATE2_S tmp_value;
  1975. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE2);
  1976. tmp_value.all = value;
  1977. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1978. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State2_lcd_para5] --> 0x%08x\n",
  1979. REG_VO_I80_LCD_STATE2,value);
  1980. #endif
  1981. return tmp_value.bitc.lcd_para5;
  1982. }
  1983. GH_INLINE U16 GH_VO_I80_get_Lcd_State2_lcd_para4(void)
  1984. {
  1985. GH_VO_I80_LCD_STATE2_S tmp_value;
  1986. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE2);
  1987. tmp_value.all = value;
  1988. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  1989. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State2_lcd_para4] --> 0x%08x\n",
  1990. REG_VO_I80_LCD_STATE2,value);
  1991. #endif
  1992. return tmp_value.bitc.lcd_para4;
  1993. }
  1994. #endif /* GH_INLINE_LEVEL == 0 */
  1995. /*----------------------------------------------------------------------------*/
  1996. /* register VO_I80_Lcd_State3 (read) */
  1997. /*----------------------------------------------------------------------------*/
  1998. #if GH_INLINE_LEVEL == 0
  1999. /*! \brief Reads the register 'VO_I80_Lcd_State3'. */
  2000. U32 GH_VO_I80_get_Lcd_State3(void);
  2001. /*! \brief Reads the bit group 'lcd_para7' of register 'VO_I80_Lcd_State3'. */
  2002. U16 GH_VO_I80_get_Lcd_State3_lcd_para7(void);
  2003. /*! \brief Reads the bit group 'lcd_para6' of register 'VO_I80_Lcd_State3'. */
  2004. U16 GH_VO_I80_get_Lcd_State3_lcd_para6(void);
  2005. #else /* GH_INLINE_LEVEL == 0 */
  2006. GH_INLINE U32 GH_VO_I80_get_Lcd_State3(void)
  2007. {
  2008. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE3);
  2009. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2010. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State3] --> 0x%08x\n",
  2011. REG_VO_I80_LCD_STATE3,value);
  2012. #endif
  2013. return value;
  2014. }
  2015. GH_INLINE U16 GH_VO_I80_get_Lcd_State3_lcd_para7(void)
  2016. {
  2017. GH_VO_I80_LCD_STATE3_S tmp_value;
  2018. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE3);
  2019. tmp_value.all = value;
  2020. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2021. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State3_lcd_para7] --> 0x%08x\n",
  2022. REG_VO_I80_LCD_STATE3,value);
  2023. #endif
  2024. return tmp_value.bitc.lcd_para7;
  2025. }
  2026. GH_INLINE U16 GH_VO_I80_get_Lcd_State3_lcd_para6(void)
  2027. {
  2028. GH_VO_I80_LCD_STATE3_S tmp_value;
  2029. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE3);
  2030. tmp_value.all = value;
  2031. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2032. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State3_lcd_para6] --> 0x%08x\n",
  2033. REG_VO_I80_LCD_STATE3,value);
  2034. #endif
  2035. return tmp_value.bitc.lcd_para6;
  2036. }
  2037. #endif /* GH_INLINE_LEVEL == 0 */
  2038. /*----------------------------------------------------------------------------*/
  2039. /* register VO_I80_Lcd_State4 (read) */
  2040. /*----------------------------------------------------------------------------*/
  2041. #if GH_INLINE_LEVEL == 0
  2042. /*! \brief Reads the register 'VO_I80_Lcd_State4'. */
  2043. U32 GH_VO_I80_get_Lcd_State4(void);
  2044. /*! \brief Reads the bit group 'lcd_para9' of register 'VO_I80_Lcd_State4'. */
  2045. U16 GH_VO_I80_get_Lcd_State4_lcd_para9(void);
  2046. /*! \brief Reads the bit group 'lcd_para8' of register 'VO_I80_Lcd_State4'. */
  2047. U16 GH_VO_I80_get_Lcd_State4_lcd_para8(void);
  2048. #else /* GH_INLINE_LEVEL == 0 */
  2049. GH_INLINE U32 GH_VO_I80_get_Lcd_State4(void)
  2050. {
  2051. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE4);
  2052. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2053. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State4] --> 0x%08x\n",
  2054. REG_VO_I80_LCD_STATE4,value);
  2055. #endif
  2056. return value;
  2057. }
  2058. GH_INLINE U16 GH_VO_I80_get_Lcd_State4_lcd_para9(void)
  2059. {
  2060. GH_VO_I80_LCD_STATE4_S tmp_value;
  2061. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE4);
  2062. tmp_value.all = value;
  2063. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2064. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State4_lcd_para9] --> 0x%08x\n",
  2065. REG_VO_I80_LCD_STATE4,value);
  2066. #endif
  2067. return tmp_value.bitc.lcd_para9;
  2068. }
  2069. GH_INLINE U16 GH_VO_I80_get_Lcd_State4_lcd_para8(void)
  2070. {
  2071. GH_VO_I80_LCD_STATE4_S tmp_value;
  2072. U32 value = (*(volatile U32 *)REG_VO_I80_LCD_STATE4);
  2073. tmp_value.all = value;
  2074. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2075. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Lcd_State4_lcd_para8] --> 0x%08x\n",
  2076. REG_VO_I80_LCD_STATE4,value);
  2077. #endif
  2078. return tmp_value.bitc.lcd_para8;
  2079. }
  2080. #endif /* GH_INLINE_LEVEL == 0 */
  2081. /*----------------------------------------------------------------------------*/
  2082. /* register VO_I80_Sram_Cmdpara (read/write) */
  2083. /*----------------------------------------------------------------------------*/
  2084. #if GH_INLINE_LEVEL == 0
  2085. /*! \brief Writes the register 'VO_I80_Sram_Cmdpara'. */
  2086. void GH_VO_I80_set_Sram_Cmdpara(U8 index, U32 data);
  2087. /*! \brief Reads the register 'VO_I80_Sram_Cmdpara'. */
  2088. U32 GH_VO_I80_get_Sram_Cmdpara(U8 index);
  2089. #else /* GH_INLINE_LEVEL == 0 */
  2090. GH_INLINE void GH_VO_I80_set_Sram_Cmdpara(U8 index, U32 data)
  2091. {
  2092. *(volatile U32 *)(REG_VO_I80_SRAM_CMDPARA + index * FIO_MOFFSET(VO_I80,0x00000004)) = data;
  2093. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2094. GH_VO_I80_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_VO_I80_set_Sram_Cmdpara] <-- 0x%08x\n",
  2095. (REG_VO_I80_SRAM_CMDPARA + index * FIO_MOFFSET(VO_I80,0x00000004)),data,data);
  2096. #endif
  2097. }
  2098. GH_INLINE U32 GH_VO_I80_get_Sram_Cmdpara(U8 index)
  2099. {
  2100. U32 value = (*(volatile U32 *)(REG_VO_I80_SRAM_CMDPARA + index * FIO_MOFFSET(VO_I80,0x00000004)));
  2101. #if GH_VO_I80_ENABLE_DEBUG_PRINT
  2102. GH_VO_I80_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_VO_I80_get_Sram_Cmdpara] --> 0x%08x\n",
  2103. (REG_VO_I80_SRAM_CMDPARA + index * FIO_MOFFSET(VO_I80,0x00000004)),value);
  2104. #endif
  2105. return value;
  2106. }
  2107. #endif /* GH_INLINE_LEVEL == 0 */
  2108. /*----------------------------------------------------------------------------*/
  2109. /* init function */
  2110. /*----------------------------------------------------------------------------*/
  2111. /*! \brief Initialises the registers and mirror variables. */
  2112. void GH_VO_I80_init(void);
  2113. #ifdef __cplusplus
  2114. }
  2115. #endif
  2116. #endif /* _GH_VO_I80_H */
  2117. /*----------------------------------------------------------------------------*/
  2118. /* end of file */
  2119. /*----------------------------------------------------------------------------*/