flexcan2_iomux_config.c 8.7 KB

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  1. /*
  2. * Copyright (c) 2012, Freescale Semiconductor, Inc.
  3. * All rights reserved.
  4. *
  5. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  6. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  7. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  8. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  9. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  10. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  11. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  12. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  13. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  14. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  15. */
  16. // File: flexcan2_iomux_config.c
  17. /* ------------------------------------------------------------------------------
  18. * <auto-generated>
  19. * This code was generated by a tool.
  20. * Runtime Version:3.4.0.0
  21. *
  22. * Changes to this file may cause incorrect behavior and will be lost if
  23. * the code is regenerated.
  24. * </auto-generated>
  25. * ------------------------------------------------------------------------------
  26. */
  27. #include "iomux_config.h"
  28. #include "registers/regsiomuxc.h"
  29. // Function to configure IOMUXC for flexcan2 module.
  30. void flexcan2_iomux_config(void)
  31. {
  32. // Config flexcan2.FLEXCAN2_RX to pad KEY_ROW4(V5)
  33. // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(0x00000000);
  34. // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(0x0001B0B0);
  35. // HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(0x00000000);
  36. // Mux Register:
  37. // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4(0x020E0268)
  38. // SION [4] - Software Input On Field Reset: DISABLED
  39. // Force the selected mux mode Input path no matter of MUX_MODE functionality.
  40. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
  41. // ENABLED (1) - Force input path of pad.
  42. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
  43. // Select iomux modes to be used for pad.
  44. // ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_RX
  45. // ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG5
  46. // ALT2 (2) - Select instance: usb signal: USB_OTG_PWR
  47. // ALT3 (3) - Select instance: kpp signal: KEY_ROW4
  48. // ALT4 (4) - Select instance: uart5 signal: UART5_CTS_B
  49. // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO15
  50. HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(
  51. BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_V(DISABLED) |
  52. BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_V(ALT0));
  53. // Pad Control Register:
  54. // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4(0x020E0650)
  55. // HYS [16] - Hysteresis Enable Field Reset: ENABLED
  56. // DISABLED (0) - CMOS input
  57. // ENABLED (1) - Schmitt trigger input
  58. // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
  59. // 100K_OHM_PD (0) - 100K Ohm Pull Down
  60. // 47K_OHM_PU (1) - 47K Ohm Pull Up
  61. // 100K_OHM_PU (2) - 100K Ohm Pull Up
  62. // 22K_OHM_PU (3) - 22K Ohm Pull Up
  63. // PUE [13] - Pull / Keep Select Field Reset: PULL
  64. // KEEP (0) - Keeper Enabled
  65. // PULL (1) - Pull Enabled
  66. // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
  67. // DISABLED (0) - Pull/Keeper Disabled
  68. // ENABLED (1) - Pull/Keeper Enabled
  69. // ODE [11] - Open Drain Enable Field Reset: DISABLED
  70. // Enables open drain of the pin.
  71. // DISABLED (0) - Output is CMOS.
  72. // ENABLED (1) - Output is Open Drain.
  73. // SPEED [7:6] - Speed Field Reset: 100MHZ
  74. // RESERVED0 (0) - Reserved
  75. // 50MHZ (1) - Low (50 MHz)
  76. // 100MHZ (2) - Medium (100 MHz)
  77. // 200MHZ (3) - Maximum (200 MHz)
  78. // DSE [5:3] - Drive Strength Field Reset: 40_OHM
  79. // HIZ (0) - HI-Z
  80. // 240_OHM (1) - 240 Ohm
  81. // 120_OHM (2) - 120 Ohm
  82. // 80_OHM (3) - 80 Ohm
  83. // 60_OHM (4) - 60 Ohm
  84. // 48_OHM (5) - 48 Ohm
  85. // 40_OHM (6) - 40 Ohm
  86. // 34_OHM (7) - 34 Ohm
  87. // SRE [0] - Slew Rate Field Reset: SLOW
  88. // Slew rate control.
  89. // SLOW (0) - Slow Slew Rate
  90. // FAST (1) - Fast Slew Rate
  91. HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(
  92. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_V(ENABLED) |
  93. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_V(100K_OHM_PU) |
  94. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_V(PULL) |
  95. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_V(ENABLED) |
  96. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_V(DISABLED) |
  97. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_V(100MHZ) |
  98. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_V(40_OHM) |
  99. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_V(SLOW));
  100. // Pad KEY_ROW4 is involved in Daisy Chain.
  101. // Input Select Register:
  102. // IOMUXC_FLEXCAN2_RX_SELECT_INPUT(0x020E07CC)
  103. // DAISY [0] - MUX Mode Select Field Reset: KEY_ROW4_ALT0
  104. // Selecting Pads Involved in Daisy Chain.
  105. // KEY_ROW4_ALT0 (0) - Select signal flexcan2 FLEXCAN2_RX as input from pad KEY_ROW4(ALT0).
  106. // SD3_DATA1_ALT2 (1) - Select signal flexcan2 FLEXCAN2_RX as input from pad SD3_DATA1(ALT2).
  107. HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(
  108. BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_V(KEY_ROW4_ALT0));
  109. // Config flexcan2.FLEXCAN2_TX to pad KEY_COL4(T6)
  110. // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(0x00000000);
  111. // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(0x0001B0B0);
  112. // Mux Register:
  113. // IOMUXC_SW_MUX_CTL_PAD_KEY_COL4(0x020E0254)
  114. // SION [4] - Software Input On Field Reset: DISABLED
  115. // Force the selected mux mode Input path no matter of MUX_MODE functionality.
  116. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
  117. // ENABLED (1) - Force input path of pad.
  118. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
  119. // Select iomux modes to be used for pad.
  120. // ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_TX
  121. // ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG4
  122. // ALT2 (2) - Select instance: usb signal: USB_OTG_OC
  123. // ALT3 (3) - Select instance: kpp signal: KEY_COL4
  124. // ALT4 (4) - Select instance: uart5 signal: UART5_RTS_B
  125. // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO14
  126. HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(
  127. BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_V(DISABLED) |
  128. BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_V(ALT0));
  129. // Pad Control Register:
  130. // IOMUXC_SW_PAD_CTL_PAD_KEY_COL4(0x020E063C)
  131. // HYS [16] - Hysteresis Enable Field Reset: ENABLED
  132. // DISABLED (0) - CMOS input
  133. // ENABLED (1) - Schmitt trigger input
  134. // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
  135. // 100K_OHM_PD (0) - 100K Ohm Pull Down
  136. // 47K_OHM_PU (1) - 47K Ohm Pull Up
  137. // 100K_OHM_PU (2) - 100K Ohm Pull Up
  138. // 22K_OHM_PU (3) - 22K Ohm Pull Up
  139. // PUE [13] - Pull / Keep Select Field Reset: PULL
  140. // KEEP (0) - Keeper Enabled
  141. // PULL (1) - Pull Enabled
  142. // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
  143. // DISABLED (0) - Pull/Keeper Disabled
  144. // ENABLED (1) - Pull/Keeper Enabled
  145. // ODE [11] - Open Drain Enable Field Reset: DISABLED
  146. // Enables open drain of the pin.
  147. // DISABLED (0) - Output is CMOS.
  148. // ENABLED (1) - Output is Open Drain.
  149. // SPEED [7:6] - Speed Field Reset: 100MHZ
  150. // RESERVED0 (0) - Reserved
  151. // 50MHZ (1) - Low (50 MHz)
  152. // 100MHZ (2) - Medium (100 MHz)
  153. // 200MHZ (3) - Maximum (200 MHz)
  154. // DSE [5:3] - Drive Strength Field Reset: 40_OHM
  155. // HIZ (0) - HI-Z
  156. // 240_OHM (1) - 240 Ohm
  157. // 120_OHM (2) - 120 Ohm
  158. // 80_OHM (3) - 80 Ohm
  159. // 60_OHM (4) - 60 Ohm
  160. // 48_OHM (5) - 48 Ohm
  161. // 40_OHM (6) - 40 Ohm
  162. // 34_OHM (7) - 34 Ohm
  163. // SRE [0] - Slew Rate Field Reset: SLOW
  164. // Slew rate control.
  165. // SLOW (0) - Slow Slew Rate
  166. // FAST (1) - Fast Slew Rate
  167. HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(
  168. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_V(ENABLED) |
  169. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_V(100K_OHM_PU) |
  170. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_V(PULL) |
  171. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_V(ENABLED) |
  172. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_V(DISABLED) |
  173. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_V(100MHZ) |
  174. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_V(40_OHM) |
  175. BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_V(SLOW));
  176. }