i2c3_iomux_config.c 9.6 KB

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  1. /*
  2. * Copyright (c) 2012, Freescale Semiconductor, Inc.
  3. * All rights reserved.
  4. *
  5. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  6. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  7. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  8. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  9. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  10. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  11. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  12. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  13. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  14. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  15. */
  16. // File: i2c3_iomux_config.c
  17. /* ------------------------------------------------------------------------------
  18. * <auto-generated>
  19. * This code was generated by a tool.
  20. * Runtime Version:3.4.0.0
  21. *
  22. * Changes to this file may cause incorrect behavior and will be lost if
  23. * the code is regenerated.
  24. * </auto-generated>
  25. * ------------------------------------------------------------------------------
  26. */
  27. #include "iomux_config.h"
  28. #include "registers/regsiomuxc.h"
  29. // Function to configure IOMUXC for i2c3 module.
  30. void i2c3_iomux_config(void)
  31. {
  32. // Config i2c3.I2C3_SCL to pad GPIO03(R7)
  33. // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(0x00000012);
  34. // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(0x0001B860);
  35. // HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(0x00000001);
  36. // Mux Register:
  37. // IOMUXC_SW_MUX_CTL_PAD_GPIO03(0x020E0228)
  38. // SION [4] - Software Input On Field Reset: DISABLED
  39. // Force the selected mux mode Input path no matter of MUX_MODE functionality.
  40. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
  41. // ENABLED (1) - Force input path of pad.
  42. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
  43. // Select iomux modes to be used for pad.
  44. // ALT0 (0) - Select instance: esai signal: ESAI_RX_HF_CLK
  45. // ALT2 (2) - Select instance: i2c3 signal: I2C3_SCL
  46. // ALT3 (3) - Select instance: xtalosc signal: XTALOSC_REF_CLK_24M
  47. // ALT4 (4) - Select instance: ccm signal: CCM_CLKO2
  48. // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO03
  49. // ALT6 (6) - Select instance: usb signal: USB_H1_OC
  50. // ALT7 (7) - Select instance: mlb signal: MLB_CLK
  51. HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(
  52. BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION_V(ENABLED) |
  53. BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE_V(ALT2));
  54. // Pad Control Register:
  55. // IOMUXC_SW_PAD_CTL_PAD_GPIO03(0x020E05F8)
  56. // HYS [16] - Hysteresis Enable Field Reset: ENABLED
  57. // DISABLED (0) - CMOS input
  58. // ENABLED (1) - Schmitt trigger input
  59. // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
  60. // 100K_OHM_PD (0) - 100K Ohm Pull Down
  61. // 47K_OHM_PU (1) - 47K Ohm Pull Up
  62. // 100K_OHM_PU (2) - 100K Ohm Pull Up
  63. // 22K_OHM_PU (3) - 22K Ohm Pull Up
  64. // PUE [13] - Pull / Keep Select Field Reset: PULL
  65. // KEEP (0) - Keeper Enabled
  66. // PULL (1) - Pull Enabled
  67. // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
  68. // DISABLED (0) - Pull/Keeper Disabled
  69. // ENABLED (1) - Pull/Keeper Enabled
  70. // ODE [11] - Open Drain Enable Field Reset: DISABLED
  71. // Enables open drain of the pin.
  72. // DISABLED (0) - Output is CMOS.
  73. // ENABLED (1) - Output is Open Drain.
  74. // SPEED [7:6] - Speed Field Reset: 100MHZ
  75. // RESERVED0 (0) - Reserved
  76. // 50MHZ (1) - Low (50 MHz)
  77. // 100MHZ (2) - Medium (100 MHz)
  78. // 200MHZ (3) - Maximum (200 MHz)
  79. // DSE [5:3] - Drive Strength Field Reset: 40_OHM
  80. // HIZ (0) - HI-Z
  81. // 240_OHM (1) - 240 Ohm
  82. // 120_OHM (2) - 120 Ohm
  83. // 80_OHM (3) - 80 Ohm
  84. // 60_OHM (4) - 60 Ohm
  85. // 48_OHM (5) - 48 Ohm
  86. // 40_OHM (6) - 40 Ohm
  87. // 34_OHM (7) - 34 Ohm
  88. // SRE [0] - Slew Rate Field Reset: SLOW
  89. // Slew rate control.
  90. // SLOW (0) - Slow Slew Rate
  91. // FAST (1) - Fast Slew Rate
  92. HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(
  93. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS_V(ENABLED) |
  94. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS_V(100K_OHM_PU) |
  95. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE_V(PULL) |
  96. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE_V(ENABLED) |
  97. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE_V(ENABLED) |
  98. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED_V(50MHZ) |
  99. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE_V(60_OHM) |
  100. BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE_V(SLOW));
  101. // Pad GPIO03 is involved in Daisy Chain.
  102. // Input Select Register:
  103. // IOMUXC_I2C3_SCL_IN_SELECT_INPUT(0x020E0878)
  104. // DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA17_ALT6
  105. // Selecting Pads Involved in Daisy Chain.
  106. // EIM_DATA17_ALT6 (0) - Select signal i2c3 I2C3_SCL as input from pad EIM_DATA17(ALT6).
  107. // GPIO03_ALT2 (1) - Select signal i2c3 I2C3_SCL as input from pad GPIO03(ALT2).
  108. // GPIO05_ALT6 (2) - Select signal i2c3 I2C3_SCL as input from pad GPIO05(ALT6).
  109. HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(
  110. BF_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY_V(GPIO03_ALT2));
  111. // Config i2c3.I2C3_SDA to pad EIM_DATA18(D24)
  112. // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(0x00000016);
  113. // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(0x0001B860);
  114. // HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(0x00000000);
  115. // Mux Register:
  116. // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18(0x020E014C)
  117. // SION [4] - Software Input On Field Reset: DISABLED
  118. // Force the selected mux mode Input path no matter of MUX_MODE functionality.
  119. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
  120. // ENABLED (1) - Force input path of pad.
  121. // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
  122. // Select iomux modes to be used for pad.
  123. // ALT0 (0) - Select instance: eim signal: EIM_DATA18
  124. // ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MOSI
  125. // ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN07
  126. // ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA17
  127. // ALT4 (4) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
  128. // ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO18
  129. // ALT6 (6) - Select instance: i2c3 signal: I2C3_SDA
  130. // ALT8 (8) - Select instance: epdc signal: EPDC_VCOM1
  131. HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(
  132. BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION_V(ENABLED) |
  133. BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE_V(ALT6));
  134. // Pad Control Register:
  135. // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18(0x020E051C)
  136. // HYS [16] - Hysteresis Enable Field Reset: ENABLED
  137. // DISABLED (0) - CMOS input
  138. // ENABLED (1) - Schmitt trigger input
  139. // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
  140. // 100K_OHM_PD (0) - 100K Ohm Pull Down
  141. // 47K_OHM_PU (1) - 47K Ohm Pull Up
  142. // 100K_OHM_PU (2) - 100K Ohm Pull Up
  143. // 22K_OHM_PU (3) - 22K Ohm Pull Up
  144. // PUE [13] - Pull / Keep Select Field Reset: PULL
  145. // KEEP (0) - Keeper Enabled
  146. // PULL (1) - Pull Enabled
  147. // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
  148. // DISABLED (0) - Pull/Keeper Disabled
  149. // ENABLED (1) - Pull/Keeper Enabled
  150. // ODE [11] - Open Drain Enable Field Reset: DISABLED
  151. // Enables open drain of the pin.
  152. // DISABLED (0) - Output is CMOS.
  153. // ENABLED (1) - Output is Open Drain.
  154. // SPEED [7:6] - Speed Field Reset: 100MHZ
  155. // RESERVED0 (0) - Reserved
  156. // 50MHZ (1) - Low (50 MHz)
  157. // 100MHZ (2) - Medium (100 MHz)
  158. // 200MHZ (3) - Maximum (200 MHz)
  159. // DSE [5:3] - Drive Strength Field Reset: 40_OHM
  160. // HIZ (0) - HI-Z
  161. // 240_OHM (1) - 240 Ohm
  162. // 120_OHM (2) - 120 Ohm
  163. // 80_OHM (3) - 80 Ohm
  164. // 60_OHM (4) - 60 Ohm
  165. // 48_OHM (5) - 48 Ohm
  166. // 40_OHM (6) - 40 Ohm
  167. // 34_OHM (7) - 34 Ohm
  168. // SRE [0] - Slew Rate Field Reset: SLOW
  169. // Slew rate control.
  170. // SLOW (0) - Slow Slew Rate
  171. // FAST (1) - Fast Slew Rate
  172. HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(
  173. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS_V(ENABLED) |
  174. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS_V(100K_OHM_PU) |
  175. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE_V(PULL) |
  176. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE_V(ENABLED) |
  177. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE_V(ENABLED) |
  178. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED_V(50MHZ) |
  179. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE_V(60_OHM) |
  180. BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE_V(SLOW));
  181. // Pad EIM_DATA18 is involved in Daisy Chain.
  182. // Input Select Register:
  183. // IOMUXC_I2C3_SDA_IN_SELECT_INPUT(0x020E087C)
  184. // DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA18_ALT6
  185. // Selecting Pads Involved in Daisy Chain.
  186. // EIM_DATA18_ALT6 (0) - Select signal i2c3 I2C3_SDA as input from pad EIM_DATA18(ALT6).
  187. // GPIO16_ALT6 (1) - Select signal i2c3 I2C3_SDA as input from pad GPIO16(ALT6).
  188. // GPIO06_ALT2 (2) - Select signal i2c3 I2C3_SDA as input from pad GPIO06(ALT2).
  189. HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(
  190. BF_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY_V(EIM_DATA18_ALT6));
  191. }