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imx6ul-pinfunc.h

imx6ul-pinfunc.h 99 KB
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  1. /*
    2. 

  2.  * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License version 2 as
    6. 

  6.  * published by the Free Software Foundation.
    7. 

  7.  *
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __DTS_IMX6UL_PINFUNC_H
    11. 

  11. #define __DTS_IMX6UL_PINFUNC_H
    12. 

  12. 

  13. #define PIN_CFG(mux_ctl_offset, pad_ctl_offset, select_input_offset, mux_mode, daisy, pad_setting) \
    14. 

  14. 	do {\
    15. 

  15. 		writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\
    16. 

  16. 		if (select_input_offset != 0)\
    17. 

  17. 			writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\
    18. 

  18. 		writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\
    19. 

  19. 	} while(0);
    20. 

  20. 

  21. /*
    22. 

  22.  * The pin function ID is a tuple of
    23. 

  23.  * <mux_reg conf_reg input_reg mux_mode input_val>
    24. 

  24.  */
    25. 

  25. #define MX6UL_PAD_JTAG_MOD__SJC_MOD(p)                               PIN_CFG(0x0044, 0x02D0, 0x0000, 0x0, 0x0, p)
    26. 

  26. #define MX6UL_PAD_JTAG_MOD__GPT2_CLK(p)                              PIN_CFG(0x0044, 0x02D0, 0x05A0, 0x1, 0x0, p)
    27. 

  27. #define MX6UL_PAD_JTAG_MOD__SPDIF_OUT(p)                             PIN_CFG(0x0044, 0x02D0, 0x0000, 0x2, 0x0, p)
    28. 

  28. #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M(p)                     PIN_CFG(0x0044, 0x02D0, 0x0000, 0x3, 0x0, p)
    29. 

  29. #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY(p)                          PIN_CFG(0x0044, 0x02D0, 0x04C0, 0x4, 0x0, p)
    30. 

  30. #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10(p)                            PIN_CFG(0x0044, 0x02D0, 0x0000, 0x5, 0x0, p)
    31. 

  31. #define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00(p)                      PIN_CFG(0x0044, 0x02D0, 0x0000, 0x6, 0x0, p)
    32. 

  32. #define MX6UL_PAD_JTAG_TMS__SJC_TMS(p)                               PIN_CFG(0x0048, 0x02D4, 0x0000, 0x0, 0x0, p)
    33. 

  33. #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1(p)                         PIN_CFG(0x0048, 0x02D4, 0x0598, 0x1, 0x0, p)
    34. 

  34. #define MX6UL_PAD_JTAG_TMS__SAI2_MCLK(p)                             PIN_CFG(0x0048, 0x02D4, 0x0000, 0x2, 0x0, p)
    35. 

  35. #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1(p)                             PIN_CFG(0x0048, 0x02D4, 0x0000, 0x3, 0x0, p)
    36. 

  36. #define MX6UL_PAD_JTAG_TMS__CCM_WAIT(p)                              PIN_CFG(0x0048, 0x02D4, 0x0000, 0x4, 0x0, p)
    37. 

  37. #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11(p)                            PIN_CFG(0x0048, 0x02D4, 0x0000, 0x5, 0x0, p)
    38. 

  38. #define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01(p)                      PIN_CFG(0x0048, 0x02D4, 0x0000, 0x6, 0x0, p)
    39. 

  39. #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT(p)                             PIN_CFG(0x0048, 0x02D4, 0x0000, 0x8, 0x0, p)
    40. 

  40. #define MX6UL_PAD_JTAG_TDO__SJC_TDO(p)                               PIN_CFG(0x004C, 0x02D8, 0x0000, 0x0, 0x0, p)
    41. 

  41. #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2(p)                         PIN_CFG(0x004C, 0x02D8, 0x059C, 0x1, 0x0, p)
    42. 

  42. #define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC(p)                          PIN_CFG(0x004C, 0x02D8, 0x05FC, 0x2, 0x0, p)
    43. 

  43. #define MX6UL_PAD_JTAG_TDO__CCM_CLKO2(p)                             PIN_CFG(0x004C, 0x02D8, 0x0000, 0x3, 0x0, p)
    44. 

  44. #define MX6UL_PAD_JTAG_TDO__CCM_STOP(p)                              PIN_CFG(0x004C, 0x02D8, 0x0000, 0x4, 0x0, p)
    45. 

  45. #define MX6UL_PAD_JTAG_TDO__GPIO1_IO12(p)                            PIN_CFG(0x004C, 0x02D8, 0x0000, 0x5, 0x0, p)
    46. 

  46. #define MX6UL_PAD_JTAG_TDO__MQS_RIGHT(p)                             PIN_CFG(0x004C, 0x02D8, 0x0000, 0x6, 0x0, p)
    47. 

  47. #define MX6UL_PAD_JTAG_TDO__EPIT2_OUT(p)                             PIN_CFG(0x004C, 0x02D8, 0x0000, 0x8, 0x0, p)
    48. 

  48. #define MX6UL_PAD_JTAG_TDI__SJC_TDI(p)                               PIN_CFG(0x0050, 0x02DC, 0x0000, 0x0, 0x0, p)
    49. 

  49. #define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1(p)                         PIN_CFG(0x0050, 0x02DC, 0x0000, 0x1, 0x0, p)
    50. 

  50. #define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK(p)                          PIN_CFG(0x0050, 0x02DC, 0x05F8, 0x2, 0x0, p)
    51. 

  51. #define MX6UL_PAD_JTAG_TDI__PWM6_OUT(p)                              PIN_CFG(0x0050, 0x02DC, 0x0000, 0x4, 0x0, p)
    52. 

  52. #define MX6UL_PAD_JTAG_TDI__GPIO1_IO13(p)                            PIN_CFG(0x0050, 0x02DC, 0x0000, 0x5, 0x0, p)
    53. 

  53. #define MX6UL_PAD_JTAG_TDI__MQS_LEFT(p)                              PIN_CFG(0x0050, 0x02DC, 0x0000, 0x6, 0x0, p)
    54. 

  54. #define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL(p)                       PIN_CFG(0x0050, 0x02DC, 0x0000, 0x8, 0x0, p)
    55. 

  55. #define MX6UL_PAD_JTAG_TCK__SJC_TCK(p)                               PIN_CFG(0x0054, 0x02E0, 0x0000, 0x0, 0x0, p)
    56. 

  56. #define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2(p)                         PIN_CFG(0x0054, 0x02E0, 0x0000, 0x1, 0x0, p)
    57. 

  57. #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA(p)                          PIN_CFG(0x0054, 0x02E0, 0x0000, 0x2, 0x0, p)
    58. 

  58. #define MX6UL_PAD_JTAG_TCK__PWM7_OUT(p)                              PIN_CFG(0x0054, 0x02E0, 0x0000, 0x4, 0x0, p)
    59. 

  59. #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14(p)                            PIN_CFG(0x0054, 0x02E0, 0x0000, 0x5, 0x0, p)
    60. 

  60. #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL(p)                       PIN_CFG(0x0054, 0x02E0, 0x0000, 0x8, 0x0, p)
    61. 

  61. #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB(p)                          PIN_CFG(0x0058, 0x02E4, 0x0000, 0x0, 0x0, p)
    62. 

  62. #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3(p)                      PIN_CFG(0x0058, 0x02E4, 0x0000, 0x1, 0x0, p)
    63. 

  63. #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA(p)                       PIN_CFG(0x0058, 0x02E4, 0x0000, 0x2, 0x0, p)
    64. 

  64. #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT(p)                           PIN_CFG(0x0058, 0x02E4, 0x0000, 0x4, 0x0, p)
    65. 

  65. #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15(p)                         PIN_CFG(0x0058, 0x02E4, 0x0000, 0x5, 0x0, p)
    66. 

  66. #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS(p)                   PIN_CFG(0x0058, 0x02E4, 0x0000, 0x8, 0x0, p)
    67. 

  67. #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL(p)                            PIN_CFG(0x005C, 0x02E8, 0x05AC, 0x0, 0x1, p)
    68. 

  68. #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1(p)                       PIN_CFG(0x005C, 0x02E8, 0x058C, 0x1, 0x0, p)
    69. 

  69. #define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID(p)                      PIN_CFG(0x005C, 0x02E8, 0x04B8, 0x2, 0x0, p)
    70. 

  70. #define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1(p)                      PIN_CFG(0x005C, 0x02E8, 0x0574, 0x3, 0x0, p)
    71. 

  71. #define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT(p)                           PIN_CFG(0x005C, 0x02E8, 0x0000, 0x4, 0x0, p)
    72. 

  72. #define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00(p)                          PIN_CFG(0x005C, 0x02E8, 0x0000, 0x5, 0x0, p)
    73. 

  73. #define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN(p)                PIN_CFG(0x005C, 0x02E8, 0x0000, 0x6, 0x0, p)
    74. 

  74. #define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET(p)                    PIN_CFG(0x005C, 0x02E8, 0x0000, 0x7, 0x0, p)
    75. 

  75. #define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B(p)                        PIN_CFG(0x005C, 0x02E8, 0x0000, 0x8, 0x0, p)
    76. 

  76. #define MX6UL_PAD_GPIO1_IO01__I2C2_SDA(p)                            PIN_CFG(0x0060, 0x02EC, 0x05B0, 0x0, 0x1, p)
    77. 

  77. #define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1(p)                       PIN_CFG(0x0060, 0x02EC, 0x0000, 0x1, 0x0, p)
    78. 

  78. #define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC(p)                         PIN_CFG(0x0060, 0x02EC, 0x0664, 0x2, 0x0, p)
    79. 

  79. #define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2(p)                      PIN_CFG(0x0060, 0x02EC, 0x057C, 0x3, 0x0, p)
    80. 

  80. #define MX6UL_PAD_GPIO1_IO01__MQS_LEFT(p)                            PIN_CFG(0x0060, 0x02EC, 0x0000, 0x4, 0x0, p)
    81. 

  81. #define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01(p)                          PIN_CFG(0x0060, 0x02EC, 0x0000, 0x5, 0x0, p)
    82. 

  82. #define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT(p)               PIN_CFG(0x0060, 0x02EC, 0x0000, 0x6, 0x0, p)
    83. 

  83. #define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET(p)                     PIN_CFG(0x0060, 0x02EC, 0x0000, 0x7, 0x0, p)
    84. 

  84. #define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B(p)                        PIN_CFG(0x0060, 0x02EC, 0x0000, 0x8, 0x0, p)
    85. 

  85. #define MX6UL_PAD_GPIO1_IO02__I2C1_SCL(p)                            PIN_CFG(0x0064, 0x02F0, 0x05A4, 0x0, 0x0, p)
    86. 

  86. #define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2(p)                       PIN_CFG(0x0064, 0x02F0, 0x0000, 0x1, 0x0, p)
    87. 

  87. #define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR(p)                        PIN_CFG(0x0064, 0x02F0, 0x0000, 0x2, 0x0, p)
    88. 

  88. #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M(p)                   PIN_CFG(0x0064, 0x02F0, 0x0000, 0x3, 0x0, p)
    89. 

  89. #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP(p)                           PIN_CFG(0x0064, 0x02F0, 0x066C, 0x4, 0x0, p)
    90. 

  90. #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02(p)                          PIN_CFG(0x0064, 0x02F0, 0x0000, 0x5, 0x0, p)
    91. 

  91. #define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00(p)                    PIN_CFG(0x0064, 0x02F0, 0x0000, 0x6, 0x0, p)
    92. 

  92. #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET(p)                    PIN_CFG(0x0064, 0x02F0, 0x0000, 0x7, 0x0, p)
    93. 

  93. #define MX6UL_PAD_GPIO1_IO02__UART1_TX(p)                            PIN_CFG(0x0064, 0x02F0, 0x0000, 0x8, 0x0, p)
    94. 

  94. #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA(p)                            PIN_CFG(0x0068, 0x02F4, 0x05A8, 0x0, 0x1, p)
    95. 

  95. #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3(p)                       PIN_CFG(0x0068, 0x02F4, 0x0000, 0x1, 0x0, p)
    96. 

  96. #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC(p)                         PIN_CFG(0x0068, 0x02F4, 0x0660, 0x2, 0x0, p)
    97. 

  97. #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B(p)                         PIN_CFG(0x0068, 0x02F4, 0x0668, 0x4, 0x0, p)
    98. 

  98. #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03(p)                          PIN_CFG(0x0068, 0x02F4, 0x0000, 0x5, 0x0, p)
    99. 

  99. #define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK(p)                     PIN_CFG(0x0068, 0x02F4, 0x0000, 0x6, 0x0, p)
    100. 

  100. #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK(p)                      PIN_CFG(0x0068, 0x02F4, 0x0000, 0x7, 0x0, p)
    101. 

  101. #define MX6UL_PAD_GPIO1_IO03__UART1_RX(p)                            PIN_CFG(0x0068, 0x02F4, 0x0000, 0x8, 0x0, p)
    102. 

  102. #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1(p)                      PIN_CFG(0x006C, 0x02F8, 0x0574, 0x0, 0x1, p)
    103. 

  103. #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT(p)                            PIN_CFG(0x006C, 0x02F8, 0x0000, 0x1, 0x0, p)
    104. 

  104. #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR(p)                        PIN_CFG(0x006C, 0x02F8, 0x0000, 0x2, 0x0, p)
    105. 

  105. #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B(p)                      PIN_CFG(0x006C, 0x02F8, 0x0000, 0x4, 0x0, p)
    106. 

  106. #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04(p)                          PIN_CFG(0x006C, 0x02F8, 0x0000, 0x5, 0x0, p)
    107. 

  107. #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN(p)                PIN_CFG(0x006C, 0x02F8, 0x0000, 0x6, 0x0, p)
    108. 

  108. #define MX6UL_PAD_GPIO1_IO04__UART5_TX(p)                            PIN_CFG(0x006C, 0x02F8, 0x0000, 0x8, 0x0, p)
    109. 

  109. #define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2(p)                      PIN_CFG(0x0070, 0x02FC, 0x057C, 0x0, 0x1, p)
    110. 

  110. #define MX6UL_PAD_GPIO1_IO05__PWM4_OUT(p)                            PIN_CFG(0x0070, 0x02FC, 0x0000, 0x1, 0x0, p)
    111. 

  111. #define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID(p)                      PIN_CFG(0x0070, 0x02FC, 0x04BC, 0x2, 0x0, p)
    112. 

  112. #define MX6UL_PAD_GPIO1_IO05__CSI_FIELD(p)                           PIN_CFG(0x0070, 0x02FC, 0x0530, 0x3, 0x0, p)
    113. 

  113. #define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT(p)                      PIN_CFG(0x0070, 0x02FC, 0x0000, 0x4, 0x0, p)
    114. 

  114. #define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05(p)                          PIN_CFG(0x0070, 0x02FC, 0x0000, 0x5, 0x0, p)
    115. 

  115. #define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT(p)               PIN_CFG(0x0070, 0x02FC, 0x0000, 0x6, 0x0, p)
    116. 

  116. #define MX6UL_PAD_GPIO1_IO05__UART5_RX(p)                            PIN_CFG(0x0070, 0x02FC, 0x0000, 0x8, 0x0, p)
    117. 

  117. #define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO(p)                          PIN_CFG(0x0074, 0x0300, 0x0578, 0x0, 0x0, p)
    118. 

  118. #define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO(p)                          PIN_CFG(0x0074, 0x0300, 0x0580, 0x1, 0x0, p)
    119. 

  119. #define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE(p)                    PIN_CFG(0x0074, 0x0300, 0x0000, 0x2, 0x0, p)
    120. 

  120. #define MX6UL_PAD_GPIO1_IO06__CSI_MCLK(p)                            PIN_CFG(0x0074, 0x0300, 0x0000, 0x3, 0x0, p)
    121. 

  121. #define MX6UL_PAD_GPIO1_IO06__USDHC2_WP(p)                           PIN_CFG(0x0074, 0x0300, 0x069C, 0x4, 0x0, p)
    122. 

  122. #define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06(p)                          PIN_CFG(0x0074, 0x0300, 0x0000, 0x5, 0x0, p)
    123. 

  123. #define MX6UL_PAD_GPIO1_IO06__CCM_WAIT(p)                            PIN_CFG(0x0074, 0x0300, 0x0000, 0x6, 0x0, p)
    124. 

  124. #define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B(p)                        PIN_CFG(0x0074, 0x0300, 0x0000, 0x7, 0x0, p)
    125. 

  125. #define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS(p)                       PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p)
    126. 

  126. #define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS(p)                       PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p)
    127. 

  127. #define MX6UL_PAD_GPIO1_IO07__ENET1_MDC(p)                           PIN_CFG(0x0078, 0x0304, 0x0000, 0x0, 0x0, p)
    128. 

  128. #define MX6UL_PAD_GPIO1_IO07__ENET2_MDC(p)                           PIN_CFG(0x0078, 0x0304, 0x0000, 0x1, 0x0, p)
    129. 

  129. #define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE(p)                   PIN_CFG(0x0078, 0x0304, 0x0000, 0x2, 0x0, p)
    130. 

  130. #define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK(p)                          PIN_CFG(0x0078, 0x0304, 0x0528, 0x3, 0x0, p)
    131. 

  131. #define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B(p)                         PIN_CFG(0x0078, 0x0304, 0x0674, 0x4, 0x1, p)
    132. 

  132. #define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07(p)                          PIN_CFG(0x0078, 0x0304, 0x0000, 0x5, 0x0, p)
    133. 

  133. #define MX6UL_PAD_GPIO1_IO07__CCM_STOP(p)                            PIN_CFG(0x0078, 0x0304, 0x0000, 0x6, 0x0, p)
    134. 

  134. #define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS(p)                       PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p)
    135. 

  135. #define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS(p)                       PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p)
    136. 

  136. #define MX6UL_PAD_GPIO1_IO08__PWM1_OUT(p)                            PIN_CFG(0x007C, 0x0308, 0x0000, 0x0, 0x0, p)
    137. 

  137. #define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B(p)                        PIN_CFG(0x007C, 0x0308, 0x0000, 0x1, 0x0, p)
    138. 

  138. #define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT(p)                           PIN_CFG(0x007C, 0x0308, 0x0000, 0x2, 0x0, p)
    139. 

  139. #define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC(p)                           PIN_CFG(0x007C, 0x0308, 0x052C, 0x3, 0x1, p)
    140. 

  140. #define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT(p)                      PIN_CFG(0x007C, 0x0308, 0x0000, 0x4, 0x0, p)
    141. 

  141. #define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08(p)                          PIN_CFG(0x007C, 0x0308, 0x0000, 0x5, 0x0, p)
    142. 

  142. #define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY(p)                        PIN_CFG(0x007C, 0x0308, 0x04C0, 0x6, 0x1, p)
    143. 

  143. #define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS(p)                       PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p)
    144. 

  144. #define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS(p)                       PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p)
    145. 

  145. #define MX6UL_PAD_GPIO1_IO09__PWM2_OUT(p)                            PIN_CFG(0x0080, 0x030C, 0x0000, 0x0, 0x0, p)
    146. 

  146. #define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY(p)                      PIN_CFG(0x0080, 0x030C, 0x0000, 0x1, 0x0, p)
    147. 

  147. #define MX6UL_PAD_GPIO1_IO09__SPDIF_IN(p)                            PIN_CFG(0x0080, 0x030C, 0x0618, 0x2, 0x0, p)
    148. 

  148. #define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC(p)                           PIN_CFG(0x0080, 0x030C, 0x0524, 0x3, 0x1, p)
    149. 

  149. #define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B(p)                      PIN_CFG(0x0080, 0x030C, 0x0000, 0x4, 0x0, p)
    150. 

  150. #define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09(p)                          PIN_CFG(0x0080, 0x030C, 0x0000, 0x5, 0x0, p)
    151. 

  151. #define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B(p)                      PIN_CFG(0x0080, 0x030C, 0x0000, 0x6, 0x0, p)
    152. 

  152. #define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS(p)                       PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p)
    153. 

  153. #define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS(p)                       PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p)
    154. 

  154. #define MX6UL_PAD_UART1_TX_DATA__UART1_TX(p)                         PIN_CFG(0x0084, 0x0310, 0x0624, 0x0, 0x2, p)
    155. 

  155. #define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02(p)                    PIN_CFG(0x0084, 0x0310, 0x0000, 0x1, 0x0, p)
    156. 

  156. #define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL(p)                         PIN_CFG(0x0084, 0x0310, 0x05B4, 0x2, 0x0, p)
    157. 

  157. #define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02(p)                       PIN_CFG(0x0084, 0x0310, 0x0000, 0x3, 0x0, p)
    158. 

  158. #define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1(p)                    PIN_CFG(0x0084, 0x0310, 0x0000, 0x4, 0x0, p)
    159. 

  159. #define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16(p)                       PIN_CFG(0x0084, 0x0310, 0x0000, 0x5, 0x0, p)
    160. 

  160. #define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT(p)                        PIN_CFG(0x0084, 0x0310, 0x0000, 0x8, 0x0, p)
    161. 

  161. #define MX6UL_PAD_UART1_RX_DATA__UART1_RX(p)                         PIN_CFG(0x0088, 0x0314, 0x0624, 0x0, 0x3, p)
    162. 

  162. #define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03(p)                    PIN_CFG(0x0088, 0x0314, 0x0000, 0x1, 0x0, p)
    163. 

  163. #define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA(p)                         PIN_CFG(0x0088, 0x0314, 0x05B8, 0x2, 0x0, p)
    164. 

  164. #define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03(p)                       PIN_CFG(0x0088, 0x0314, 0x0000, 0x3, 0x0, p)
    165. 

  165. #define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK(p)                         PIN_CFG(0x0088, 0x0314, 0x0594, 0x4, 0x0, p)
    166. 

  166. #define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17(p)                       PIN_CFG(0x0088, 0x0314, 0x0000, 0x5, 0x0, p)
    167. 

  167. #define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN(p)                         PIN_CFG(0x0088, 0x0314, 0x0000, 0x8, 0x0, p)
    168. 

  168. #define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS(p)                      PIN_CFG(0x008C, 0x0318, 0x0000, 0x0, 0x0, p)
    169. 

  169. #define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS(p)                      PIN_CFG(0x008C, 0x0318, 0x0620, 0x0, 0x2, p)
    170. 

  170. #define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK(p)                       PIN_CFG(0x008C, 0x0318, 0x0000, 0x1, 0x0, p)
    171. 

  171. #define MX6UL_PAD_UART1_CTS_B__USDHC1_WP(p)                          PIN_CFG(0x008C, 0x0318, 0x066C, 0x2, 0x1, p)
    172. 

  172. #define MX6UL_PAD_UART1_CTS_B__CSI_DATA04(p)                         PIN_CFG(0x008C, 0x0318, 0x0000, 0x3, 0x0, p)
    173. 

  173. #define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN(p)               PIN_CFG(0x008C, 0x0318, 0x0000, 0x4, 0x0, p)
    174. 

  174. #define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18(p)                         PIN_CFG(0x008C, 0x0318, 0x0000, 0x5, 0x0, p)
    175. 

  175. #define MX6UL_PAD_UART1_CTS_B__USDHC2_WP(p)                          PIN_CFG(0x008C, 0x0318, 0x0000, 0x8, 0x0, p)
    176. 

  176. #define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS(p)                      PIN_CFG(0x0090, 0x031C, 0x0620, 0x0, 0x3, p)
    177. 

  177. #define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS(p)                      PIN_CFG(0x0090, 0x031C, 0x0000, 0x0, 0x0, p)
    178. 

  178. #define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER(p)                        PIN_CFG(0x0090, 0x031C, 0x0000, 0x1, 0x0, p)
    179. 

  179. #define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B(p)                        PIN_CFG(0x0090, 0x031C, 0x0668, 0x2, 0x1, p)
    180. 

  180. #define MX6UL_PAD_UART1_RTS_B__CSI_DATA05(p)                         PIN_CFG(0x0090, 0x031C, 0x0000, 0x3, 0x0, p)
    181. 

  181. #define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT(p)              PIN_CFG(0x0090, 0x031C, 0x0000, 0x4, 0x0, p)
    182. 

  182. #define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19(p)                         PIN_CFG(0x0090, 0x031C, 0x0000, 0x5, 0x0, p)
    183. 

  183. #define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B(p)                        PIN_CFG(0x0090, 0x031C, 0x0000, 0x8, 0x0, p)
    184. 

  184. #define MX6UL_PAD_UART2_TX_DATA__UART2_TX(p)                         PIN_CFG(0x0094, 0x0320, 0x062C, 0x0, 0x0, p)
    185. 

  185. #define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02(p)                    PIN_CFG(0x0094, 0x0320, 0x0000, 0x1, 0x0, p)
    186. 

  186. #define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL(p)                         PIN_CFG(0x0094, 0x0320, 0x05BC, 0x2, 0x0, p)
    187. 

  187. #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06(p)                       PIN_CFG(0x0094, 0x0320, 0x0000, 0x3, 0x0, p)
    188. 

  188. #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1(p)                    PIN_CFG(0x0094, 0x0320, 0x058C, 0x4, 0x1, p)
    189. 

  189. #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20(p)                       PIN_CFG(0x0094, 0x0320, 0x0000, 0x5, 0x0, p)
    190. 

  190. #define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0(p)                       PIN_CFG(0x0094, 0x0320, 0x0000, 0x8, 0x0, p)
    191. 

  191. #define MX6UL_PAD_UART2_RX_DATA__UART2_RX(p)                         PIN_CFG(0x0098, 0x0324, 0x062C, 0x0, 0x1, p)
    192. 

  192. #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03(p)                    PIN_CFG(0x0098, 0x0324, 0x0000, 0x1, 0x0, p)
    193. 

  193. #define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA(p)                         PIN_CFG(0x0098, 0x0324, 0x05C0, 0x2, 0x0, p)
    194. 

  194. #define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07(p)                       PIN_CFG(0x0098, 0x0324, 0x0000, 0x3, 0x0, p)
    195. 

  195. #define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2(p)                    PIN_CFG(0x0098, 0x0324, 0x0590, 0x4, 0x0, p)
    196. 

  196. #define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21(p)                       PIN_CFG(0x0098, 0x0324, 0x0000, 0x5, 0x0, p)
    197. 

  197. #define MX6UL_PAD_UART2_RX_DATA__SJC_DONE(p)                         PIN_CFG(0x0098, 0x0324, 0x0000, 0x7, 0x0, p)
    198. 

  198. #define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK(p)                      PIN_CFG(0x0098, 0x0324, 0x0000, 0x8, 0x0, p)
    199. 

  199. #define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS(p)                      PIN_CFG(0x009C, 0x0328, 0x0000, 0x0, 0x0, p)
    200. 

  200. #define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS(p)                      PIN_CFG(0x009C, 0x0328, 0x0628, 0x0, 0x0, p)
    201. 

  201. #define MX6UL_PAD_UART2_CTS_B__ENET1_CRS(p)                          PIN_CFG(0x009C, 0x0328, 0x0000, 0x1, 0x0, p)
    202. 

  202. #define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX(p)                        PIN_CFG(0x009C, 0x0328, 0x0000, 0x12, 0x0, p)
    203. 

  203. #define MX6UL_PAD_UART2_CTS_B__CSI_DATA08(p)                         PIN_CFG(0x009C, 0x0328, 0x0000, 0x3, 0x0, p)
    204. 

  204. #define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2(p)                      PIN_CFG(0x009C, 0x0328, 0x0000, 0x4, 0x0, p)
    205. 

  205. #define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22(p)                         PIN_CFG(0x009C, 0x0328, 0x0000, 0x5, 0x0, p)
    206. 

  206. #define MX6UL_PAD_UART2_CTS_B__SJC_DE_B(p)                           PIN_CFG(0x009C, 0x0328, 0x0000, 0x7, 0x0, p)
    207. 

  207. #define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI(p)                        PIN_CFG(0x009C, 0x0328, 0x0000, 0x8, 0x0, p)
    208. 

  208. #define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS(p)                      PIN_CFG(0x00A0, 0x032C, 0x0628, 0x0, 0x1, p)
    209. 

  209. #define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS(p)                      PIN_CFG(0x00A0, 0x032C, 0x0000, 0x0, 0x0, p)
    210. 

  210. #define MX6UL_PAD_UART2_RTS_B__ENET1_COL(p)                          PIN_CFG(0x00A0, 0x032C, 0x0000, 0x1, 0x0, p)
    211. 

  211. #define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX(p)                        PIN_CFG(0x00A0, 0x032C, 0x0588, 0x12, 0x0, p)
    212. 

  212. #define MX6UL_PAD_UART2_RTS_B__CSI_DATA09(p)                         PIN_CFG(0x00A0, 0x032C, 0x0000, 0x3, 0x0, p)
    213. 

  213. #define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3(p)                      PIN_CFG(0x00A0, 0x032C, 0x0000, 0x4, 0x0, p)
    214. 

  214. #define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23(p)                         PIN_CFG(0x00A0, 0x032C, 0x0000, 0x5, 0x0, p)
    215. 

  215. #define MX6UL_PAD_UART2_RTS_B__SJC_FAIL(p)                           PIN_CFG(0x00A0, 0x032C, 0x0000, 0x7, 0x0, p)
    216. 

  216. #define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO(p)                        PIN_CFG(0x00A0, 0x032C, 0x0000, 0x8, 0x0, p)
    217. 

  217. #define MX6UL_PAD_UART3_TX_DATA__UART3_TX(p)                         PIN_CFG(0x00A4, 0x0330, 0x0634, 0x0, 0x0, p)
    218. 

  218. #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02(p)                    PIN_CFG(0x00A4, 0x0330, 0x0000, 0x1, 0x0, p)
    219. 

  219. #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD(p)                    PIN_CFG(0x00A4, 0x0330, 0x0000, 0x2, 0x0, p)
    220. 

  220. #define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01(p)                       PIN_CFG(0x00A4, 0x0330, 0x0000, 0x3, 0x0, p)
    221. 

  221. #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS(p)                    PIN_CFG(0x00A4, 0x0330, 0x0000, 0x4, 0x0, p)
    222. 

  222. #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS(p)                    PIN_CFG(0x00A4, 0x0330, 0x0628, 0x4, 0x2, p)
    223. 

  223. #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24(p)                       PIN_CFG(0x00A4, 0x0330, 0x0000, 0x5, 0x0, p)
    224. 

  224. #define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT(p)                     PIN_CFG(0x00A4, 0x0330, 0x0000, 0x7, 0x0, p)
    225. 

  225. #define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID(p)                   PIN_CFG(0x00A4, 0x0330, 0x0000, 0x8, 0x0, p)
    226. 

  226. #define MX6UL_PAD_UART3_RX_DATA__UART3_RX(p)                         PIN_CFG(0x00A8, 0x0334, 0x0634, 0x0, 0x1, p)
    227. 

  227. #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03(p)                    PIN_CFG(0x00A8, 0x0334, 0x0000, 0x1, 0x0, p)
    228. 

  228. #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD(p)                    PIN_CFG(0x00A8, 0x0334, 0x0000, 0x2, 0x0, p)
    229. 

  229. #define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00(p)                       PIN_CFG(0x00A8, 0x0334, 0x0000, 0x3, 0x0, p)
    230. 

  230. #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS(p)                    PIN_CFG(0x00A8, 0x0334, 0x0628, 0x4, 0x3, p)
    231. 

  231. #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS(p)                    PIN_CFG(0x00A8, 0x0334, 0x0000, 0x4, 0x0, p)
    232. 

  232. #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25(p)                       PIN_CFG(0x00A8, 0x0334, 0x0000, 0x5, 0x0, p)
    233. 

  233. #define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT(p)                        PIN_CFG(0x00A8, 0x0334, 0x0000, 0x8, 0x0, p)
    234. 

  234. #define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS(p)                      PIN_CFG(0x00AC, 0x0338, 0x0000, 0x0, 0x0, p)
    235. 

  235. #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS(p)                      PIN_CFG(0x00AC, 0x0338, 0x0630, 0x0, 0x0, p)
    236. 

  236. #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK(p)                       PIN_CFG(0x00AC, 0x0338, 0x0000, 0x1, 0x0, p)
    237. 

  237. #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX(p)                        PIN_CFG(0x00AC, 0x0338, 0x0000, 0x12, 0x0, p)
    238. 

  238. #define MX6UL_PAD_UART3_CTS_B__CSI_DATA10(p)                         PIN_CFG(0x00AC, 0x0338, 0x0000, 0x3, 0x0, p)
    239. 

  239. #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN(p)               PIN_CFG(0x00AC, 0x0338, 0x0000, 0x4, 0x0, p)
    240. 

  240. #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26(p)                         PIN_CFG(0x00AC, 0x0338, 0x0000, 0x5, 0x0, p)
    241. 

  241. #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT(p)                          PIN_CFG(0x00AC, 0x0338, 0x0000, 0x8, 0x0, p)
    242. 

  242. #define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS(p)                      PIN_CFG(0x00B0, 0x033C, 0x0630, 0x0, 0x1, p)
    243. 

  243. #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS(p)                      PIN_CFG(0x00B0, 0x033C, 0x0000, 0x0, 0x0, p)
    244. 

  244. #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER(p)                        PIN_CFG(0x00B0, 0x033C, 0x0000, 0x1, 0x0, p)
    245. 

  245. #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX(p)                        PIN_CFG(0x00B0, 0x033C, 0x0584, 0x12, 0x0, p)
    246. 

  246. #define MX6UL_PAD_UART3_RTS_B__CSI_DATA11(p)                         PIN_CFG(0x00B0, 0x033C, 0x0000, 0x3, 0x0, p)
    247. 

  247. #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT(p)              PIN_CFG(0x00B0, 0x033C, 0x0000, 0x4, 0x0, p)
    248. 

  248. #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27(p)                         PIN_CFG(0x00B0, 0x033C, 0x0000, 0x5, 0x0, p)
    249. 

  249. #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B(p)                       PIN_CFG(0x00B0, 0x033C, 0x0000, 0x8, 0x0, p)
    250. 

  250. #define MX6UL_PAD_UART4_TX_DATA__UART4_TX(p)                         PIN_CFG(0x00B4, 0x0340, 0x063C, 0x0, 0x0, p)
    251. 

  251. #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02(p)                    PIN_CFG(0x00B4, 0x0340, 0x0000, 0x1, 0x0, p)
    252. 

  252. #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL(p)                         PIN_CFG(0x00B4, 0x0340, 0x05A4, 0x12, 0x1, p)
    253. 

  253. #define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12(p)                       PIN_CFG(0x00B4, 0x0340, 0x0000, 0x3, 0x0, p)
    254. 

  254. #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02(p)              PIN_CFG(0x00B4, 0x0340, 0x0000, 0x4, 0x0, p)
    255. 

  255. #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28(p)                       PIN_CFG(0x00B4, 0x0340, 0x0000, 0x5, 0x0, p)
    256. 

  256. #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK(p)                      PIN_CFG(0x00B4, 0x0340, 0x0000, 0x8, 0x0, p)
    257. 

  257. #define MX6UL_PAD_UART4_RX_DATA__UART4_RX(p)                         PIN_CFG(0x00B8, 0x0344, 0x063C, 0x0, 0x1, p)
    258. 

  258. #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03(p)                    PIN_CFG(0x00B8, 0x0344, 0x0000, 0x1, 0x0, p)
    259. 

  259. #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA(p)                         PIN_CFG(0x00B8, 0x0344, 0x05A8, 0x12, 0x2, p)
    260. 

  260. #define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13(p)                       PIN_CFG(0x00B8, 0x0344, 0x0000, 0x3, 0x0, p)
    261. 

  261. #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01(p)              PIN_CFG(0x00B8, 0x0344, 0x0000, 0x4, 0x0, p)
    262. 

  262. #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29(p)                       PIN_CFG(0x00B8, 0x0344, 0x0000, 0x5, 0x0, p)
    263. 

  263. #define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0(p)                       PIN_CFG(0x00B8, 0x0344, 0x0000, 0x8, 0x0, p)
    264. 

  264. #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30(p)                       PIN_CFG(0x00BC, 0x0348, 0x0000, 0x5, 0x0, p)
    265. 

  265. #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI(p)                      PIN_CFG(0x00BC, 0x0348, 0x0000, 0x8, 0x0, p)
    266. 

  266. #define MX6UL_PAD_UART5_TX_DATA__UART5_TX(p)                         PIN_CFG(0x00BC, 0x0348, 0x0644, 0x0, 0x4, p)
    267. 

  267. #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS(p)                        PIN_CFG(0x00BC, 0x0348, 0x0000, 0x1, 0x0, p)
    268. 

  268. #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL(p)                         PIN_CFG(0x00BC, 0x0348, 0x05AC, 0x12, 0x2, p)
    269. 

  269. #define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14(p)                       PIN_CFG(0x00BC, 0x0348, 0x0000, 0x3, 0x0, p)
    270. 

  270. #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00(p)              PIN_CFG(0x00BC, 0x0348, 0x0000, 0x4, 0x0, p)
    271. 

  271. #define MX6UL_PAD_UART5_RX_DATA__UART5_RX(p)                         PIN_CFG(0x00C0, 0x034C, 0x0644, 0x0, 0x5, p)
    272. 

  272. #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL(p)                        PIN_CFG(0x00C0, 0x034C, 0x0000, 0x1, 0x0, p)
    273. 

  273. #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA(p)                         PIN_CFG(0x00C0, 0x034C, 0x05B0, 0x12, 0x2, p)
    274. 

  274. #define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15(p)                       PIN_CFG(0x00C0, 0x034C, 0x0000, 0x3, 0x0, p)
    275. 

  275. #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB(p)                  PIN_CFG(0x00C0, 0x034C, 0x0000, 0x4, 0x0, p)
    276. 

  276. #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31(p)                       PIN_CFG(0x00C0, 0x034C, 0x0000, 0x5, 0x0, p)
    277. 

  277. #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO(p)                      PIN_CFG(0x00C0, 0x034C, 0x0000, 0x8, 0x0, p)
    278. 

  278. #define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00(p)                   PIN_CFG(0x00C4, 0x0350, 0x0000, 0x0, 0x0, p)
    279. 

  279. #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS(p)                   PIN_CFG(0x00C4, 0x0350, 0x0638, 0x1, 0x0, p)
    280. 

  280. #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS(p)                   PIN_CFG(0x00C4, 0x0350, 0x0000, 0x1, 0x0, p)
    281. 

  281. #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT(p)                        PIN_CFG(0x00C4, 0x0350, 0x0000, 0x2, 0x0, p)
    282. 

  282. #define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16(p)                      PIN_CFG(0x00C4, 0x0350, 0x0000, 0x3, 0x0, p)
    283. 

  283. #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX(p)                     PIN_CFG(0x00C4, 0x0350, 0x0000, 0x4, 0x0, p)
    284. 

  284. #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00(p)                      PIN_CFG(0x00C4, 0x0350, 0x0000, 0x5, 0x0, p)
    285. 

  285. #define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00(p)                       PIN_CFG(0x00C4, 0x0350, 0x0000, 0x6, 0x0, p)
    286. 

  286. #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL(p)                     PIN_CFG(0x00C4, 0x0350, 0x0000, 0x8, 0x0, p)
    287. 

  287. #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01(p)                   PIN_CFG(0x00C8, 0x0354, 0x0000, 0x0, 0x0, p)
    288. 

  288. #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS(p)                   PIN_CFG(0x00C8, 0x0354, 0x0000, 0x1, 0x0, p)
    289. 

  289. #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS(p)                   PIN_CFG(0x00C8, 0x0354, 0x0638, 0x1, 0x1, p)
    290. 

  290. #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT(p)                        PIN_CFG(0x00C8, 0x0354, 0x0000, 0x2, 0x0, p)
    291. 

  291. #define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17(p)                      PIN_CFG(0x00C8, 0x0354, 0x0000, 0x3, 0x0, p)
    292. 

  292. #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX(p)                     PIN_CFG(0x00C8, 0x0354, 0x0584, 0x4, 0x1, p)
    293. 

  293. #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01(p)                      PIN_CFG(0x00C8, 0x0354, 0x0000, 0x5, 0x0, p)
    294. 

  294. #define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00(p)                       PIN_CFG(0x00C8, 0x0354, 0x0000, 0x6, 0x0, p)
    295. 

  295. #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL(p)                     PIN_CFG(0x00C8, 0x0354, 0x0000, 0x8, 0x0, p)
    296. 

  296. #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN(p)                        PIN_CFG(0x00CC, 0x0358, 0x0000, 0x0, 0x0, p)
    297. 

  297. #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS(p)                      PIN_CFG(0x00CC, 0x0358, 0x0640, 0x1, 0x3, p)
    298. 

  298. #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS(p)                      PIN_CFG(0x00CC, 0x0358, 0x0000, 0x1, 0x0, p)
    299. 

  299. #define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18(p)                         PIN_CFG(0x00CC, 0x0358, 0x0000, 0x3, 0x0, p)
    300. 

  300. #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX(p)                        PIN_CFG(0x00CC, 0x0358, 0x0000, 0x4, 0x0, p)
    301. 

  301. #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02(p)                         PIN_CFG(0x00CC, 0x0358, 0x0000, 0x5, 0x0, p)
    302. 

  302. #define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01(p)                          PIN_CFG(0x00CC, 0x0358, 0x0000, 0x6, 0x0, p)
    303. 

  303. #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT(p)                     PIN_CFG(0x00CC, 0x0358, 0x0000, 0x8, 0x0, p)
    304. 

  304. #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00(p)                   PIN_CFG(0x00D0, 0x035C, 0x0000, 0x0, 0x0, p)
    305. 

  305. #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS(p)                   PIN_CFG(0x00D0, 0x035C, 0x0000, 0x1, 0x0, p)
    306. 

  306. #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS(p)                   PIN_CFG(0x00D0, 0x035C, 0x0640, 0x1, 0x4, p)
    307. 

  307. #define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19(p)                      PIN_CFG(0x00D0, 0x035C, 0x0000, 0x3, 0x0, p)
    308. 

  308. #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX(p)                     PIN_CFG(0x00D0, 0x035C, 0x0588, 0x4, 0x1, p)
    309. 

  309. #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03(p)                      PIN_CFG(0x00D0, 0x035C, 0x0000, 0x5, 0x0, p)
    310. 

  310. #define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01(p)                       PIN_CFG(0x00D0, 0x035C, 0x0000, 0x6, 0x0, p)
    311. 

  311. #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT(p)                  PIN_CFG(0x00D0, 0x035C, 0x0000, 0x8, 0x0, p)
    312. 

  312. #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01(p)                   PIN_CFG(0x00D4, 0x0360, 0x0000, 0x0, 0x0, p)
    313. 

  313. #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS(p)                   PIN_CFG(0x00D4, 0x0360, 0x0000, 0x1, 0x0, p)
    314. 

  314. #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS(p)                   PIN_CFG(0x00D4, 0x0360, 0x0648, 0x1, 0x2, p)
    315. 

  315. #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT(p)                        PIN_CFG(0x00D4, 0x0360, 0x0000, 0x2, 0x0, p)
    316. 

  316. #define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20(p)                      PIN_CFG(0x00D4, 0x0360, 0x0000, 0x3, 0x0, p)
    317. 

  317. #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO(p)                      PIN_CFG(0x00D4, 0x0360, 0x0580, 0x4, 0x1, p)
    318. 

  318. #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04(p)                      PIN_CFG(0x00D4, 0x0360, 0x0000, 0x5, 0x0, p)
    319. 

  319. #define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02(p)                       PIN_CFG(0x00D4, 0x0360, 0x0000, 0x6, 0x0, p)
    320. 

  320. #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB(p)            PIN_CFG(0x00D4, 0x0360, 0x0000, 0x8, 0x0, p)
    321. 

  321. #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN(p)                        PIN_CFG(0x00D8, 0x0364, 0x0000, 0x0, 0x0, p)
    322. 

  322. #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS(p)                      PIN_CFG(0x00D8, 0x0364, 0x0648, 0x1, 0x3, p)
    323. 

  323. #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS(p)                      PIN_CFG(0x00D8, 0x0364, 0x0000, 0x1, 0x0, p)
    324. 

  324. #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT(p)                           PIN_CFG(0x00D8, 0x0364, 0x0000, 0x2, 0x0, p)
    325. 

  325. #define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21(p)                         PIN_CFG(0x00D8, 0x0364, 0x0000, 0x3, 0x0, p)
    326. 

  326. #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC(p)                          PIN_CFG(0x00D8, 0x0364, 0x0000, 0x4, 0x0, p)
    327. 

  327. #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05(p)                         PIN_CFG(0x00D8, 0x0364, 0x0000, 0x5, 0x0, p)
    328. 

  328. #define MX6UL_PAD_ENET1_TX_EN__KPP_COL02(p)                          PIN_CFG(0x00D8, 0x0364, 0x0000, 0x6, 0x0, p)
    329. 

  329. #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB(p)               PIN_CFG(0x00D8, 0x0364, 0x0000, 0x8, 0x0, p)
    330. 

  330. #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK(p)                      PIN_CFG(0x00DC, 0x0368, 0x0000, 0x0, 0x0, p)
    331. 

  331. #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS(p)                     PIN_CFG(0x00DC, 0x0368, 0x0000, 0x1, 0x0, p)
    332. 

  332. #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS(p)                     PIN_CFG(0x00DC, 0x0368, 0x0650, 0x1, 0x0, p)
    333. 

  333. #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT(p)                          PIN_CFG(0x00DC, 0x0368, 0x0000, 0x2, 0x0, p)
    334. 

  334. #define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22(p)                        PIN_CFG(0x00DC, 0x0368, 0x0000, 0x3, 0x0, p)
    335. 

  335. #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1(p)                    PIN_CFG(0x00DC, 0x0368, 0x0574, 0x14, 0x2, p)
    336. 

  336. #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06(p)                        PIN_CFG(0x00DC, 0x0368, 0x0000, 0x5, 0x0, p)
    337. 

  337. #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03(p)                         PIN_CFG(0x00DC, 0x0368, 0x0000, 0x6, 0x0, p)
    338. 

  338. #define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK(p)                          PIN_CFG(0x00DC, 0x0368, 0x0000, 0x8, 0x0, p)
    339. 

  339. #define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER(p)                        PIN_CFG(0x00E0, 0x036C, 0x0000, 0x0, 0x0, p)
    340. 

  340. #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS(p)                      PIN_CFG(0x00E0, 0x036C, 0x0650, 0x1, 0x1, p)
    341. 

  341. #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS(p)                      PIN_CFG(0x00E0, 0x036C, 0x0000, 0x1, 0x0, p)
    342. 

  342. #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT(p)                           PIN_CFG(0x00E0, 0x036C, 0x0000, 0x2, 0x0, p)
    343. 

  343. #define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23(p)                         PIN_CFG(0x00E0, 0x036C, 0x0000, 0x3, 0x0, p)
    344. 

  344. #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE(p)                            PIN_CFG(0x00E0, 0x036C, 0x0000, 0x4, 0x0, p)
    345. 

  345. #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07(p)                         PIN_CFG(0x00E0, 0x036C, 0x0000, 0x5, 0x0, p)
    346. 

  346. #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03(p)                          PIN_CFG(0x00E0, 0x036C, 0x0000, 0x6, 0x0, p)
    347. 

  347. #define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2(p)                      PIN_CFG(0x00E0, 0x036C, 0x0000, 0x8, 0x0, p)
    348. 

  348. #define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00(p)                   PIN_CFG(0x00E4, 0x0370, 0x0000, 0x0, 0x0, p)
    349. 

  349. #define MX6UL_PAD_ENET2_RX_DATA0__UART6_TX(p)                        PIN_CFG(0x00E4, 0x0370, 0x064C, 0x1, 0x1, p)
    350. 

  350. #define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD(p)                 PIN_CFG(0x00E4, 0x0370, 0x0000, 0x2, 0x0, p)
    351. 

  351. #define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL(p)                        PIN_CFG(0x00E4, 0x0370, 0x05B4, 0x3, 0x1, p)
    352. 

  352. #define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO(p)                      PIN_CFG(0x00E4, 0x0370, 0x0578, 0x4, 0x1, p)
    353. 

  353. #define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08(p)                      PIN_CFG(0x00E4, 0x0370, 0x0000, 0x5, 0x0, p)
    354. 

  354. #define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04(p)                       PIN_CFG(0x00E4, 0x0370, 0x0000, 0x6, 0x0, p)
    355. 

  355. #define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR(p)                    PIN_CFG(0x00E4, 0x0370, 0x0000, 0x8, 0x0, p)
    356. 

  356. #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01(p)                   PIN_CFG(0x00E8, 0x0374, 0x0000, 0x0, 0x0, p)
    357. 

  357. #define MX6UL_PAD_ENET2_RX_DATA1__UART6_RX(p)                        PIN_CFG(0x00E8, 0x0374, 0x064C, 0x1, 0x2, p)
    358. 

  358. #define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK(p)                  PIN_CFG(0x00E8, 0x0374, 0x0000, 0x2, 0x0, p)
    359. 

  359. #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA(p)                        PIN_CFG(0x00E8, 0x0374, 0x05B8, 0x3, 0x1, p)
    360. 

  360. #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC(p)                       PIN_CFG(0x00E8, 0x0374, 0x0000, 0x4, 0x0, p)
    361. 

  361. #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09(p)                      PIN_CFG(0x00E8, 0x0374, 0x0000, 0x5, 0x0, p)
    362. 

  362. #define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04(p)                       PIN_CFG(0x00E8, 0x0374, 0x0000, 0x6, 0x0, p)
    363. 

  363. #define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC(p)                     PIN_CFG(0x00E8, 0x0374, 0x0000, 0x8, 0x0, p)
    364. 

  364. #define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN(p)                        PIN_CFG(0x00EC, 0x0378, 0x0000, 0x0, 0x0, p)
    365. 

  365. #define MX6UL_PAD_ENET2_RX_EN__UART7_TX(p)                           PIN_CFG(0x00EC, 0x0378, 0x0654, 0x1, 0x0, p)
    366. 

  366. #define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B(p)                   PIN_CFG(0x00EC, 0x0378, 0x0000, 0x2, 0x0, p)
    367. 

  367. #define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL(p)                           PIN_CFG(0x00EC, 0x0378, 0x05BC, 0x3, 0x1, p)
    368. 

  368. #define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26(p)                         PIN_CFG(0x00EC, 0x0378, 0x0000, 0x4, 0x0, p)
    369. 

  369. #define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10(p)                         PIN_CFG(0x00EC, 0x0378, 0x0000, 0x5, 0x0, p)
    370. 

  370. #define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05(p)                          PIN_CFG(0x00EC, 0x0378, 0x0000, 0x6, 0x0, p)
    371. 

  371. #define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M(p)                  PIN_CFG(0x00EC, 0x0378, 0x0000, 0x8, 0x0, p)
    372. 

  372. #define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00(p)                   PIN_CFG(0x00F0, 0x037C, 0x0000, 0x0, 0x0, p)
    373. 

  373. #define MX6UL_PAD_ENET2_TX_DATA0__UART7_RX(p)                        PIN_CFG(0x00F0, 0x037C, 0x0654, 0x1, 0x1, p)
    374. 

  374. #define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN(p)                 PIN_CFG(0x00F0, 0x037C, 0x0000, 0x2, 0x0, p)
    375. 

  375. #define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA(p)                        PIN_CFG(0x00F0, 0x037C, 0x05C0, 0x3, 0x1, p)
    376. 

  376. #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02(p)                      PIN_CFG(0x00F0, 0x037C, 0x0000, 0x4, 0x0, p)
    377. 

  377. #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11(p)                      PIN_CFG(0x00F0, 0x037C, 0x0000, 0x5, 0x0, p)
    378. 

  378. #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05(p)                       PIN_CFG(0x00F0, 0x037C, 0x0000, 0x6, 0x0, p)
    379. 

  379. #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01(p)                   PIN_CFG(0x00F4, 0x0380, 0x0000, 0x0, 0x0, p)
    380. 

  380. #define MX6UL_PAD_ENET2_TX_DATA1__UART8_TX(p)                        PIN_CFG(0x00F4, 0x0380, 0x065C, 0x1, 0x0, p)
    381. 

  381. #define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD(p)                 PIN_CFG(0x00F4, 0x0380, 0x0000, 0x2, 0x0, p)
    382. 

  382. #define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK(p)                     PIN_CFG(0x00F4, 0x0380, 0x0564, 0x3, 0x0, p)
    383. 

  383. #define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03(p)                      PIN_CFG(0x00F4, 0x0380, 0x0000, 0x4, 0x0, p)
    384. 

  384. #define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12(p)                      PIN_CFG(0x00F4, 0x0380, 0x0000, 0x5, 0x0, p)
    385. 

  385. #define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06(p)                       PIN_CFG(0x00F4, 0x0380, 0x0000, 0x6, 0x0, p)
    386. 

  386. #define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR(p)                    PIN_CFG(0x00F4, 0x0380, 0x0000, 0x8, 0x0, p)
    387. 

  387. #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN(p)                        PIN_CFG(0x00F8, 0x0384, 0x0000, 0x0, 0x0, p)
    388. 

  388. #define MX6UL_PAD_ENET2_TX_EN__UART8_RX(p)                           PIN_CFG(0x00F8, 0x0384, 0x065C, 0x1, 0x1, p)
    389. 

  389. #define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK(p)                     PIN_CFG(0x00F8, 0x0384, 0x0000, 0x2, 0x0, p)
    390. 

  390. #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI(p)                        PIN_CFG(0x00F8, 0x0384, 0x056C, 0x3, 0x0, p)
    391. 

  391. #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN(p)                   PIN_CFG(0x00F8, 0x0384, 0x0000, 0x4, 0x0, p)
    392. 

  392. #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13(p)                         PIN_CFG(0x00F8, 0x0384, 0x0000, 0x5, 0x0, p)
    393. 

  393. #define MX6UL_PAD_ENET2_TX_EN__KPP_COL06(p)                          PIN_CFG(0x00F8, 0x0384, 0x0000, 0x6, 0x0, p)
    394. 

  394. #define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC(p)                        PIN_CFG(0x00F8, 0x0384, 0x0000, 0x8, 0x0, p)
    395. 

  395. #define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK(p)                      PIN_CFG(0x00FC, 0x0388, 0x0000, 0x0, 0x0, p)
    396. 

  396. #define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS(p)                     PIN_CFG(0x00FC, 0x0388, 0x0000, 0x1, 0x0, p)
    397. 

  397. #define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS(p)                     PIN_CFG(0x00FC, 0x0388, 0x0658, 0x1, 0x0, p)
    398. 

  398. #define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B(p)                  PIN_CFG(0x00FC, 0x0388, 0x0000, 0x2, 0x0, p)
    399. 

  399. #define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO(p)                       PIN_CFG(0x00FC, 0x0388, 0x0568, 0x3, 0x0, p)
    400. 

  400. #define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2(p)                    PIN_CFG(0x00FC, 0x0388, 0x057C, 0x14, 0x2, p)
    401. 

  401. #define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14(p)                        PIN_CFG(0x00FC, 0x0388, 0x0000, 0x5, 0x0, p)
    402. 

  402. #define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07(p)                         PIN_CFG(0x00FC, 0x0388, 0x0000, 0x6, 0x0, p)
    403. 

  403. #define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID(p)                    PIN_CFG(0x00FC, 0x0388, 0x0000, 0x8, 0x0, p)
    404. 

  404. #define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER(p)                        PIN_CFG(0x0100, 0x038C, 0x0000, 0x0, 0x0, p)
    405. 

  405. #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS(p)                      PIN_CFG(0x0100, 0x038C, 0x0658, 0x1, 0x1, p)
    406. 

  406. #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS(p)                      PIN_CFG(0x0100, 0x038C, 0x0000, 0x1, 0x0, p)
    407. 

  407. #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN(p)                    PIN_CFG(0x0100, 0x038C, 0x0000, 0x2, 0x0, p)
    408. 

  408. #define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0(p)                         PIN_CFG(0x0100, 0x038C, 0x0000, 0x3, 0x0, p)
    409. 

  409. #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25(p)                         PIN_CFG(0x0100, 0x038C, 0x0000, 0x4, 0x0, p)
    410. 

  410. #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15(p)                         PIN_CFG(0x0100, 0x038C, 0x0000, 0x5, 0x0, p)
    411. 

  411. #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07(p)                          PIN_CFG(0x0100, 0x038C, 0x0000, 0x6, 0x0, p)
    412. 

  412. #define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY(p)                     PIN_CFG(0x0100, 0x038C, 0x0000, 0x8, 0x0, p)
    413. 

  413. #define MX6UL_PAD_LCD_CLK__LCDIF_CLK(p)                              PIN_CFG(0x0104, 0x0390, 0x0000, 0x0, 0x0, p)
    414. 

  414. #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN(p)                           PIN_CFG(0x0104, 0x0390, 0x0000, 0x1, 0x0, p)
    415. 

  415. #define MX6UL_PAD_LCD_CLK__UART4_TX(p)                               PIN_CFG(0x0104, 0x0390, 0x063C, 0x2, 0x2, p)
    416. 

  416. #define MX6UL_PAD_LCD_CLK__SAI3_MCLK(p)                              PIN_CFG(0x0104, 0x0390, 0x0000, 0x3, 0x0, p)
    417. 

  417. #define MX6UL_PAD_LCD_CLK__EIM_CS2_B(p)                              PIN_CFG(0x0104, 0x0390, 0x0000, 0x4, 0x0, p)
    418. 

  418. #define MX6UL_PAD_LCD_CLK__GPIO3_IO00(p)                             PIN_CFG(0x0104, 0x0390, 0x0000, 0x5, 0x0, p)
    419. 

  419. #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB(p)                   PIN_CFG(0x0104, 0x0390, 0x0000, 0x8, 0x0, p)
    420. 

  420. #define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE(p)                        PIN_CFG(0x0108, 0x0394, 0x0000, 0x0, 0x0, p)
    421. 

  421. #define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E(p)                          PIN_CFG(0x0108, 0x0394, 0x0000, 0x1, 0x0, p)
    422. 

  422. #define MX6UL_PAD_LCD_ENABLE__UART4_RX(p)                            PIN_CFG(0x0108, 0x0394, 0x063C, 0x2, 0x3, p)
    423. 

  423. #define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC(p)                        PIN_CFG(0x0108, 0x0394, 0x060C, 0x3, 0x0, p)
    424. 

  424. #define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B(p)                           PIN_CFG(0x0108, 0x0394, 0x0000, 0x4, 0x0, p)
    425. 

  425. #define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01(p)                          PIN_CFG(0x0108, 0x0394, 0x0000, 0x5, 0x0, p)
    426. 

  426. #define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY(p)                          PIN_CFG(0x0108, 0x0394, 0x0000, 0x8, 0x0, p)
    427. 

  427. #define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC(p)                          PIN_CFG(0x010C, 0x0398, 0x05DC, 0x0, 0x0, p)
    428. 

  428. #define MX6UL_PAD_LCD_HSYNC__LCDIF_RS(p)                             PIN_CFG(0x010C, 0x0398, 0x0000, 0x1, 0x0, p)
    429. 

  429. #define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS(p)                        PIN_CFG(0x010C, 0x0398, 0x0000, 0x2, 0x0, p)
    430. 

  430. #define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS(p)                        PIN_CFG(0x010C, 0x0398, 0x0638, 0x2, 0x2, p)
    431. 

  431. #define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK(p)                         PIN_CFG(0x010C, 0x0398, 0x0608, 0x3, 0x0, p)
    432. 

  432. #define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB(p)                 PIN_CFG(0x010C, 0x0398, 0x0000, 0x4, 0x0, p)
    433. 

  433. #define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02(p)                           PIN_CFG(0x010C, 0x0398, 0x0000, 0x5, 0x0, p)
    434. 

  434. #define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1(p)                           PIN_CFG(0x010C, 0x0398, 0x0000, 0x8, 0x0, p)
    435. 

  435. #define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC(p)                          PIN_CFG(0x0110, 0x039C, 0x0000, 0x0, 0x0, p)
    436. 

  436. #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY(p)                           PIN_CFG(0x0110, 0x039C, 0x05DC, 0x1, 0x1, p)
    437. 

  437. #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS(p)                        PIN_CFG(0x0110, 0x039C, 0x0638, 0x2, 0x3, p)
    438. 

  438. #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS(p)                        PIN_CFG(0x0110, 0x039C, 0x0000, 0x2, 0x0, p)
    439. 

  439. #define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA(p)                         PIN_CFG(0x0110, 0x039C, 0x0000, 0x3, 0x0, p)
    440. 

  440. #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B(p)                         PIN_CFG(0x0110, 0x039C, 0x0000, 0x4, 0x0, p)
    441. 

  441. #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03(p)                           PIN_CFG(0x0110, 0x039C, 0x0000, 0x5, 0x0, p)
    442. 

  442. #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2(p)                           PIN_CFG(0x0110, 0x039C, 0x0000, 0x8, 0x0, p)
    443. 

  443. #define MX6UL_PAD_LCD_RESET__LCDIF_RESET(p)                          PIN_CFG(0x0114, 0x03A0, 0x0000, 0x0, 0x0, p)
    444. 

  444. #define MX6UL_PAD_LCD_RESET__LCDIF_CS(p)                             PIN_CFG(0x0114, 0x03A0, 0x0000, 0x1, 0x0, p)
    445. 

  445. #define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI(p)                     PIN_CFG(0x0114, 0x03A0, 0x0000, 0x2, 0x0, p)
    446. 

  446. #define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA(p)                         PIN_CFG(0x0114, 0x03A0, 0x0000, 0x3, 0x0, p)
    447. 

  447. #define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY(p)                       PIN_CFG(0x0114, 0x03A0, 0x0000, 0x4, 0x0, p)
    448. 

  448. #define MX6UL_PAD_LCD_RESET__GPIO3_IO04(p)                           PIN_CFG(0x0114, 0x03A0, 0x0000, 0x5, 0x0, p)
    449. 

  449. #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3(p)                           PIN_CFG(0x0114, 0x03A0, 0x0000, 0x8, 0x0, p)
    450. 

  450. #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00(p)                        PIN_CFG(0x0118, 0x03A4, 0x0000, 0x0, 0x0, p)
    451. 

  451. #define MX6UL_PAD_LCD_DATA00__PWM1_OUT(p)                            PIN_CFG(0x0118, 0x03A4, 0x0000, 0x1, 0x0, p)
    452. 

  452. #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN(p)                PIN_CFG(0x0118, 0x03A4, 0x0000, 0x3, 0x0, p)
    453. 

  453. #define MX6UL_PAD_LCD_DATA00__I2C3_SDA(p)                            PIN_CFG(0x0118, 0x03A4, 0x05B8, 0x4, 0x2, p)
    454. 

  454. #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05(p)                          PIN_CFG(0x0118, 0x03A4, 0x0000, 0x5, 0x0, p)
    455. 

  455. #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00(p)                        PIN_CFG(0x0118, 0x03A4, 0x0000, 0x6, 0x0, p)
    456. 

  456. #define MX6UL_PAD_LCD_DATA00__SAI1_MCLK(p)                           PIN_CFG(0x0118, 0x03A4, 0x0000, 0x8, 0x0, p)
    457. 

  457. #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01(p)                        PIN_CFG(0x011C, 0x03A8, 0x0000, 0x0, 0x0, p)
    458. 

  458. #define MX6UL_PAD_LCD_DATA01__PWM2_OUT(p)                            PIN_CFG(0x011C, 0x03A8, 0x0000, 0x1, 0x0, p)
    459. 

  459. #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT(p)               PIN_CFG(0x011C, 0x03A8, 0x0000, 0x3, 0x0, p)
    460. 

  460. #define MX6UL_PAD_LCD_DATA01__I2C3_SCL(p)                            PIN_CFG(0x011C, 0x03A8, 0x05B4, 0x4, 0x2, p)
    461. 

  461. #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06(p)                          PIN_CFG(0x011C, 0x03A8, 0x0000, 0x5, 0x0, p)
    462. 

  462. #define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01(p)                        PIN_CFG(0x011C, 0x03A8, 0x0000, 0x6, 0x0, p)
    463. 

  463. #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC(p)                        PIN_CFG(0x011C, 0x03A8, 0x0000, 0x8, 0x0, p)
    464. 

  464. #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02(p)                        PIN_CFG(0x0120, 0x03AC, 0x0000, 0x0, 0x0, p)
    465. 

  465. #define MX6UL_PAD_LCD_DATA02__PWM3_OUT(p)                            PIN_CFG(0x0120, 0x03AC, 0x0000, 0x1, 0x0, p)
    466. 

  466. #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN(p)                PIN_CFG(0x0120, 0x03AC, 0x0000, 0x3, 0x0, p)
    467. 

  467. #define MX6UL_PAD_LCD_DATA02__I2C4_SDA(p)                            PIN_CFG(0x0120, 0x03AC, 0x05C0, 0x4, 0x2, p)
    468. 

  468. #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07(p)                          PIN_CFG(0x0120, 0x03AC, 0x0000, 0x5, 0x0, p)
    469. 

  469. #define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02(p)                        PIN_CFG(0x0120, 0x03AC, 0x0000, 0x6, 0x0, p)
    470. 

  470. #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK(p)                        PIN_CFG(0x0120, 0x03AC, 0x0000, 0x8, 0x0, p)
    471. 

  471. #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03(p)                        PIN_CFG(0x0124, 0x03B0, 0x0000, 0x0, 0x0, p)
    472. 

  472. #define MX6UL_PAD_LCD_DATA03__PWM4_OUT(p)                            PIN_CFG(0x0124, 0x03B0, 0x0000, 0x1, 0x0, p)
    473. 

  473. #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT(p)               PIN_CFG(0x0124, 0x03B0, 0x0000, 0x3, 0x0, p)
    474. 

  474. #define MX6UL_PAD_LCD_DATA03__I2C4_SCL(p)                            PIN_CFG(0x0124, 0x03B0, 0x05BC, 0x4, 0x2, p)
    475. 

  475. #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08(p)                          PIN_CFG(0x0124, 0x03B0, 0x0000, 0x5, 0x0, p)
    476. 

  476. #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03(p)                        PIN_CFG(0x0124, 0x03B0, 0x0000, 0x6, 0x0, p)
    477. 

  477. #define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA(p)                        PIN_CFG(0x0124, 0x03B0, 0x0000, 0x8, 0x0, p)
    478. 

  478. #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x0, 0x0, p)
    479. 

  479. #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS(p)                       PIN_CFG(0x0128, 0x03B4, 0x0000, 0x1, 0x0, p)
    480. 

  480. #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS(p)                       PIN_CFG(0x0128, 0x03B4, 0x0658, 0x1, 0x2, p)
    481. 

  481. #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN(p)                PIN_CFG(0x0128, 0x03B4, 0x0000, 0x3, 0x0, p)
    482. 

  482. #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x4, 0x0, p)
    483. 

  483. #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09(p)                          PIN_CFG(0x0128, 0x03B4, 0x0000, 0x5, 0x0, p)
    484. 

  484. #define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x6, 0x0, p)
    485. 

  485. #define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x8, 0x0, p)
    486. 

  486. #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05(p)                        PIN_CFG(0x012C, 0x03B8, 0x0000, 0x0, 0x0, p)
    487. 

  487. #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS(p)                       PIN_CFG(0x012C, 0x03B8, 0x0658, 0x1, 0x3, p)
    488. 

  488. #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS(p)                       PIN_CFG(0x012C, 0x03B8, 0x0000, 0x1, 0x0, p)
    489. 

  489. #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT(p)               PIN_CFG(0x012C, 0x03B8, 0x0000, 0x3, 0x0, p)
    490. 

  490. #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT(p)                           PIN_CFG(0x012C, 0x03B8, 0x0000, 0x4, 0x0, p)
    491. 

  491. #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10(p)                          PIN_CFG(0x012C, 0x03B8, 0x0000, 0x5, 0x0, p)
    492. 

  492. #define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05(p)                        PIN_CFG(0x012C, 0x03B8, 0x0000, 0x6, 0x0, p)
    493. 

  493. #define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1(p)                          PIN_CFG(0x012C, 0x03B8, 0x0000, 0x8, 0x0, p)
    494. 

  494. #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06(p)                        PIN_CFG(0x0130, 0x03BC, 0x0000, 0x0, 0x0, p)
    495. 

  495. #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS(p)                       PIN_CFG(0x0130, 0x03BC, 0x0000, 0x1, 0x0, p)
    496. 

  496. #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS(p)                       PIN_CFG(0x0130, 0x03BC, 0x0650, 0x1, 0x2, p)
    497. 

  497. #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN(p)                PIN_CFG(0x0130, 0x03BC, 0x0000, 0x3, 0x0, p)
    498. 

  498. #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK(p)                          PIN_CFG(0x0130, 0x03BC, 0x0000, 0x4, 0x0, p)
    499. 

  499. #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11(p)                          PIN_CFG(0x0130, 0x03BC, 0x0000, 0x5, 0x0, p)
    500. 

  500. #define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06(p)                        PIN_CFG(0x0130, 0x03BC, 0x0000, 0x6, 0x0, p)
    501. 

  501. #define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2(p)                          PIN_CFG(0x0130, 0x03BC, 0x0000, 0x8, 0x0, p)
    502. 

  502. #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07(p)                        PIN_CFG(0x0134, 0x03C0, 0x0000, 0x0, 0x0, p)
    503. 

  503. #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS(p)                       PIN_CFG(0x0134, 0x03C0, 0x0650, 0x1, 0x3, p)
    504. 

  504. #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS(p)                       PIN_CFG(0x0134, 0x03C0, 0x0000, 0x1, 0x0, p)
    505. 

  505. #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT(p)               PIN_CFG(0x0134, 0x03C0, 0x0000, 0x3, 0x0, p)
    506. 

  506. #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK(p)                       PIN_CFG(0x0134, 0x03C0, 0x061C, 0x4, 0x0, p)
    507. 

  507. #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12(p)                          PIN_CFG(0x0134, 0x03C0, 0x0000, 0x5, 0x0, p)
    508. 

  508. #define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07(p)                        PIN_CFG(0x0134, 0x03C0, 0x0000, 0x6, 0x0, p)
    509. 

  509. #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3(p)                          PIN_CFG(0x0134, 0x03C0, 0x0000, 0x8, 0x0, p)
    510. 

  510. #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08(p)                        PIN_CFG(0x0138, 0x03C4, 0x0000, 0x0, 0x0, p)
    511. 

  511. #define MX6UL_PAD_LCD_DATA08__SPDIF_IN(p)                            PIN_CFG(0x0138, 0x03C4, 0x0618, 0x1, 0x2, p)
    512. 

  512. #define MX6UL_PAD_LCD_DATA08__CSI_DATA16(p)                          PIN_CFG(0x0138, 0x03C4, 0x0000, 0x3, 0x0, p)
    513. 

  513. #define MX6UL_PAD_LCD_DATA08__EIM_DATA00(p)                          PIN_CFG(0x0138, 0x03C4, 0x0000, 0x4, 0x0, p)
    514. 

  514. #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13(p)                          PIN_CFG(0x0138, 0x03C4, 0x0000, 0x5, 0x0, p)
    515. 

  515. #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08(p)                        PIN_CFG(0x0138, 0x03C4, 0x0000, 0x6, 0x0, p)
    516. 

  516. #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX(p)                         PIN_CFG(0x0138, 0x03C4, 0x0000, 0x8, 0x0, p)
    517. 

  517. #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09(p)                        PIN_CFG(0x013C, 0x03C8, 0x0000, 0x0, 0x0, p)
    518. 

  518. #define MX6UL_PAD_LCD_DATA09__SAI3_MCLK(p)                           PIN_CFG(0x013C, 0x03C8, 0x0000, 0x1, 0x0, p)
    519. 

  519. #define MX6UL_PAD_LCD_DATA09__CSI_DATA17(p)                          PIN_CFG(0x013C, 0x03C8, 0x0000, 0x3, 0x0, p)
    520. 

  520. #define MX6UL_PAD_LCD_DATA09__EIM_DATA01(p)                          PIN_CFG(0x013C, 0x03C8, 0x0000, 0x4, 0x0, p)
    521. 

  521. #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14(p)                          PIN_CFG(0x013C, 0x03C8, 0x0000, 0x5, 0x0, p)
    522. 

  522. #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09(p)                        PIN_CFG(0x013C, 0x03C8, 0x0000, 0x6, 0x0, p)
    523. 

  523. #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX(p)                         PIN_CFG(0x013C, 0x03C8, 0x0000, 0x8, 0x0, p)
    524. 

  524. #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10(p)                        PIN_CFG(0x0140, 0x03CC, 0x0000, 0x0, 0x0, p)
    525. 

  525. #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC(p)                        PIN_CFG(0x0140, 0x03CC, 0x0000, 0x1, 0x0, p)
    526. 

  526. #define MX6UL_PAD_LCD_DATA10__CSI_DATA18(p)                          PIN_CFG(0x0140, 0x03CC, 0x0000, 0x3, 0x0, p)
    527. 

  527. #define MX6UL_PAD_LCD_DATA10__EIM_DATA02(p)                          PIN_CFG(0x0140, 0x03CC, 0x0000, 0x4, 0x0, p)
    528. 

  528. #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15(p)                          PIN_CFG(0x0140, 0x03CC, 0x0000, 0x5, 0x0, p)
    529. 

  529. #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10(p)                        PIN_CFG(0x0140, 0x03CC, 0x0000, 0x6, 0x0, p)
    530. 

  530. #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX(p)                         PIN_CFG(0x0140, 0x03CC, 0x0000, 0x8, 0x0, p)
    531. 

  531. #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11(p)                        PIN_CFG(0x0144, 0x03D0, 0x0000, 0x0, 0x0, p)
    532. 

  532. #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK(p)                        PIN_CFG(0x0144, 0x03D0, 0x0000, 0x1, 0x0, p)
    533. 

  533. #define MX6UL_PAD_LCD_DATA11__CSI_DATA19(p)                          PIN_CFG(0x0144, 0x03D0, 0x0000, 0x3, 0x0, p)
    534. 

  534. #define MX6UL_PAD_LCD_DATA11__EIM_DATA03(p)                          PIN_CFG(0x0144, 0x03D0, 0x0000, 0x4, 0x0, p)
    535. 

  535. #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16(p)                          PIN_CFG(0x0144, 0x03D0, 0x0000, 0x5, 0x0, p)
    536. 

  536. #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11(p)                        PIN_CFG(0x0144, 0x03D0, 0x0000, 0x6, 0x0, p)
    537. 

  537. #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX(p)                         PIN_CFG(0x0144, 0x03D0, 0x0000, 0x8, 0x0, p)
    538. 

  538. #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12(p)                        PIN_CFG(0x0148, 0x03D4, 0x0000, 0x0, 0x0, p)
    539. 

  539. #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC(p)                        PIN_CFG(0x0148, 0x03D4, 0x060C, 0x1, 0x1, p)
    540. 

  540. #define MX6UL_PAD_LCD_DATA12__CSI_DATA20(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x3, 0x0, p)
    541. 

  541. #define MX6UL_PAD_LCD_DATA12__EIM_DATA04(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x4, 0x0, p)
    542. 

  542. #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x5, 0x0, p)
    543. 

  543. #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12(p)                        PIN_CFG(0x0148, 0x03D4, 0x0000, 0x6, 0x0, p)
    544. 

  544. #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x8, 0x0, p)
    545. 

  545. #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13(p)                        PIN_CFG(0x014C, 0x03D8, 0x0000, 0x0, 0x0, p)
    546. 

  546. #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK(p)                        PIN_CFG(0x014C, 0x03D8, 0x0608, 0x1, 0x1, p)
    547. 

  547. #define MX6UL_PAD_LCD_DATA13__CSI_DATA21(p)                          PIN_CFG(0x014C, 0x03D8, 0x0000, 0x3, 0x0, p)
    548. 

  548. #define MX6UL_PAD_LCD_DATA13__EIM_DATA05(p)                          PIN_CFG(0x014C, 0x03D8, 0x0000, 0x4, 0x0, p)
    549. 

  549. #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18(p)                          PIN_CFG(0x014C, 0x03D8, 0x0000, 0x5, 0x0, p)
    550. 

  550. #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13(p)                        PIN_CFG(0x014C, 0x03D8, 0x0000, 0x6, 0x0, p)
    551. 

  551. #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B(p)                      PIN_CFG(0x014C, 0x03D8, 0x0000, 0x8, 0x0, p)
    552. 

  552. #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x0, 0x0, p)
    553. 

  553. #define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x1, 0x0, p)
    554. 

  554. #define MX6UL_PAD_LCD_DATA14__CSI_DATA22(p)                          PIN_CFG(0x0150, 0x03DC, 0x0000, 0x3, 0x0, p)
    555. 

  555. #define MX6UL_PAD_LCD_DATA14__EIM_DATA06(p)                          PIN_CFG(0x0150, 0x03DC, 0x0000, 0x4, 0x0, p)
    556. 

  556. #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19(p)                          PIN_CFG(0x0150, 0x03DC, 0x0000, 0x5, 0x0, p)
    557. 

  557. #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x6, 0x0, p)
    558. 

  558. #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x8, 0x0, p)
    559. 

  559. #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x0, 0x0, p)
    560. 

  560. #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x1, 0x0, p)
    561. 

  561. #define MX6UL_PAD_LCD_DATA15__CSI_DATA23(p)                          PIN_CFG(0x0154, 0x03E0, 0x0000, 0x3, 0x0, p)
    562. 

  562. #define MX6UL_PAD_LCD_DATA15__EIM_DATA07(p)                          PIN_CFG(0x0154, 0x03E0, 0x0000, 0x4, 0x0, p)
    563. 

  563. #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20(p)                          PIN_CFG(0x0154, 0x03E0, 0x0000, 0x5, 0x0, p)
    564. 

  564. #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x6, 0x0, p)
    565. 

  565. #define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x8, 0x0, p)
    566. 

  566. #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16(p)                        PIN_CFG(0x0158, 0x03E4, 0x0000, 0x0, 0x0, p)
    567. 

  567. #define MX6UL_PAD_LCD_DATA16__UART7_TX(p)                            PIN_CFG(0x0158, 0x03E4, 0x0654, 0x1, 0x2, p)
    568. 

  568. #define MX6UL_PAD_LCD_DATA16__CSI_DATA01(p)                          PIN_CFG(0x0158, 0x03E4, 0x0000, 0x3, 0x0, p)
    569. 

  569. #define MX6UL_PAD_LCD_DATA16__EIM_DATA08(p)                          PIN_CFG(0x0158, 0x03E4, 0x0000, 0x4, 0x0, p)
    570. 

  570. #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21(p)                          PIN_CFG(0x0158, 0x03E4, 0x0000, 0x5, 0x0, p)
    571. 

  571. #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24(p)                        PIN_CFG(0x0158, 0x03E4, 0x0000, 0x6, 0x0, p)
    572. 

  572. #define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6(p)                        PIN_CFG(0x0158, 0x03E4, 0x0000, 0x8, 0x0, p)
    573. 

  573. #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17(p)                        PIN_CFG(0x015C, 0x03E8, 0x0000, 0x0, 0x0, p)
    574. 

  574. #define MX6UL_PAD_LCD_DATA17__UART7_RX(p)                            PIN_CFG(0x015C, 0x03E8, 0x0654, 0x1, 0x3, p)
    575. 

  575. #define MX6UL_PAD_LCD_DATA17__CSI_DATA00(p)                          PIN_CFG(0x015C, 0x03E8, 0x0000, 0x3, 0x0, p)
    576. 

  576. #define MX6UL_PAD_LCD_DATA17__EIM_DATA09(p)                          PIN_CFG(0x015C, 0x03E8, 0x0000, 0x4, 0x0, p)
    577. 

  577. #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22(p)                          PIN_CFG(0x015C, 0x03E8, 0x0000, 0x5, 0x0, p)
    578. 

  578. #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25(p)                        PIN_CFG(0x015C, 0x03E8, 0x0000, 0x6, 0x0, p)
    579. 

  579. #define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7(p)                        PIN_CFG(0x015C, 0x03E8, 0x0000, 0x8, 0x0, p)
    580. 

  580. #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18(p)                        PIN_CFG(0x0160, 0x03EC, 0x0000, 0x0, 0x0, p)
    581. 

  581. #define MX6UL_PAD_LCD_DATA18__PWM5_OUT(p)                            PIN_CFG(0x0160, 0x03EC, 0x0000, 0x1, 0x0, p)
    582. 

  582. #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO(p)                    PIN_CFG(0x0160, 0x03EC, 0x0000, 0x2, 0x0, p)
    583. 

  583. #define MX6UL_PAD_LCD_DATA18__CSI_DATA10(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x3, 0x0, p)
    584. 

  584. #define MX6UL_PAD_LCD_DATA18__EIM_DATA10(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x4, 0x0, p)
    585. 

  585. #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x5, 0x0, p)
    586. 

  586. #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26(p)                        PIN_CFG(0x0160, 0x03EC, 0x0000, 0x6, 0x0, p)
    587. 

  587. #define MX6UL_PAD_LCD_DATA18__USDHC2_CMD(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x8, 0x0, p)
    588. 

  588. #define MX6UL_PAD_LCD_DATA19__EIM_DATA11(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x4, 0x0, p)
    589. 

  589. #define MX6UL_PAD_LCD_DATA19__GPIO3_IO24(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x5, 0x0, p)
    590. 

  590. #define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27(p)                        PIN_CFG(0x0164, 0x03F0, 0x0000, 0x6, 0x0, p)
    591. 

  591. #define MX6UL_PAD_LCD_DATA19__USDHC2_CLK(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x8, 0x0, p)
    592. 

  592. #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19(p)                        PIN_CFG(0x0164, 0x03F0, 0x0000, 0x0, 0x0, p)
    593. 

  593. #define MX6UL_PAD_LCD_DATA19__PWM6_OUT(p)                            PIN_CFG(0x0164, 0x03F0, 0x0000, 0x1, 0x0, p)
    594. 

  594. #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY(p)                      PIN_CFG(0x0164, 0x03F0, 0x0000, 0x2, 0x0, p)
    595. 

  595. #define MX6UL_PAD_LCD_DATA19__CSI_DATA11(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x3, 0x0, p)
    596. 

  596. #define MX6UL_PAD_LCD_DATA20__EIM_DATA12(p)                          PIN_CFG(0x0168, 0x03F4, 0x0000, 0x4, 0x0, p)
    597. 

  597. #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25(p)                          PIN_CFG(0x0168, 0x03F4, 0x0000, 0x5, 0x0, p)
    598. 

  598. #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28(p)                        PIN_CFG(0x0168, 0x03F4, 0x0000, 0x6, 0x0, p)
    599. 

  599. #define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0(p)                        PIN_CFG(0x0168, 0x03F4, 0x0000, 0x8, 0x0, p)
    600. 

  600. #define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20(p)                        PIN_CFG(0x0168, 0x03F4, 0x0000, 0x0, 0x0, p)
    601. 

  601. #define MX6UL_PAD_LCD_DATA20__UART8_TX(p)                            PIN_CFG(0x0168, 0x03F4, 0x065C, 0x1, 0x2, p)
    602. 

  602. #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK(p)                         PIN_CFG(0x0168, 0x03F4, 0x0534, 0x2, 0x0, p)
    603. 

  603. #define MX6UL_PAD_LCD_DATA20__CSI_DATA12(p)                          PIN_CFG(0x0168, 0x03F4, 0x0000, 0x3, 0x0, p)
    604. 

  604. #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21(p)                        PIN_CFG(0x016C, 0x03F8, 0x0000, 0x0, 0x0, p)
    605. 

  605. #define MX6UL_PAD_LCD_DATA21__UART8_RX(p)                            PIN_CFG(0x016C, 0x03F8, 0x065C, 0x1, 0x3, p)
    606. 

  606. #define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x2, 0x0, p)
    607. 

  607. #define MX6UL_PAD_LCD_DATA21__CSI_DATA13(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x3, 0x0, p)
    608. 

  608. #define MX6UL_PAD_LCD_DATA21__EIM_DATA13(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x4, 0x0, p)
    609. 

  609. #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x5, 0x0, p)
    610. 

  610. #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29(p)                        PIN_CFG(0x016C, 0x03F8, 0x0000, 0x6, 0x0, p)
    611. 

  611. #define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1(p)                        PIN_CFG(0x016C, 0x03F8, 0x0000, 0x8, 0x0, p)
    612. 

  612. #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22(p)                        PIN_CFG(0x0170, 0x03FC, 0x0000, 0x0, 0x0, p)
    613. 

  613. #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT(p)                           PIN_CFG(0x0170, 0x03FC, 0x0000, 0x1, 0x0, p)
    614. 

  614. #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI(p)                         PIN_CFG(0x0170, 0x03FC, 0x053C, 0x2, 0x0, p)
    615. 

  615. #define MX6UL_PAD_LCD_DATA22__CSI_DATA14(p)                          PIN_CFG(0x0170, 0x03FC, 0x0000, 0x3, 0x0, p)
    616. 

  616. #define MX6UL_PAD_LCD_DATA22__EIM_DATA14(p)                          PIN_CFG(0x0170, 0x03FC, 0x0000, 0x4, 0x0, p)
    617. 

  617. #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27(p)                          PIN_CFG(0x0170, 0x03FC, 0x0000, 0x5, 0x0, p)
    618. 

  618. #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30(p)                        PIN_CFG(0x0170, 0x03FC, 0x0000, 0x6, 0x0, p)
    619. 

  619. #define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2(p)                        PIN_CFG(0x0170, 0x03FC, 0x0000, 0x8, 0x0, p)
    620. 

  620. #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23(p)                        PIN_CFG(0x0174, 0x0400, 0x0000, 0x0, 0x0, p)
    621. 

  621. #define MX6UL_PAD_LCD_DATA23__MQS_LEFT(p)                            PIN_CFG(0x0174, 0x0400, 0x0000, 0x1, 0x0, p)
    622. 

  622. #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO(p)                         PIN_CFG(0x0174, 0x0400, 0x0538, 0x2, 0x0, p)
    623. 

  623. #define MX6UL_PAD_LCD_DATA23__CSI_DATA15(p)                          PIN_CFG(0x0174, 0x0400, 0x0000, 0x3, 0x0, p)
    624. 

  624. #define MX6UL_PAD_LCD_DATA23__EIM_DATA15(p)                          PIN_CFG(0x0174, 0x0400, 0x0000, 0x4, 0x0, p)
    625. 

  625. #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28(p)                          PIN_CFG(0x0174, 0x0400, 0x0000, 0x5, 0x0, p)
    626. 

  626. #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31(p)                        PIN_CFG(0x0174, 0x0400, 0x0000, 0x6, 0x0, p)
    627. 

  627. #define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3(p)                        PIN_CFG(0x0174, 0x0400, 0x0000, 0x8, 0x0, p)
    628. 

  628. #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B(p)                         PIN_CFG(0x0178, 0x0404, 0x0000, 0x0, 0x0, p)
    629. 

  629. #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK(p)                           PIN_CFG(0x0178, 0x0404, 0x0670, 0x1, 0x2, p)
    630. 

  630. #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK(p)                          PIN_CFG(0x0178, 0x0404, 0x0000, 0x2, 0x0, p)
    631. 

  631. #define MX6UL_PAD_NAND_RE_B__KPP_ROW00(p)                            PIN_CFG(0x0178, 0x0404, 0x0000, 0x3, 0x0, p)
    632. 

  632. #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00(p)                           PIN_CFG(0x0178, 0x0404, 0x0000, 0x4, 0x0, p)
    633. 

  633. #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00(p)                           PIN_CFG(0x0178, 0x0404, 0x0000, 0x5, 0x0, p)
    634. 

  634. #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2(p)                           PIN_CFG(0x0178, 0x0404, 0x0000, 0x8, 0x0, p)
    635. 

  635. #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B(p)                         PIN_CFG(0x017C, 0x0408, 0x0000, 0x0, 0x0, p)
    636. 

  636. #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD(p)                           PIN_CFG(0x017C, 0x0408, 0x0678, 0x1, 0x2, p)
    637. 

  637. #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B(p)                         PIN_CFG(0x017C, 0x0408, 0x0000, 0x2, 0x0, p)
    638. 

  638. #define MX6UL_PAD_NAND_WE_B__KPP_COL00(p)                            PIN_CFG(0x017C, 0x0408, 0x0000, 0x3, 0x0, p)
    639. 

  639. #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01(p)                           PIN_CFG(0x017C, 0x0408, 0x0000, 0x4, 0x0, p)
    640. 

  640. #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01(p)                           PIN_CFG(0x017C, 0x0408, 0x0000, 0x5, 0x0, p)
    641. 

  641. #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3(p)                           PIN_CFG(0x017C, 0x0408, 0x0000, 0x8, 0x0, p)
    642. 

  642. #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00(p)                     PIN_CFG(0x0180, 0x040C, 0x0000, 0x0, 0x0, p)
    643. 

  643. #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0(p)                       PIN_CFG(0x0180, 0x040C, 0x067C, 0x1, 0x2, p)
    644. 

  644. #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B(p)                       PIN_CFG(0x0180, 0x040C, 0x0000, 0x2, 0x0, p)
    645. 

  645. #define MX6UL_PAD_NAND_DATA00__KPP_ROW01(p)                          PIN_CFG(0x0180, 0x040C, 0x0000, 0x3, 0x0, p)
    646. 

  646. #define MX6UL_PAD_NAND_DATA00__EIM_AD08(p)                           PIN_CFG(0x0180, 0x040C, 0x0000, 0x4, 0x0, p)
    647. 

  647. #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02(p)                         PIN_CFG(0x0180, 0x040C, 0x0000, 0x5, 0x0, p)
    648. 

  648. #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY(p)                         PIN_CFG(0x0180, 0x040C, 0x0000, 0x8, 0x0, p)
    649. 

  649. #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01(p)                     PIN_CFG(0x0184, 0x0410, 0x0000, 0x0, 0x0, p)
    650. 

  650. #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1(p)                       PIN_CFG(0x0184, 0x0410, 0x0680, 0x1, 0x2, p)
    651. 

  651. #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS(p)                         PIN_CFG(0x0184, 0x0410, 0x0000, 0x2, 0x0, p)
    652. 

  652. #define MX6UL_PAD_NAND_DATA01__KPP_COL01(p)                          PIN_CFG(0x0184, 0x0410, 0x0000, 0x3, 0x0, p)
    653. 

  653. #define MX6UL_PAD_NAND_DATA01__EIM_AD09(p)                           PIN_CFG(0x0184, 0x0410, 0x0000, 0x4, 0x0, p)
    654. 

  654. #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03(p)                         PIN_CFG(0x0184, 0x0410, 0x0000, 0x5, 0x0, p)
    655. 

  655. #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1(p)                         PIN_CFG(0x0184, 0x0410, 0x0000, 0x8, 0x0, p)
    656. 

  656. #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02(p)                     PIN_CFG(0x0188, 0x0414, 0x0000, 0x0, 0x0, p)
    657. 

  657. #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2(p)                       PIN_CFG(0x0188, 0x0414, 0x0684, 0x1, 0x1, p)
    658. 

  658. #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00(p)                      PIN_CFG(0x0188, 0x0414, 0x0000, 0x2, 0x0, p)
    659. 

  659. #define MX6UL_PAD_NAND_DATA02__KPP_ROW02(p)                          PIN_CFG(0x0188, 0x0414, 0x0000, 0x3, 0x0, p)
    660. 

  660. #define MX6UL_PAD_NAND_DATA02__EIM_AD10(p)                           PIN_CFG(0x0188, 0x0414, 0x0000, 0x4, 0x0, p)
    661. 

  661. #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04(p)                         PIN_CFG(0x0188, 0x0414, 0x0000, 0x5, 0x0, p)
    662. 

  662. #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2(p)                         PIN_CFG(0x0188, 0x0414, 0x0000, 0x8, 0x0, p)
    663. 

  663. #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03(p)                     PIN_CFG(0x018C, 0x0418, 0x0000, 0x0, 0x0, p)
    664. 

  664. #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3(p)                       PIN_CFG(0x018C, 0x0418, 0x0688, 0x1, 0x2, p)
    665. 

  665. #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01(p)                      PIN_CFG(0x018C, 0x0418, 0x0000, 0x2, 0x0, p)
    666. 

  666. #define MX6UL_PAD_NAND_DATA03__KPP_COL02(p)                          PIN_CFG(0x018C, 0x0418, 0x0000, 0x3, 0x0, p)
    667. 

  667. #define MX6UL_PAD_NAND_DATA03__EIM_AD11(p)                           PIN_CFG(0x018C, 0x0418, 0x0000, 0x4, 0x0, p)
    668. 

  668. #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05(p)                         PIN_CFG(0x018C, 0x0418, 0x0000, 0x5, 0x0, p)
    669. 

  669. #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3(p)                         PIN_CFG(0x018C, 0x0418, 0x0000, 0x8, 0x0, p)
    670. 

  670. #define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04(p)                     PIN_CFG(0x0190, 0x041C, 0x0000, 0x0, 0x0, p)
    671. 

  671. #define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4(p)                       PIN_CFG(0x0190, 0x041C, 0x068C, 0x1, 0x1, p)
    672. 

  672. #define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02(p)                      PIN_CFG(0x0190, 0x041C, 0x0000, 0x2, 0x0, p)
    673. 

  673. #define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK(p)                        PIN_CFG(0x0190, 0x041C, 0x0564, 0x3, 0x1, p)
    674. 

  674. #define MX6UL_PAD_NAND_DATA04__EIM_AD12(p)                           PIN_CFG(0x0190, 0x041C, 0x0000, 0x4, 0x0, p)
    675. 

  675. #define MX6UL_PAD_NAND_DATA04__GPIO4_IO06(p)                         PIN_CFG(0x0190, 0x041C, 0x0000, 0x5, 0x0, p)
    676. 

  676. #define MX6UL_PAD_NAND_DATA04__UART2_TX(p)                           PIN_CFG(0x0190, 0x041C, 0x0000, 0x8, 0x0, p)
    677. 

  677. #define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05(p)                     PIN_CFG(0x0194, 0x0420, 0x0000, 0x0, 0x0, p)
    678. 

  678. #define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5(p)                       PIN_CFG(0x0194, 0x0420, 0x0690, 0x1, 0x1, p)
    679. 

  679. #define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03(p)                      PIN_CFG(0x0194, 0x0420, 0x0000, 0x2, 0x0, p)
    680. 

  680. #define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI(p)                        PIN_CFG(0x0194, 0x0420, 0x056C, 0x3, 0x1, p)
    681. 

  681. #define MX6UL_PAD_NAND_DATA05__EIM_AD13(p)                           PIN_CFG(0x0194, 0x0420, 0x0000, 0x4, 0x0, p)
    682. 

  682. #define MX6UL_PAD_NAND_DATA05__GPIO4_IO07(p)                         PIN_CFG(0x0194, 0x0420, 0x0000, 0x5, 0x0, p)
    683. 

  683. #define MX6UL_PAD_NAND_DATA05__UART2_RX(p)                           PIN_CFG(0x0194, 0x0420, 0x0000, 0x8, 0x0, p)
    684. 

  684. #define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06(p)                     PIN_CFG(0x0198, 0x0424, 0x0000, 0x0, 0x0, p)
    685. 

  685. #define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6(p)                       PIN_CFG(0x0198, 0x0424, 0x0694, 0x1, 0x1, p)
    686. 

  686. #define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK(p)                       PIN_CFG(0x0198, 0x0424, 0x0000, 0x2, 0x0, p)
    687. 

  687. #define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO(p)                        PIN_CFG(0x0198, 0x0424, 0x0568, 0x3, 0x1, p)
    688. 

  688. #define MX6UL_PAD_NAND_DATA06__EIM_AD14(p)                           PIN_CFG(0x0198, 0x0424, 0x0000, 0x4, 0x0, p)
    689. 

  689. #define MX6UL_PAD_NAND_DATA06__GPIO4_IO08(p)                         PIN_CFG(0x0198, 0x0424, 0x0000, 0x5, 0x0, p)
    690. 

  690. #define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS(p)                      PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p)
    691. 

  691. #define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS(p)                      PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p)
    692. 

  692. #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07(p)                     PIN_CFG(0x019C, 0x0428, 0x0000, 0x0, 0x0, p)
    693. 

  693. #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7(p)                       PIN_CFG(0x019C, 0x0428, 0x0698, 0x1, 0x1, p)
    694. 

  694. #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B(p)                       PIN_CFG(0x019C, 0x0428, 0x0000, 0x2, 0x0, p)
    695. 

  695. #define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0(p)                         PIN_CFG(0x019C, 0x0428, 0x0000, 0x3, 0x0, p)
    696. 

  696. #define MX6UL_PAD_NAND_DATA07__EIM_AD15(p)                           PIN_CFG(0x019C, 0x0428, 0x0000, 0x4, 0x0, p)
    697. 

  697. #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09(p)                         PIN_CFG(0x019C, 0x0428, 0x0000, 0x5, 0x0, p)
    698. 

  698. #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS(p)                      PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p)
    699. 

  699. #define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS(p)                      PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p)
    700. 

  700. #define MX6UL_PAD_NAND_ALE__RAWNAND_ALE(p)                           PIN_CFG(0x01A0, 0x042C, 0x0000, 0x0, 0x0, p)
    701. 

  701. #define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B(p)                        PIN_CFG(0x01A0, 0x042C, 0x0000, 0x1, 0x0, p)
    702. 

  702. #define MX6UL_PAD_NAND_ALE__QSPI_A_DQS(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x2, 0x0, p)
    703. 

  703. #define MX6UL_PAD_NAND_ALE__PWM3_OUT(p)                              PIN_CFG(0x01A0, 0x042C, 0x0000, 0x3, 0x0, p)
    704. 

  704. #define MX6UL_PAD_NAND_ALE__EIM_ADDR17(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x4, 0x0, p)
    705. 

  705. #define MX6UL_PAD_NAND_ALE__GPIO4_IO10(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x5, 0x0, p)
    706. 

  706. #define MX6UL_PAD_NAND_ALE__ECSPI3_SS1(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x8, 0x0, p)
    707. 

  707. #define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B(p)                         PIN_CFG(0x01A4, 0x0430, 0x0000, 0x0, 0x0, p)
    708. 

  708. #define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B(p)                       PIN_CFG(0x01A4, 0x0430, 0x0000, 0x1, 0x0, p)
    709. 

  709. #define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK(p)                          PIN_CFG(0x01A4, 0x0430, 0x0000, 0x2, 0x0, p)
    710. 

  710. #define MX6UL_PAD_NAND_WP_B__PWM4_OUT(p)                             PIN_CFG(0x01A4, 0x0430, 0x0000, 0x3, 0x0, p)
    711. 

  711. #define MX6UL_PAD_NAND_WP_B__EIM_BCLK(p)                             PIN_CFG(0x01A4, 0x0430, 0x0000, 0x4, 0x0, p)
    712. 

  712. #define MX6UL_PAD_NAND_WP_B__GPIO4_IO11(p)                           PIN_CFG(0x01A4, 0x0430, 0x0000, 0x5, 0x0, p)
    713. 

  713. #define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY(p)                           PIN_CFG(0x01A4, 0x0430, 0x0000, 0x8, 0x0, p)
    714. 

  714. #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B(p)                   PIN_CFG(0x01A8, 0x0434, 0x0000, 0x0, 0x0, p)
    715. 

  715. #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4(p)                      PIN_CFG(0x01A8, 0x0434, 0x0000, 0x1, 0x0, p)
    716. 

  716. #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00(p)                     PIN_CFG(0x01A8, 0x0434, 0x0000, 0x2, 0x0, p)
    717. 

  717. #define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0(p)                        PIN_CFG(0x01A8, 0x0434, 0x0000, 0x3, 0x0, p)
    718. 

  718. #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B(p)                         PIN_CFG(0x01A8, 0x0434, 0x0000, 0x4, 0x0, p)
    719. 

  719. #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12(p)                        PIN_CFG(0x01A8, 0x0434, 0x0000, 0x5, 0x0, p)
    720. 

  720. #define MX6UL_PAD_NAND_READY_B__UART3_TX(p)                          PIN_CFG(0x01A8, 0x0434, 0x0000, 0x8, 0x0, p)
    721. 

  721. #define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B(p)                       PIN_CFG(0x01AC, 0x0438, 0x0000, 0x0, 0x0, p)
    722. 

  722. #define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5(p)                        PIN_CFG(0x01AC, 0x0438, 0x0000, 0x1, 0x0, p)
    723. 

  723. #define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01(p)                       PIN_CFG(0x01AC, 0x0438, 0x0000, 0x2, 0x0, p)
    724. 

  724. #define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK(p)                         PIN_CFG(0x01AC, 0x0438, 0x0554, 0x3, 0x1, p)
    725. 

  725. #define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B(p)                         PIN_CFG(0x01AC, 0x0438, 0x0000, 0x4, 0x0, p)
    726. 

  726. #define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13(p)                          PIN_CFG(0x01AC, 0x0438, 0x0000, 0x5, 0x0, p)
    727. 

  727. #define MX6UL_PAD_NAND_CE0_B__UART3_RX(p)                            PIN_CFG(0x01AC, 0x0438, 0x0000, 0x8, 0x0, p)
    728. 

  728. #define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x0, 0x0, p)
    729. 

  729. #define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6(p)                        PIN_CFG(0x01B0, 0x043C, 0x0000, 0x1, 0x0, p)
    730. 

  730. #define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x2, 0x0, p)
    731. 

  731. #define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI(p)                         PIN_CFG(0x01B0, 0x043C, 0x055C, 0x3, 0x1, p)
    732. 

  732. #define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18(p)                          PIN_CFG(0x01B0, 0x043C, 0x0000, 0x4, 0x0, p)
    733. 

  733. #define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14(p)                          PIN_CFG(0x01B0, 0x043C, 0x0000, 0x5, 0x0, p)
    734. 

  734. #define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p)
    735. 

  735. #define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p)
    736. 

  736. #define MX6UL_PAD_NAND_CLE__RAWNAND_CLE(p)                           PIN_CFG(0x01B4, 0x0440, 0x0000, 0x0, 0x0, p)
    737. 

  737. #define MX6UL_PAD_NAND_CLE__USDHC1_DATA7(p)                          PIN_CFG(0x01B4, 0x0440, 0x0000, 0x1, 0x0, p)
    738. 

  738. #define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03(p)                         PIN_CFG(0x01B4, 0x0440, 0x0000, 0x2, 0x0, p)
    739. 

  739. #define MX6UL_PAD_NAND_CLE__ECSPI3_MISO(p)                           PIN_CFG(0x01B4, 0x0440, 0x0558, 0x3, 0x1, p)
    740. 

  740. #define MX6UL_PAD_NAND_CLE__EIM_ADDR16(p)                            PIN_CFG(0x01B4, 0x0440, 0x0000, 0x4, 0x0, p)
    741. 

  741. #define MX6UL_PAD_NAND_CLE__GPIO4_IO15(p)                            PIN_CFG(0x01B4, 0x0440, 0x0000, 0x5, 0x0, p)
    742. 

  742. #define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS(p)                         PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p)
    743. 

  743. #define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS(p)                         PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p)
    744. 

  744. #define MX6UL_PAD_NAND_DQS__RAWNAND_DQS(p)                           PIN_CFG(0x01B8, 0x0444, 0x0000, 0x0, 0x0, p)
    745. 

  745. #define MX6UL_PAD_NAND_DQS__CSI_FIELD(p)                             PIN_CFG(0x01B8, 0x0444, 0x0530, 0x1, 0x1, p)
    746. 

  746. #define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B(p)                          PIN_CFG(0x01B8, 0x0444, 0x0000, 0x2, 0x0, p)
    747. 

  747. #define MX6UL_PAD_NAND_DQS__PWM5_OUT(p)                              PIN_CFG(0x01B8, 0x0444, 0x0000, 0x3, 0x0, p)
    748. 

  748. #define MX6UL_PAD_NAND_DQS__EIM_WAIT(p)                              PIN_CFG(0x01B8, 0x0444, 0x0000, 0x4, 0x0, p)
    749. 

  749. #define MX6UL_PAD_NAND_DQS__GPIO4_IO16(p)                            PIN_CFG(0x01B8, 0x0444, 0x0000, 0x5, 0x0, p)
    750. 

  750. #define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01(p)                      PIN_CFG(0x01B8, 0x0444, 0x0000, 0x6, 0x0, p)
    751. 

  751. #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK(p)                         PIN_CFG(0x01B8, 0x0444, 0x0000, 0x8, 0x0, p)
    752. 

  752. #define MX6UL_PAD_SD1_CMD__USDHC1_CMD(p)                             PIN_CFG(0x01BC, 0x0448, 0x0000, 0x0, 0x0, p)
    753. 

  753. #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1(p)                          PIN_CFG(0x01BC, 0x0448, 0x0000, 0x1, 0x0, p)
    754. 

  754. #define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC(p)                           PIN_CFG(0x01BC, 0x0448, 0x0000, 0x2, 0x0, p)
    755. 

  755. #define MX6UL_PAD_SD1_CMD__SPDIF_OUT(p)                              PIN_CFG(0x01BC, 0x0448, 0x0000, 0x3, 0x0, p)
    756. 

  756. #define MX6UL_PAD_SD1_CMD__EIM_ADDR19(p)                             PIN_CFG(0x01BC, 0x0448, 0x0000, 0x4, 0x0, p)
    757. 

  757. #define MX6UL_PAD_SD1_CMD__GPIO2_IO16(p)                             PIN_CFG(0x01BC, 0x0448, 0x0000, 0x5, 0x0, p)
    758. 

  758. #define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00(p)                       PIN_CFG(0x01BC, 0x0448, 0x0000, 0x6, 0x0, p)
    759. 

  759. #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR(p)                           PIN_CFG(0x01BC, 0x0448, 0x0000, 0x8, 0x0, p)
    760. 

  760. #define MX6UL_PAD_SD1_CLK__USDHC1_CLK(p)                             PIN_CFG(0x01C0, 0x044C, 0x0000, 0x0, 0x0, p)
    761. 

  761. #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2(p)                          PIN_CFG(0x01C0, 0x044C, 0x0000, 0x1, 0x0, p)
    762. 

  762. #define MX6UL_PAD_SD1_CLK__SAI2_MCLK(p)                              PIN_CFG(0x01C0, 0x044C, 0x0000, 0x2, 0x0, p)
    763. 

  763. #define MX6UL_PAD_SD1_CLK__SPDIF_IN(p)                               PIN_CFG(0x01C0, 0x044C, 0x0618, 0x3, 0x3, p)
    764. 

  764. #define MX6UL_PAD_SD1_CLK__EIM_ADDR20(p)                             PIN_CFG(0x01C0, 0x044C, 0x0000, 0x4, 0x0, p)
    765. 

  765. #define MX6UL_PAD_SD1_CLK__GPIO2_IO17(p)                             PIN_CFG(0x01C0, 0x044C, 0x0000, 0x5, 0x0, p)
    766. 

  766. #define MX6UL_PAD_SD1_CLK__USB_OTG1_OC(p)                            PIN_CFG(0x01C0, 0x044C, 0x0000, 0x8, 0x0, p)
    767. 

  767. #define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0(p)                         PIN_CFG(0x01C4, 0x0450, 0x0000, 0x0, 0x0, p)
    768. 

  768. #define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3(p)                        PIN_CFG(0x01C4, 0x0450, 0x0000, 0x1, 0x0, p)
    769. 

  769. #define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC(p)                         PIN_CFG(0x01C4, 0x0450, 0x05FC, 0x2, 0x1, p)
    770. 

  770. #define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX(p)                          PIN_CFG(0x01C4, 0x0450, 0x0000, 0x3, 0x0, p)
    771. 

  771. #define MX6UL_PAD_SD1_DATA0__EIM_ADDR21(p)                           PIN_CFG(0x01C4, 0x0450, 0x0000, 0x4, 0x0, p)
    772. 

  772. #define MX6UL_PAD_SD1_DATA0__GPIO2_IO18(p)                           PIN_CFG(0x01C4, 0x0450, 0x0000, 0x5, 0x0, p)
    773. 

  773. #define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID(p)                       PIN_CFG(0x01C4, 0x0450, 0x0000, 0x8, 0x0, p)
    774. 

  774. #define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1(p)                         PIN_CFG(0x01C8, 0x0454, 0x0000, 0x0, 0x0, p)
    775. 

  775. #define MX6UL_PAD_SD1_DATA1__GPT2_CLK(p)                             PIN_CFG(0x01C8, 0x0454, 0x05A0, 0x1, 0x1, p)
    776. 

  776. #define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK(p)                         PIN_CFG(0x01C8, 0x0454, 0x05F8, 0x2, 0x1, p)
    777. 

  777. #define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX(p)                          PIN_CFG(0x01C8, 0x0454, 0x0584, 0x3, 0x3, p)
    778. 

  778. #define MX6UL_PAD_SD1_DATA1__EIM_ADDR22(p)                           PIN_CFG(0x01C8, 0x0454, 0x0000, 0x4, 0x0, p)
    779. 

  779. #define MX6UL_PAD_SD1_DATA1__GPIO2_IO19(p)                           PIN_CFG(0x01C8, 0x0454, 0x0000, 0x5, 0x0, p)
    780. 

  780. #define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR(p)                         PIN_CFG(0x01C8, 0x0454, 0x0000, 0x8, 0x0, p)
    781. 

  781. #define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2(p)                         PIN_CFG(0x01CC, 0x0458, 0x0000, 0x0, 0x0, p)
    782. 

  782. #define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1(p)                        PIN_CFG(0x01CC, 0x0458, 0x0598, 0x1, 0x1, p)
    783. 

  783. #define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA(p)                         PIN_CFG(0x01CC, 0x0458, 0x0000, 0x2, 0x0, p)
    784. 

  784. #define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX(p)                          PIN_CFG(0x01CC, 0x0458, 0x0000, 0x3, 0x0, p)
    785. 

  785. #define MX6UL_PAD_SD1_DATA2__EIM_ADDR23(p)                           PIN_CFG(0x01CC, 0x0458, 0x0000, 0x4, 0x0, p)
    786. 

  786. #define MX6UL_PAD_SD1_DATA2__GPIO2_IO20(p)                           PIN_CFG(0x01CC, 0x0458, 0x0000, 0x5, 0x0, p)
    787. 

  787. #define MX6UL_PAD_SD1_DATA2__CCM_CLKO1(p)                            PIN_CFG(0x01CC, 0x0458, 0x0000, 0x6, 0x0, p)
    788. 

  788. #define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC(p)                          PIN_CFG(0x01CC, 0x0458, 0x0000, 0x8, 0x0, p)
    789. 

  789. #define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3(p)                         PIN_CFG(0x01D0, 0x045C, 0x0000, 0x0, 0x0, p)
    790. 

  790. #define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2(p)                        PIN_CFG(0x01D0, 0x045C, 0x059C, 0x1, 0x1, p)
    791. 

  791. #define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA(p)                         PIN_CFG(0x01D0, 0x045C, 0x0000, 0x2, 0x0, p)
    792. 

  792. #define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX(p)                          PIN_CFG(0x01D0, 0x045C, 0x0588, 0x3, 0x3, p)
    793. 

  793. #define MX6UL_PAD_SD1_DATA3__EIM_ADDR24(p)                           PIN_CFG(0x01D0, 0x045C, 0x0000, 0x4, 0x0, p)
    794. 

  794. #define MX6UL_PAD_SD1_DATA3__GPIO2_IO21(p)                           PIN_CFG(0x01D0, 0x045C, 0x0000, 0x5, 0x0, p)
    795. 

  795. #define MX6UL_PAD_SD1_DATA3__CCM_CLKO2(p)                            PIN_CFG(0x01D0, 0x045C, 0x0000, 0x6, 0x0, p)
    796. 

  796. #define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID(p)                       PIN_CFG(0x01D0, 0x045C, 0x0000, 0x8, 0x0, p)
    797. 

  797. #define MX6UL_PAD_CSI_MCLK__CSI_MCLK(p)                              PIN_CFG(0x01D4, 0x0460, 0x0000, 0x0, 0x0, p)
    798. 

  798. #define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B(p)                           PIN_CFG(0x01D4, 0x0460, 0x0674, 0x1, 0x0, p)
    799. 

  799. #define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B(p)                         PIN_CFG(0x01D4, 0x0460, 0x0000, 0x2, 0x0, p)
    800. 

  800. #define MX6UL_PAD_CSI_MCLK__I2C1_SDA(p)                              PIN_CFG(0x01D4, 0x0460, 0x05A8, 0x3, 0x0, p)
    801. 

  801. #define MX6UL_PAD_CSI_MCLK__EIM_CS0_B(p)                             PIN_CFG(0x01D4, 0x0460, 0x0000, 0x4, 0x0, p)
    802. 

  802. #define MX6UL_PAD_CSI_MCLK__GPIO4_IO17(p)                            PIN_CFG(0x01D4, 0x0460, 0x0000, 0x5, 0x0, p)
    803. 

  803. #define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL(p)                     PIN_CFG(0x01D4, 0x0460, 0x0000, 0x6, 0x0, p)
    804. 

  804. #define MX6UL_PAD_CSI_MCLK__UART6_TX(p)                              PIN_CFG(0x01D4, 0x0460, 0x0000, 0x8, 0x0, p)
    805. 

  805. #define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK(p)                          PIN_CFG(0x01D8, 0x0464, 0x0528, 0x0, 0x1, p)
    806. 

  806. #define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP(p)                           PIN_CFG(0x01D8, 0x0464, 0x069C, 0x1, 0x2, p)
    807. 

  807. #define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B(p)                       PIN_CFG(0x01D8, 0x0464, 0x0000, 0x2, 0x0, p)
    808. 

  808. #define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL(p)                            PIN_CFG(0x01D8, 0x0464, 0x05A4, 0x3, 0x2, p)
    809. 

  809. #define MX6UL_PAD_CSI_PIXCLK__EIM_OE(p)                              PIN_CFG(0x01D8, 0x0464, 0x0000, 0x4, 0x0, p)
    810. 

  810. #define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18(p)                          PIN_CFG(0x01D8, 0x0464, 0x0000, 0x5, 0x0, p)
    811. 

  811. #define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5(p)                       PIN_CFG(0x01D8, 0x0464, 0x0000, 0x6, 0x0, p)
    812. 

  812. #define MX6UL_PAD_CSI_PIXCLK__UART6_RX(p)                            PIN_CFG(0x01D8, 0x0464, 0x0000, 0x8, 0x0, p)
    813. 

  813. #define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC(p)                            PIN_CFG(0x01DC, 0x0468, 0x052C, 0x0, 0x0, p)
    814. 

  814. #define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK(p)                           PIN_CFG(0x01DC, 0x0468, 0x0670, 0x1, 0x0, p)
    815. 

  815. #define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK(p)                       PIN_CFG(0x01DC, 0x0468, 0x0000, 0x2, 0x0, p)
    816. 

  816. #define MX6UL_PAD_CSI_VSYNC__I2C2_SDA(p)                             PIN_CFG(0x01DC, 0x0468, 0x05B0, 0x3, 0x0, p)
    817. 

  817. #define MX6UL_PAD_CSI_VSYNC__EIM_RW(p)                               PIN_CFG(0x01DC, 0x0468, 0x0000, 0x4, 0x0, p)
    818. 

  818. #define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19(p)                           PIN_CFG(0x01DC, 0x0468, 0x0000, 0x5, 0x0, p)
    819. 

  819. #define MX6UL_PAD_CSI_VSYNC__PWM7_OUT(p)                             PIN_CFG(0x01DC, 0x0468, 0x0000, 0x6, 0x0, p)
    820. 

  820. #define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS(p)                        PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p)
    821. 

  821. #define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS(p)                        PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p)
    822. 

  822. #define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC(p)                            PIN_CFG(0x01E0, 0x046C, 0x0524, 0x0, 0x0, p)
    823. 

  823. #define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD(p)                           PIN_CFG(0x01E0, 0x046C, 0x0678, 0x1, 0x0, p)
    824. 

  824. #define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD(p)                        PIN_CFG(0x01E0, 0x046C, 0x0000, 0x2, 0x0, p)
    825. 

  825. #define MX6UL_PAD_CSI_HSYNC__I2C2_SCL(p)                             PIN_CFG(0x01E0, 0x046C, 0x05AC, 0x3, 0x0, p)
    826. 

  826. #define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B(p)                            PIN_CFG(0x01E0, 0x046C, 0x0000, 0x4, 0x0, p)
    827. 

  827. #define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20(p)                           PIN_CFG(0x01E0, 0x046C, 0x0000, 0x5, 0x0, p)
    828. 

  828. #define MX6UL_PAD_CSI_HSYNC__PWM8_OUT(p)                             PIN_CFG(0x01E0, 0x046C, 0x0000, 0x6, 0x0, p)
    829. 

  829. #define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS(p)                        PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p)
    830. 

  830. #define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS(p)                        PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p)
    831. 

  831. #define MX6UL_PAD_CSI_DATA00__CSI_DATA02(p)                          PIN_CFG(0x01E4, 0x0470, 0x0000, 0x0, 0x0, p)
    832. 

  832. #define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0(p)                        PIN_CFG(0x01E4, 0x0470, 0x067C, 0x1, 0x0, p)
    833. 

  833. #define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B(p)                    PIN_CFG(0x01E4, 0x0470, 0x0000, 0x2, 0x0, p)
    834. 

  834. #define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK(p)                         PIN_CFG(0x01E4, 0x0470, 0x0544, 0x3, 0x0, p)
    835. 

  835. #define MX6UL_PAD_CSI_DATA00__EIM_AD00(p)                            PIN_CFG(0x01E4, 0x0470, 0x0000, 0x4, 0x0, p)
    836. 

  836. #define MX6UL_PAD_CSI_DATA00__GPIO4_IO21(p)                          PIN_CFG(0x01E4, 0x0470, 0x0000, 0x5, 0x0, p)
    837. 

  837. #define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT(p)                        PIN_CFG(0x01E4, 0x0470, 0x0000, 0x6, 0x0, p)
    838. 

  838. #define MX6UL_PAD_CSI_DATA00__UART5_TX(p)                            PIN_CFG(0x01E4, 0x0470, 0x0000, 0x8, 0x0, p)
    839. 

  839. #define MX6UL_PAD_CSI_DATA01__CSI_DATA03(p)                          PIN_CFG(0x01E8, 0x0474, 0x0000, 0x0, 0x0, p)
    840. 

  840. #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1(p)                        PIN_CFG(0x01E8, 0x0474, 0x0680, 0x1, 0x0, p)
    841. 

  841. #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN(p)                     PIN_CFG(0x01E8, 0x0474, 0x0000, 0x2, 0x0, p)
    842. 

  842. #define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0(p)                          PIN_CFG(0x01E8, 0x0474, 0x0000, 0x3, 0x0, p)
    843. 

  843. #define MX6UL_PAD_CSI_DATA01__EIM_AD01(p)                            PIN_CFG(0x01E8, 0x0474, 0x0000, 0x4, 0x0, p)
    844. 

  844. #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22(p)                          PIN_CFG(0x01E8, 0x0474, 0x0000, 0x5, 0x0, p)
    845. 

  845. #define MX6UL_PAD_CSI_DATA01__SAI1_MCLK(p)                           PIN_CFG(0x01E8, 0x0474, 0x0000, 0x6, 0x0, p)
    846. 

  846. #define MX6UL_PAD_CSI_DATA01__UART5_RX(p)                            PIN_CFG(0x01E8, 0x0474, 0x0000, 0x8, 0x0, p)
    847. 

  847. #define MX6UL_PAD_CSI_DATA02__CSI_DATA04(p)                          PIN_CFG(0x01EC, 0x0478, 0x0000, 0x0, 0x0, p)
    848. 

  848. #define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2(p)                        PIN_CFG(0x01EC, 0x0478, 0x0684, 0x1, 0x2, p)
    849. 

  849. #define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD(p)                     PIN_CFG(0x01EC, 0x0478, 0x0000, 0x2, 0x0, p)
    850. 

  850. #define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI(p)                         PIN_CFG(0x01EC, 0x0478, 0x054C, 0x3, 0x1, p)
    851. 

  851. #define MX6UL_PAD_CSI_DATA02__EIM_AD02(p)                            PIN_CFG(0x01EC, 0x0478, 0x0000, 0x4, 0x0, p)
    852. 

  852. #define MX6UL_PAD_CSI_DATA02__GPIO4_IO23(p)                          PIN_CFG(0x01EC, 0x0478, 0x0000, 0x5, 0x0, p)
    853. 

  853. #define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC(p)                        PIN_CFG(0x01EC, 0x0478, 0x0000, 0x6, 0x0, p)
    854. 

  854. #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS(p)                       PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p)
    855. 

  855. #define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS(p)                       PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p)
    856. 

  856. #define MX6UL_PAD_CSI_DATA03__CSI_DATA05(p)                          PIN_CFG(0x01F0, 0x047C, 0x0000, 0x0, 0x0, p)
    857. 

  857. #define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3(p)                        PIN_CFG(0x01F0, 0x047C, 0x0688, 0x1, 0x0, p)
    858. 

  858. #define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD(p)                       PIN_CFG(0x01F0, 0x047C, 0x0000, 0x2, 0x0, p)
    859. 

  859. #define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO(p)                         PIN_CFG(0x01F0, 0x047C, 0x0548, 0x3, 0x0, p)
    860. 

  860. #define MX6UL_PAD_CSI_DATA03__EIM_AD03(p)                            PIN_CFG(0x01F0, 0x047C, 0x0000, 0x4, 0x0, p)
    861. 

  861. #define MX6UL_PAD_CSI_DATA03__GPIO4_IO24(p)                          PIN_CFG(0x01F0, 0x047C, 0x0000, 0x5, 0x0, p)
    862. 

  862. #define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK(p)                        PIN_CFG(0x01F0, 0x047C, 0x0000, 0x6, 0x0, p)
    863. 

  863. #define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS(p)                       PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p)
    864. 

  864. #define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS(p)                       PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p)
    865. 

  865. #define MX6UL_PAD_CSI_DATA04__CSI_DATA06(p)                          PIN_CFG(0x01F4, 0x0480, 0x0000, 0x0, 0x0, p)
    866. 

  866. #define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4(p)                        PIN_CFG(0x01F4, 0x0480, 0x068C, 0x1, 0x2, p)
    867. 

  867. #define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK(p)                      PIN_CFG(0x01F4, 0x0480, 0x0000, 0x2, 0x0, p)
    868. 

  868. #define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK(p)                         PIN_CFG(0x01F4, 0x0480, 0x0534, 0x3, 0x1, p)
    869. 

  869. #define MX6UL_PAD_CSI_DATA04__EIM_AD04(p)                            PIN_CFG(0x01F4, 0x0480, 0x0000, 0x4, 0x0, p)
    870. 

  870. #define MX6UL_PAD_CSI_DATA04__GPIO4_IO25(p)                          PIN_CFG(0x01F4, 0x0480, 0x0000, 0x5, 0x0, p)
    871. 

  871. #define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC(p)                        PIN_CFG(0x01F4, 0x0480, 0x05EC, 0x6, 0x1, p)
    872. 

  872. #define MX6UL_PAD_CSI_DATA04__USDHC1_WP(p)                           PIN_CFG(0x01F4, 0x0480, 0x0000, 0x8, 0x0, p)
    873. 

  873. #define MX6UL_PAD_CSI_DATA05__CSI_DATA07(p)                          PIN_CFG(0x01F8, 0x0484, 0x0000, 0x0, 0x0, p)
    874. 

  874. #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5(p)                        PIN_CFG(0x01F8, 0x0484, 0x0690, 0x1, 0x2, p)
    875. 

  875. #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B(p)                    PIN_CFG(0x01F8, 0x0484, 0x0000, 0x2, 0x0, p)
    876. 

  876. #define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0(p)                          PIN_CFG(0x01F8, 0x0484, 0x0000, 0x3, 0x0, p)
    877. 

  877. #define MX6UL_PAD_CSI_DATA05__EIM_AD05(p)                            PIN_CFG(0x01F8, 0x0484, 0x0000, 0x4, 0x0, p)
    878. 

  878. #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26(p)                          PIN_CFG(0x01F8, 0x0484, 0x0000, 0x5, 0x0, p)
    879. 

  879. #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK(p)                        PIN_CFG(0x01F8, 0x0484, 0x05E8, 0x6, 0x1, p)
    880. 

  880. #define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B(p)                         PIN_CFG(0x01F8, 0x0484, 0x0000, 0x8, 0x0, p)
    881. 

  881. #define MX6UL_PAD_CSI_DATA06__CSI_DATA08(p)                          PIN_CFG(0x01FC, 0x0488, 0x0000, 0x0, 0x0, p)
    882. 

  882. #define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6(p)                        PIN_CFG(0x01FC, 0x0488, 0x0694, 0x1, 0x2, p)
    883. 

  883. #define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN(p)                     PIN_CFG(0x01FC, 0x0488, 0x0000, 0x2, 0x0, p)
    884. 

  884. #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI(p)                         PIN_CFG(0x01FC, 0x0488, 0x053C, 0x3, 0x1, p)
    885. 

  885. #define MX6UL_PAD_CSI_DATA06__EIM_AD06(p)                            PIN_CFG(0x01FC, 0x0488, 0x0000, 0x4, 0x0, p)
    886. 

  886. #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27(p)                          PIN_CFG(0x01FC, 0x0488, 0x0000, 0x5, 0x0, p)
    887. 

  887. #define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA(p)                        PIN_CFG(0x01FC, 0x0488, 0x0000, 0x6, 0x0, p)
    888. 

  888. #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B(p)                      PIN_CFG(0x01FC, 0x0488, 0x0000, 0x8, 0x0, p)
    889. 

  889. #define MX6UL_PAD_CSI_DATA07__CSI_DATA09(p)                          PIN_CFG(0x0200, 0x048C, 0x0000, 0x0, 0x0, p)
    890. 

  890. #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7(p)                        PIN_CFG(0x0200, 0x048C, 0x0698, 0x1, 0x2, p)
    891. 

  891. #define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD(p)                     PIN_CFG(0x0200, 0x048C, 0x0000, 0x2, 0x0, p)
    892. 

  892. #define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO(p)                         PIN_CFG(0x0200, 0x048C, 0x0538, 0x3, 0x1, p)
    893. 

  893. #define MX6UL_PAD_CSI_DATA07__EIM_AD07(p)                            PIN_CFG(0x0200, 0x048C, 0x0000, 0x4, 0x0, p)
    894. 

  894. #define MX6UL_PAD_CSI_DATA07__GPIO4_IO28(p)                          PIN_CFG(0x0200, 0x048C, 0x0000, 0x5, 0x0, p)
    895. 

  895. #define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA(p)                        PIN_CFG(0x0200, 0x048C, 0x0000, 0x6, 0x0, p)
    896. 

  896. #define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT(p)                      PIN_CFG(0x0200, 0x048C, 0x0000, 0x8, 0x0, p)
    897. 

  897. 

  898. /*
    899. 

  899.  * The TAMPER Pin can be used for GPIO, which depends on
    900. 

  900.  * TAMPER_PIN_DISABLE[1:0] settings.
    901. 

  901.  */
    902. 

  902. #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00(p)                        PIN_CFG(0x001C, 0x02A8, 0x0000, 0x5, 0x0, p)
    903. 

  903. #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01(p)                        PIN_CFG(0x0020, 0x02AC, 0x0000, 0x5, 0x0, p)
    904. 

  904. #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02(p)                        PIN_CFG(0x0024, 0x02B0, 0x0000, 0x5, 0x0, p)
    905. 

  905. #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03(p)                        PIN_CFG(0x0028, 0x02B4, 0x0000, 0x5, 0x0, p)
    906. 

  906. #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04(p)                        PIN_CFG(0x002C, 0x02B8, 0x0000, 0x5, 0x0, p)
    907. 

  907. #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05(p)                        PIN_CFG(0x0030, 0x02BC, 0x0000, 0x5, 0x0, p)
    908. 

  908. #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06(p)                        PIN_CFG(0x0034, 0x02C0, 0x0000, 0x5, 0x0, p)
    909. 

  909. #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07(p)                        PIN_CFG(0x0038, 0x02C4, 0x0000, 0x5, 0x0, p)
    910. 

  910. #define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08(p)                        PIN_CFG(0x003C, 0x02C8, 0x0000, 0x5, 0x0, p)
    911. 

  911. #define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09(p)                        PIN_CFG(0x0040, 0x02CC, 0x0000, 0x5, 0x0, p)
    912. 

  912. #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10(p)                          PIN_CFG(0x0014, 0x02A0, 0x0000, 0x5, 0x0, p)
    913. 

  913. #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11(p)                          PIN_CFG(0x0018, 0x02A4, 0x0000, 0x5, 0x0, p)
    914. 

  914. 

  915. #endif /* __DTS_IMX6UL_PINFUNC_H */
    916.