iomux_define.h 2.6 KB

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  1. #ifndef _IOMUX_DEFINE_H_
  2. #define _IOMUX_DEFINE_H_
  3. #include "soc_memory_map.h"
  4. // IOMUXC_SW_MUX_CTL_PAD_*
  5. // SION
  6. #define SION_DISABLED 0x0
  7. #define SION_ENABLED 0x1
  8. // MUX_MODE
  9. #define ALT0 0x0
  10. #define ALT1 0x1
  11. #define ALT2 0x2
  12. #define ALT3 0x3
  13. #define ALT4 0x4
  14. #define ALT5 0x5
  15. #define ALT6 0x6
  16. #define ALT7 0x7
  17. // IOMUXC_SW_PAD_CTL_PAD_*
  18. // IOMUXC_SW_PAD_CTL_GRP_*
  19. // LVE
  20. #define LVE_DISABLED 0x0
  21. #define LVE_ENABLED 0x1
  22. // HYS
  23. #define HYS_DISABLED 0x0
  24. #define HYS_ENABLED 0x1
  25. // PUS
  26. #define PUS_100KOHM_PD 0x0
  27. #define PUS_47KOHM_PU 0x1
  28. #define PUS_100KOHM_PU 0x2
  29. #define PUS_22KOHM_PU 0x3
  30. // PUE
  31. #define PUE_KEEP 0x0
  32. #define PUE_PULL 0x1
  33. // PKE
  34. #define PKE_DISABLED 0x0
  35. #define PKE_ENABLED 0x1
  36. // ODE
  37. #define ODE_DISABLED 0x0
  38. #define ODE_ENABLED 0x1
  39. // SPEED
  40. #define SPD_TBD 0x0
  41. #define SPD_50MHZ 0x1
  42. #define SPD_100MHZ 0x2
  43. #define SPD_200MHZ 0x3
  44. // DSE
  45. #define DSE_DISABLED 0x0
  46. #define DSE_240OHM 0x1
  47. #define DSE_120OHM 0x2
  48. #define DSE_80OHM 0x3
  49. #define DSE_60OHM 0x4
  50. #define DSE_48OHM 0x5
  51. #define DSE_40OHM 0x6
  52. #define DSE_34OHM 0x7
  53. // SRE
  54. #define SRE_SLOW 0x0
  55. #define SRE_FAST 0x1
  56. // ODT
  57. #define ODT_OFF 0x0
  58. #define ODT_120OHM 0x1
  59. #define ODT_60OHM 0x2
  60. #define ODT_40OHM 0x3
  61. #define ODT_30OHM 0x4
  62. #define ODT_RES5 0x5
  63. #define ODT_20OHM 0x6
  64. #define ODT_RES7 0x7
  65. // DDR_INPUT
  66. #define DDR_INPUT_CMOS 0x0
  67. #define DDR_INPUT_DIFF 0x1
  68. // DDR_SEL
  69. #define DDR_SEL_LPDDR1_DDR3_DDR2_ODT 0x0
  70. #define DDR_SEL_DDR2 0x1
  71. #define DDR_SEL_LPDDR2 0x2
  72. #define DDR_SEL_RES0 0x3
  73. // DO_TRIM
  74. #define DO_TRIM_RES0 0x0
  75. #define DO_TRIM_RES1 0x1
  76. #define MK_PAD(HYS, PUS, PUE, PKE, ODE, SPEED, DSE, SRE) ( \
  77. ((HYS & 0x1) << 16) | \
  78. ((PUS & 0x3) << 14) | \
  79. ((PUE & 0x1) << 13) | \
  80. ((PKE & 0x1) << 12) | \
  81. ((ODE & 0x1) << 11) | \
  82. ((SPEED & 0x3) << 6 ) | \
  83. ((DSE & 0x7) << 3 ) | \
  84. ((SRE & 0x1) << 0 ) )
  85. #define PAD_ENET_INPUT MK_PAD(1, 0, 0, 0, 0, 3, 5, 1)
  86. #define PAD_ENET_OUTPUT MK_PAD(0, 0, 0, 0, 0, 3, 5, 1)
  87. #define PAD_ENET_CTRL MK_PAD(0, 0, 0, 0, 0, 0, 3, 1)
  88. #define PAD_GPIO_OUTPUT MK_PAD(0, 0, 0, 0, 0, 0, 2, 0)
  89. #define PAD_GPIO_INPUT MK_PAD(0, 1, 1, 1, 0, 0, 2, 0)
  90. #define PAD_UART_OUTPUT MK_PAD(0, 0, 0, 0, 0, 0, 2, 0)
  91. #define PAD_UART_INPUT MK_PAD(0, 2, 0, 0, 0, 0, 2, 0)
  92. #define PAD_I2C MK_PAD(0, 2, 0, 0, 1, 0, 2, 0)
  93. #define PAD_I2C4 MK_PAD(0, 2, 0, 0, 1, 0, 4, 0)
  94. #define PAD_LCD_DATA MK_PAD(0, 0, 0, 0, 0, 2, 3, 1)
  95. #define PAD_AUDMUX MK_PAD(0, 0, 0, 0, 0, 0, 5, 1)
  96. #define PAD_CAN MK_PAD(0, 0, 0, 0, 0, 0, 2, 0)
  97. #define PAD_SDHC_DATA MK_PAD(0, 1, 1, 1, 0, 2, 3, 1)
  98. #define PAD_QSPI MK_PAD(0, 0, 0, 0, 0, 3, 3, 1)
  99. #define PAD_QSPI_PU MK_PAD(0, 1, 1, 1, 0, 3, 3, 1)
  100. #endif