cpuctrl_5410x.h 3.4 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
  1. /*
  2. * @brief LPC5410X CPU multi-core support driver
  3. *
  4. * @note
  5. * Copyright(C) NXP Semiconductors, 2014
  6. * All rights reserved.
  7. *
  8. * @par
  9. * Software that is described herein is for illustrative purposes only
  10. * which provides customers with programming information regarding the
  11. * LPC products. This software is supplied "AS IS" without any warranties of
  12. * any kind, and NXP Semiconductors and its licensor disclaim any and
  13. * all warranties, express or implied, including all implied warranties of
  14. * merchantability, fitness for a particular purpose and non-infringement of
  15. * intellectual property rights. NXP Semiconductors assumes no responsibility
  16. * or liability for the use of the software, conveys no license or rights under any
  17. * patent, copyright, mask work right, or any other intellectual property rights in
  18. * or to any products. NXP Semiconductors reserves the right to make changes
  19. * in the software without notification. NXP Semiconductors also makes no
  20. * representation or warranty that such application will be suitable for the
  21. * specified use without further testing or modification.
  22. *
  23. * @par
  24. * Permission to use, copy, modify, and distribute this software and its
  25. * documentation is hereby granted, under NXP Semiconductors' and its
  26. * licensor's relevant copyrights in the software, without fee, provided that it
  27. * is used in conjunction with NXP Semiconductors microcontrollers. This
  28. * copyright, permission, and disclaimer notice must appear in all copies of
  29. * this code.
  30. */
  31. #ifndef __CPUCTRL_5410X_H_
  32. #define __CPUCTRL_5410X_H_
  33. #ifdef __cplusplus
  34. extern "C" {
  35. #endif
  36. /** @defgroup CPUCTRL_5410X CHIP: LPC5410X CPU multi-core support driver
  37. * @ingroup CHIP_5410X_DRIVERS
  38. * This driver helps with determine which MCU core the software is running,
  39. * whether the MCU core is in master or slave mode, and provides functions
  40. * for master and slave core control.<br>
  41. *
  42. * The functions for the driver are provided as part of the
  43. * @ref POWER_LIBRARY_5410X library. For more information on using the
  44. * LPC5410x LPCopen package with multi-core, see @ref CHIP_5410X_MULTICORE<br>.
  45. * @{
  46. */
  47. /**
  48. * @brief Determine which MCU this code is running on
  49. * @return true if executing on the CM4, or false if executing on the CM0+
  50. */
  51. STATIC INLINE bool Chip_CPU_IsM4Core(void) {
  52. /* M4 core is designated by values 0xC24 on bits 15..4 */
  53. if (((SCB->CPUID >> 4) & 0xFFF) == 0xC24) {
  54. return true;
  55. }
  56. return false;
  57. }
  58. /**
  59. * @brief Determine if this core is a slave or master
  60. * @return true if this MCU is operating as the master, or false if operating as a slave
  61. */
  62. bool Chip_CPU_IsMasterCore(void);
  63. /**
  64. * @brief Setup M0+ boot and reset M0+ core
  65. * @param coentry : Pointer to boot entry point for M0+ core
  66. * @param costackptr : Pointer to where stack should be located for M0+ core
  67. * @return Nothing
  68. * @note Will setup boot stack and entry point, enable M0+ clock and then
  69. * reset M0+ core.
  70. */
  71. void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr);
  72. /**
  73. * @brief Setup M4 boot and reset M4 core
  74. * @param coentry : Pointer to boot entry point for M4 core
  75. * @param costackptr : Pointer to where stack should be located for M4 core
  76. * @return Nothing
  77. * @note Will setup boot stack and entry point, enable M4 clock and then
  78. * reset M0+ core.
  79. */
  80. void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr);
  81. /**
  82. * @}
  83. */
  84. #ifdef __cplusplus
  85. }
  86. #endif
  87. #endif /* __CPUCTRL_5410X_H_ */