inmux_5410x.h 6.3 KB

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  1. /*
  2. * @brief LPC5410X Input Mux Registers and Driver
  3. *
  4. * @note
  5. * Copyright(C) NXP Semiconductors, 2014
  6. * All rights reserved.
  7. *
  8. * @par
  9. * Software that is described herein is for illustrative purposes only
  10. * which provides customers with programming information regarding the
  11. * LPC products. This software is supplied "AS IS" without any warranties of
  12. * any kind, and NXP Semiconductors and its licensor disclaim any and
  13. * all warranties, express or implied, including all implied warranties of
  14. * merchantability, fitness for a particular purpose and non-infringement of
  15. * intellectual property rights. NXP Semiconductors assumes no responsibility
  16. * or liability for the use of the software, conveys no license or rights under any
  17. * patent, copyright, mask work right, or any other intellectual property rights in
  18. * or to any products. NXP Semiconductors reserves the right to make changes
  19. * in the software without notification. NXP Semiconductors also makes no
  20. * representation or warranty that such application will be suitable for the
  21. * specified use without further testing or modification.
  22. *
  23. * @par
  24. * Permission to use, copy, modify, and distribute this software and its
  25. * documentation is hereby granted, under NXP Semiconductors' and its
  26. * licensor's relevant copyrights in the software, without fee, provided that it
  27. * is used in conjunction with NXP Semiconductors microcontrollers. This
  28. * copyright, permission, and disclaimer notice must appear in all copies of
  29. * this code.
  30. */
  31. #ifndef __INMUX_5410X_H_
  32. #define __INMUX_5410X_H_
  33. #ifdef __cplusplus
  34. extern "C" {
  35. #endif
  36. /** @defgroup INMUX_5410X CHIP: LPC5410X Input Mux Registers and Driver
  37. * @ingroup CHIP_5410X_DRIVERS
  38. * @{
  39. */
  40. /**
  41. * @brief LPC5410X Input Mux Register Block Structure
  42. */
  43. typedef struct { /*!< INMUX Structure */
  44. __IO uint32_t RESERVED0[6];
  45. __I uint32_t RESERVED1[42];
  46. __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select registers */
  47. __IO uint32_t DMA_ITRIG_INMUX[22]; /*!< Input mux register for DMA trigger inputs */
  48. __I uint32_t RESERVED2[2];
  49. __IO uint32_t DMA_OTRIG_INMUX[4]; /*!< Input mux register for DMA trigger inputs */
  50. __I uint32_t RESERVED3[4];
  51. __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement ref clock */
  52. __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement target clock */
  53. } LPC_INMUX_T;
  54. /**
  55. * @brief GPIO Pin Interrupt Pin Select (sets PINTSEL register)
  56. * @param pintSel : GPIO PINTSEL interrupt, should be: 0 to 7
  57. * @param portNum : GPIO port number interrupt, should be: 0 to 1
  58. * @param pinNum : GPIO pin number Interrupt, should be: 0 to 31
  59. * @return Nothing
  60. */
  61. STATIC INLINE void Chip_INMUX_PinIntSel(uint8_t pintSel, uint8_t portNum, uint8_t pinNum)
  62. {
  63. LPC_INMUX->PINTSEL[pintSel] = (portNum * 32) + pinNum;
  64. }
  65. /* DMA triggers that can mapped to DMA channels */
  66. typedef enum {
  67. DMATRIG_ADC0_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */
  68. DMATRIG_ADC0_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */
  69. DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */
  70. DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */
  71. DMATRIG_TIMER0_MATCH0, /*!< Timer 0, match 0 trigger */
  72. DMATRIG_TIMER0_MATCH1, /*!< Timer 0, match 1 trigger */
  73. DMATRIG_TIMER1_MATCH0, /*!< Timer 1, match 0 trigger */
  74. DMATRIG_TIMER1_MATCH1, /*!< Timer 1, match 1 trigger */
  75. DMATRIG_TIMER2_MATCH0, /*!< Timer 2, match 0 trigger */
  76. DMATRIG_TIMER2_MATCH1, /*!< Timer 2, match 1 trigger */
  77. DMATRIG_TIMER3_MATCH0, /*!< Timer 3, match 0 trigger */
  78. DMATRIG_TIMER3_MATCH1, /*!< Timer 3, match 1 trigger */
  79. DMATRIG_TIMER4_MATCH0, /*!< Timer 4, match 0 trigger */
  80. DMATRIG_TIMER4_MATCH1, /*!< Timer 4, match 1 trigger */
  81. DMATRIG_PININT0, /*!< Pin interrupt 0 trigger */
  82. DMATRIG_PININT1, /*!< Pin interrupt 1 trigger */
  83. DMATRIG_PININT2, /*!< Pin interrupt 2 trigger */
  84. DMATRIG_PININT3, /*!< Pin interrupt 3 trigger */
  85. DMATRIG_OUTMUX0, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
  86. DMATRIG_OUTMUX1, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
  87. DMATRIG_OUTMUX2, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
  88. DMATRIG_OUTMUX3 /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
  89. } DMA_TRIGSRC_T;
  90. /**
  91. * @brief Select a trigger source for a DMA channel
  92. * @param ch : DMA channel number
  93. * @param trig : Trigger source for the DMA channel
  94. * @return Nothing
  95. */
  96. STATIC INLINE void Chip_INMUX_SetDMATrigger(uint8_t ch, DMA_TRIGSRC_T trig)
  97. {
  98. LPC_INMUX->DMA_ITRIG_INMUX[ch] = (uint32_t) trig;
  99. }
  100. /**
  101. * @brief Selects a DMA trigger source for the DMATRIG_OUTMUXn IDs
  102. * @param index : Select 0 to 3 to sets the source for DMATRIG_OUTMUX0 to DMATRIG_OUTMUX3
  103. * @param dmaCh : DMA channel to select for DMATRIG_OUTMUXn source
  104. * @return Nothing
  105. * @note This function sets the DMA trigger (out) source used with the DMATRIG_OUTMUXn
  106. * trigger source.
  107. */
  108. STATIC INLINE void Chip_INMUX_SetDMAOutMux(uint8_t index, uint8_t dmaCh)
  109. {
  110. LPC_INMUX->DMA_OTRIG_INMUX[index] = (uint32_t) dmaCh;
  111. }
  112. /* Freqeuency measure reference and target clock sources */
  113. typedef enum {
  114. FREQMSR_CLKIN = 0, /*!< CLKIN pin */
  115. FREQMSR_IRC, /*!< Internal RC (IRC) oscillator */
  116. FREQMSR_WDOSC, /*!< Watchdog oscillator */
  117. FREQMSR_32KHZOSC, /*!< 32KHz (RTC) oscillator rate */
  118. FREQ_MEAS_MAIN_CLK, /*!< main system clock */
  119. FREQMSR_PIO0_4, /*!< External pin PIO0_4 as input rate */
  120. FREQMSR_PIO0_20, /*!< External pin PIO0_20 as input rate */
  121. FREQMSR_PIO0_24, /*!< External pin PIO0_24 as input rate */
  122. FREQMSR_PIO1_4 /*!< External pin PIO1_4 as input rate */
  123. } FREQMSR_SRC_T;
  124. /**
  125. * @brief Selects a reference clock used with the frequency measure function
  126. * @param ref : Frequency measure function reference clock
  127. * @return Nothing
  128. */
  129. STATIC INLINE void Chip_INMUX_SetFreqMeasRefClock(FREQMSR_SRC_T ref)
  130. {
  131. LPC_INMUX->FREQMEAS_REF = (uint32_t) ref;
  132. }
  133. /**
  134. * @brief Selects a target clock used with the frequency measure function
  135. * @param targ : Frequency measure function reference clock
  136. * @return Nothing
  137. */
  138. STATIC INLINE void Chip_INMUX_SetFreqMeasTargClock(FREQMSR_SRC_T targ)
  139. {
  140. LPC_INMUX->FREQMEAS_TARGET = (uint32_t) targ;
  141. }
  142. /**
  143. * @}
  144. */
  145. #ifdef __cplusplus
  146. }
  147. #endif
  148. #endif /* __INMUX_5410X_H_ */