core_cm3.c 8.2 KB

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  1. /**************************************************************************//**
  2. * @file core_cm3.c
  3. * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
  4. * @version V1.40
  5. * @date 18. February 2010
  6. *
  7. * @note
  8. * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
  9. *
  10. * @par
  11. * ARM Limited (ARM) is supplying this software for use with Cortex-M
  12. * processor based microcontrollers. This file can be freely distributed
  13. * within development tools that are supporting such ARM based processors.
  14. *
  15. * @par
  16. * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  17. * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  18. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  19. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  20. * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  21. *
  22. ******************************************************************************/
  23. #include <stdint.h>
  24. /* define compiler specific symbols */
  25. #if defined ( __CC_ARM )
  26. #define __ASM __asm /*!< asm keyword for ARM Compiler */
  27. #define __INLINE __inline /*!< inline keyword for ARM Compiler */
  28. #elif defined ( __ICCARM__ )
  29. #define __ASM __asm /*!< asm keyword for IAR Compiler */
  30. #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
  31. #elif defined ( __GNUC__ )
  32. #define __ASM __asm /*!< asm keyword for GNU Compiler */
  33. #define __INLINE inline /*!< inline keyword for GNU Compiler */
  34. #elif defined ( __TASKING__ )
  35. #define __ASM __asm /*!< asm keyword for TASKING Compiler */
  36. #define __INLINE inline /*!< inline keyword for TASKING Compiler */
  37. #endif
  38. /* ########################## Core Instruction Access ######################### */
  39. #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
  40. /**
  41. * @brief Reverse byte order (16 bit)
  42. *
  43. * @param value value to reverse
  44. * @return reversed value
  45. *
  46. * Reverse byte order in unsigned short value
  47. */
  48. #if (__ARMCC_VERSION < 400677)
  49. __ASM uint32_t __REV16(uint16_t value)
  50. {
  51. rev16 r0, r0
  52. bx lr
  53. }
  54. #endif /* __ARMCC_VERSION */
  55. /**
  56. * @brief Reverse byte order in signed short value with sign extension to integer
  57. *
  58. * @param value value to reverse
  59. * @return reversed value
  60. *
  61. * Reverse byte order in signed short value with sign extension to integer
  62. */
  63. #if (__ARMCC_VERSION < 400677)
  64. __ASM int32_t __REVSH(int16_t value)
  65. {
  66. revsh r0, r0
  67. bx lr
  68. }
  69. #endif /* __ARMCC_VERSION */
  70. /**
  71. * @brief Remove the exclusive lock created by ldrex
  72. *
  73. * Removes the exclusive lock which is created by ldrex.
  74. */
  75. #if (__ARMCC_VERSION < 400000)
  76. __ASM void __CLREX(void)
  77. {
  78. clrex
  79. }
  80. #endif /* __ARMCC_VERSION */
  81. #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
  82. /* obsolete */
  83. #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
  84. /* obsolete */
  85. #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
  86. /* obsolete */
  87. #endif
  88. /* ########################### Core Function Access ########################### */
  89. #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
  90. /**
  91. * @brief Return the Control Register value
  92. *
  93. * @return Control value
  94. *
  95. * Return the content of the control register
  96. */
  97. #if (__ARMCC_VERSION < 400000)
  98. __ASM uint32_t __get_CONTROL(void)
  99. {
  100. mrs r0, control
  101. bx lr
  102. }
  103. #endif /* __ARMCC_VERSION */
  104. /**
  105. * @brief Set the Control Register value
  106. *
  107. * @param control Control value
  108. *
  109. * Set the control register
  110. */
  111. #if (__ARMCC_VERSION < 400000)
  112. __ASM void __set_CONTROL(uint32_t control)
  113. {
  114. msr control, r0
  115. bx lr
  116. }
  117. #endif /* __ARMCC_VERSION */
  118. /**
  119. * @brief Get IPSR Register value
  120. *
  121. * @return uint32_t IPSR value
  122. *
  123. * return the content of the IPSR register
  124. */
  125. #if (__ARMCC_VERSION < 400000)
  126. __ASM uint32_t __get_IPSR(void)
  127. {
  128. mrs r0, ipsr
  129. bx lr
  130. }
  131. #endif /* __ARMCC_VERSION */
  132. /**
  133. * @brief Get APSR Register value
  134. *
  135. * @return uint32_t APSR value
  136. *
  137. * return the content of the APSR register
  138. */
  139. #if (__ARMCC_VERSION < 400000)
  140. __ASM uint32_t __get_APSR(void)
  141. {
  142. mrs r0, apsr
  143. bx lr
  144. }
  145. #endif /* __ARMCC_VERSION */
  146. /**
  147. * @brief Get xPSR Register value
  148. *
  149. * @return uint32_t xPSR value
  150. *
  151. * return the content of the xPSR register
  152. */
  153. #if (__ARMCC_VERSION < 400000)
  154. __ASM uint32_t __get_xPSR(void)
  155. {
  156. mrs r0, xpsr
  157. bx lr
  158. }
  159. #endif /* __ARMCC_VERSION */
  160. /**
  161. * @brief Return the Process Stack Pointer
  162. *
  163. * @return ProcessStackPointer
  164. *
  165. * Return the actual process stack pointer
  166. */
  167. #if (__ARMCC_VERSION < 400000)
  168. __ASM uint32_t __get_PSP(void)
  169. {
  170. mrs r0, psp
  171. bx lr
  172. }
  173. #endif /* __ARMCC_VERSION */
  174. /**
  175. * @brief Set the Process Stack Pointer
  176. *
  177. * @param topOfProcStack Process Stack Pointer
  178. *
  179. * Assign the value ProcessStackPointer to the MSP
  180. * (process stack pointer) Cortex processor register
  181. */
  182. #if (__ARMCC_VERSION < 400000)
  183. __ASM void __set_PSP(uint32_t topOfProcStack)
  184. {
  185. msr psp, r0
  186. bx lr
  187. }
  188. #endif /* __ARMCC_VERSION */
  189. /**
  190. * @brief Return the Main Stack Pointer
  191. *
  192. * @return Main Stack Pointer
  193. *
  194. * Return the current value of the MSP (main stack pointer)
  195. * Cortex processor register
  196. */
  197. #if (__ARMCC_VERSION < 400000)
  198. __ASM uint32_t __get_MSP(void)
  199. {
  200. mrs r0, msp
  201. bx lr
  202. }
  203. #endif /* __ARMCC_VERSION */
  204. /**
  205. * @brief Set the Main Stack Pointer
  206. *
  207. * @param topOfMainStack Main Stack Pointer
  208. *
  209. * Assign the value mainStackPointer to the MSP
  210. * (main stack pointer) Cortex processor register
  211. */
  212. #if (__ARMCC_VERSION < 400000)
  213. __ASM void __set_MSP(uint32_t mainStackPointer)
  214. {
  215. msr msp, r0
  216. bx lr
  217. }
  218. #endif /* __ARMCC_VERSION */
  219. /**
  220. * @brief Return the Base Priority value
  221. *
  222. * @return BasePriority
  223. *
  224. * Return the content of the base priority register
  225. */
  226. #if (__ARMCC_VERSION < 400000)
  227. __ASM uint32_t __get_BASEPRI(void)
  228. {
  229. mrs r0, basepri
  230. bx lr
  231. }
  232. #endif /* __ARMCC_VERSION */
  233. /**
  234. * @brief Set the Base Priority value
  235. *
  236. * @param basePri BasePriority
  237. *
  238. * Set the base priority register
  239. */
  240. #if (__ARMCC_VERSION < 400000)
  241. __ASM void __set_BASEPRI(uint32_t basePri)
  242. {
  243. msr basepri, r0
  244. bx lr
  245. }
  246. #endif /* __ARMCC_VERSION */
  247. /**
  248. * @brief Return the Priority Mask value
  249. *
  250. * @return PriMask
  251. *
  252. * Return state of the priority mask bit from the priority mask register
  253. */
  254. #if (__ARMCC_VERSION < 400000)
  255. __ASM uint32_t __get_PRIMASK(void)
  256. {
  257. mrs r0, primask
  258. bx lr
  259. }
  260. #endif /* __ARMCC_VERSION */
  261. /**
  262. * @brief Set the Priority Mask value
  263. *
  264. * @param priMask PriMask
  265. *
  266. * Set the priority mask bit in the priority mask register
  267. */
  268. #if (__ARMCC_VERSION < 400000)
  269. __ASM void __set_PRIMASK(uint32_t priMask)
  270. {
  271. msr primask, r0
  272. bx lr
  273. }
  274. #endif /* __ARMCC_VERSION */
  275. /**
  276. * @brief Return the Fault Mask value
  277. *
  278. * @return FaultMask
  279. *
  280. * Return the content of the fault mask register
  281. */
  282. #if (__ARMCC_VERSION < 400000)
  283. __ASM uint32_t __get_FAULTMASK(void)
  284. {
  285. mrs r0, faultmask
  286. bx lr
  287. }
  288. #endif /* __ARMCC_VERSION */
  289. /**
  290. * @brief Set the Fault Mask value
  291. *
  292. * @param faultMask faultMask value
  293. *
  294. * Set the fault mask register
  295. */
  296. #if (__ARMCC_VERSION < 400000)
  297. __ASM void __set_FAULTMASK(uint32_t faultMask)
  298. {
  299. msr faultmask, r0
  300. bx lr
  301. }
  302. #endif /* __ARMCC_VERSION */
  303. /**
  304. * @brief Return the FPSCR value
  305. *
  306. * @return FloatingPointStatusControlRegister
  307. *
  308. * Return the content of the FPSCR register
  309. */
  310. /**
  311. * @brief Set the FPSCR value
  312. *
  313. * @param fpscr FloatingPointStatusControlRegister
  314. *
  315. * Set the FPSCR register
  316. */
  317. #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
  318. /* obsolete */
  319. #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
  320. /* obsolete */
  321. #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
  322. /* obsolete */
  323. #endif