dm9161.h 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778
  1. /*
  2. * File : dm9161.h
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. */
  13. #ifndef __DM9000_H__
  14. #define __DM9000_H__
  15. /*MACRO DEFINATIONS*/
  16. #define SEP4020_ID_EMAC ((unsigned int) 28) // Ethernet Mac
  17. /* Davicom 9161 PHY */
  18. #define MII_DM9161_ID 0x0181b880
  19. #define MII_DM9161A_ID 0x0181b8a0
  20. /* Davicom specific registers */
  21. #define MII_DSCR_REG 16
  22. #define MII_DSCSR_REG 17
  23. #define MII_DSINTR_REG 21
  24. /* Intel LXT971A PHY */
  25. #define MII_LXT971A_ID 0x001378E0
  26. /* Intel specific registers */
  27. #define MII_ISINTE_REG 18
  28. #define MII_ISINTS_REG 19
  29. #define MII_LEDCTRL_REG 20
  30. /* Realtek RTL8201 PHY */
  31. #define MII_RTL8201_ID 0x00008200
  32. /* Broadcom BCM5221 PHY */
  33. #define MII_BCM5221_ID 0x004061e0
  34. /* Broadcom specific registers */
  35. #define MII_BCMINTR_REG 26
  36. /* National Semiconductor DP83847 */
  37. #define MII_DP83847_ID 0x20005c30
  38. /* Altima AC101L PHY */
  39. #define MII_AC101L_ID 0x00225520
  40. /* Micrel KS8721 PHY */
  41. #define MII_KS8721_ID 0x00221610
  42. /* ........................................................................ */
  43. #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */
  44. #define MAX_RX_DESCR 20 /* max number of receive buffers */
  45. #define MAX_TBUFF_SZ 0x600 /* 1518 rounded up */
  46. #define MAX_TX_DESCR 20 /* max number of receive buffers */
  47. #define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */
  48. #define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
  49. #define EMAC_BROADCAST 0x80000000 /* broadcast address */
  50. #define EMAC_MULTICAST 0x40000000 /* multicast address */
  51. #define EMAC_UNICAST 0x20000000 /* unicast address */
  52. #define DM9161_inb(r) (*(volatile rt_uint8_t *)r)
  53. #define DM9161_outb(r, d) (*(volatile rt_uint8_t *)r = d)
  54. #define DM9161_inw(r) (*(volatile rt_uint16_t *)r)
  55. #define DM9161_outw(r, d) (*(volatile rt_uint16_t *)r = d)
  56. void rt_hw_dm9616_init(void);
  57. #endif