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clk.h

clk.h 46 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file     CLK.h
    3. 

  3.  * @version  V1.0
    4. 

  4.  * $Revision  1 $
    5. 

  5.  * $Date: 15/11/19 10:06a $
    6. 

  6.  * @brief    NUC472/NUC442 CLK Header File
    7. 

  7.  *
    8. 

  8.  * @note
    9. 

  9.  * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
    10. 

  10.  ******************************************************************************/
    11. 

  11. #ifndef __CLK_H__
    12. 

  12. #define __CLK_H__
    13. 

  13. 

  14. #ifdef __cplusplus
    15. 

  15. extern "C"
    16. 

  16. {
    17. 

  17. #endif
    18. 

  18. 

  19. 

  20. /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
    21. 

  21.   @{
    22. 

  22. */
    23. 

  23. 

  24. /** @addtogroup NUC472_442_CLK_Driver CLK Driver
    25. 

  25.   @{
    26. 

  26. */
    27. 

  27. 

  28. 

  29. /** @addtogroup NUC472_442_CLK_EXPORTED_CONSTANTS CLK Exported Constants
    30. 

  30. @{
    31. 

  31. */
    32. 

  32. 

  33. #define FREQ_500MHZ        500000000
    34. 

  34. #define FREQ_250MHZ        250000000
    35. 

  35. #define FREQ_200MHZ        200000000
    36. 

  36. #define FREQ_125MHZ        125000000
    37. 

  37. #define FREQ_72MHZ         72000000
    38. 

  38. #define FREQ_50MHZ         50000000
    39. 

  39. #define FREQ_25MHZ         25000000
    40. 

  40. #define FREQ_24MHZ         24000000
    41. 

  41. #define FREQ_22MHZ         22000000
    42. 

  42. #define FREQ_32KHZ         32000
    43. 

  43. #define FREQ_10KHZ         10000
    44. 

  44. 

  45. /*---------------------------------------------------------------------------------------------------------*/
    46. 

  46. /*  PLLCTL constant definitions. PLL = FIN * NF / NR / NO                                                  */
    47. 

  47. /*---------------------------------------------------------------------------------------------------------*/
    48. 

  48. #define CLK_PLLCTL_PLLSRC_HIRC (0x1UL<<CLK_PLLCTL_PLLSRC_Pos)        /*!< For PLL clock source is internal RC clock. 4MHz < FIN < 24MHz  \hideinitializer */
    49. 

  49. #define CLK_PLLCTL_PLLSRC_HXT  (0x0UL<<CLK_PLLCTL_PLLSRC_Pos)        /*!< For PLL clock source is external crystal.  4MHz < FIN < 24MHz  \hideinitializer */
    50. 

  50. 

  51. #define CLK_PLLCTL_NR(x)        (((x)-2)<<9)        /*!< x must be constant and 2 <= x <= 33.  1.6MHz < FIN/NR < 15MHz  \hideinitializer */
    52. 

  52. #define CLK_PLLCTL_NF(x)         ((x)-2)            /*!< x must be constant and 2 <= x <= 513. 100MHz < FIN*NF/NR < 200MHz. (120MHz < FIN*NF/NR < 200MHz is preferred.)  \hideinitializer */
    53. 

  53. 

  54. #define CLK_PLLCTL_NO_1         (0x0UL<<CLK_PLLCTL_OUTDV_Pos)             /*!< For output divider is 1  \hideinitializer */
    55. 

  55. #define CLK_PLLCTL_NO_2         (0x1UL<<CLK_PLLCTL_OUTDV_Pos)             /*!< For output divider is 2  \hideinitializer */
    56. 

  56. #define CLK_PLLCTL_NO_4         (0x3UL<<CLK_PLLCTL_OUTDV_Pos)             /*!< For output divider is 4  \hideinitializer */
    57. 

  57. 

  58. #if (__HXT == 12000000)
    59. 

  59. #define CLK_PLLCTL_FOR_I2S      (0xA54)                                                                                     /*!< Predefined PLLCTL setting for 147428571.428571Hz PLL output with 12MHz XTAL  \hideinitializer */
    60. 

  60. #define CLK_PLLCTL_84MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 28) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz XTAL  \hideinitializer */
    61. 

  61. #define CLK_PLLCTL_50MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 25) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50MHz PLL output with 12MHz XTAL  \hideinitializer */
    62. 

  62. #define CLK_PLLCTL_48MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF(112) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz XTAL  \hideinitializer */
    63. 

  63. #define CLK_PLLCTL_36MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF( 84) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 36MHz PLL output with 12MHz XTAL  \hideinitializer */
    64. 

  64. #define CLK_PLLCTL_32MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(6) | CLK_PLLCTL_NF( 64) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 32MHz PLL output with 12MHz XTAL  \hideinitializer */
    65. 

  65. #define CLK_PLLCTL_24MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 16) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 24MHz PLL output with 12MHz XTAL  \hideinitializer */
    66. 

  66. #else
    67. 

  67. # error "The PLL pre-definitions are only valid when external crystal is 12MHz"
    68. 

  68. #endif
    69. 

  69. 

  70. #define CLK_PLLCTL_50MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF( 59) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50.1918MHz PLL output with 22.1184MHz IRC  \hideinitializer */
    71. 

  71. #define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48.064985MHz PLL output with 22.1184MHz IRC \hideinitializer */
    72. 

  72. #define CLK_PLLCTL_36MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(12) | CLK_PLLCTL_NF( 78) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 35.9424MHz PLL output with 22.1184MHz IRC  \hideinitializer */
    73. 

  73. #define CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 9) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 31.9488MHz PLL output with 22.1184MHz IRC \hideinitializer */
    74. 

  74. #define CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 3) | CLK_PLLCTL_NF( 13) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 23.9616MHz PLL output with 22.1184MHz IRC \hideinitializer */
    75. 

  75. 

  76. /*---------------------------------------------------------------------------------------------------------*/
    77. 

  77. /*  PLL2CTL constant definitions.                                                                */
    78. 

  78. /*---------------------------------------------------------------------------------------------------------*/
    79. 

  79. #define CLK_PLL2CTL_PLL2DIV(x)       (((x)-1) << CLK_PLL2CTL_PLL2DIV_Pos) /*!< USBPLL clock frequency = (480 MHz) / 2 / (USB_N + 1). It could be 1~256,  Max. PLL frequency :480MHz / 2 when XTL12M.  \hideinitializer */
    80. 

  80. 

  81. /*---------------------------------------------------------------------------------------------------------*/
    82. 

  82. /*  CLKSEL0 constant definitions.  (Write-protection)                                                                         */
    83. 

  83. /*---------------------------------------------------------------------------------------------------------*/
    84. 

  84. #define CLK_CLKSEL0_HCLKSEL_HXT         (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL  \hideinitializer */
    85. 

  85. #define CLK_CLKSEL0_HCLKSEL_LXT         (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */
    86. 

  86. #define CLK_CLKSEL0_HCLKSEL_PLL         (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL output  \hideinitializer */
    87. 

  87. #define CLK_CLKSEL0_HCLKSEL_LIRC        (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 10KHz RC clock  \hideinitializer */
    88. 

  88. #define CLK_CLKSEL0_HCLKSEL_PLL2        (0x04UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as USBPLL clock  \hideinitializer */
    89. 

  89. #define CLK_CLKSEL0_HCLKSEL_HIRC        (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock  \hideinitializer */
    90. 

  90. 

  91. #define CLK_CLKSEL0_STCLKSEL_HXT         (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos)  /*!< Setting clock source as external XTAL  \hideinitializer */
    92. 

  92. #define CLK_CLKSEL0_STCLKSEL_LXT      (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos)  /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */
    93. 

  93. #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2    (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos)  /*!< Setting clock source as external XTAL/2  \hideinitializer */
    94. 

  94. #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2    (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos)  /*!< Setting clock source as HCLK/2  \hideinitializer */
    95. 

  95. #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2  (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos)  /*!< Setting clock source as internal 22.1184MHz RC clock/2  \hideinitializer */
    96. 

  96. #define CLK_CLKSEL0_STCLKSEL_HCLK      (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
    97. 

  97. 

  98. #define CLK_CLKSEL0_PCLKSEL_HCLK   (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos)    /*!< Setting clock source as HCLK  \hideinitializer */
    99. 

  99. #define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2  (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos)    /*!< Setting clock source as HCLK/2  \hideinitializer */
    100. 

  100. 

  101. #define CLK_CLKSEL0_USBHSEL_PLL   (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos)    /*!< Setting clock source as PLL   \hideinitializer */
    102. 

  102. #define CLK_CLKSEL0_USBHSEL_PLL2    (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos)    /*!< Setting clock source as PLL2  \hideinitializer */
    103. 

  103. 

  104. #define CLK_CLKSEL0_CAPSEL_HXT     (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as external XTAL  \hideinitializer */
    105. 

  105. #define CLK_CLKSEL0_CAPSEL_PLL     (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as PLL   \hideinitializer */
    106. 

  106. #define CLK_CLKSEL0_CAPSEL_HCLK    (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as HCLK  \hideinitializer */
    107. 

  107. #define CLK_CLKSEL0_CAPSEL_HIRC    (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as internal 22.1184MHz RC clock  \hideinitializer */
    108. 

  108. 

  109. #define CLK_CLKSEL0_ICAPSEL_HXT    (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as external XTAL  \hideinitializer */
    110. 

  110. #define CLK_CLKSEL0_ICAPSEL_PLL    (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as PLL   \hideinitializer */
    111. 

  111. #define CLK_CLKSEL0_ICAPSEL_HCLK   (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as HCLK  \hideinitializer */
    112. 

  112. #define CLK_CLKSEL0_ICAPSEL_HIRC   (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos)    /*!< Setting clock source as internal 22.1184MHz RC clock  \hideinitializer */
    113. 

  113. 

  114. #define CLK_CLKSEL0_SDHSEL_HXT    (0x00UL<<CLK_CLKSEL0_SDHSEL_Pos)    /*!< Setting clock source as external XTAL  \hideinitializer */
    115. 

  115. #define CLK_CLKSEL0_SDHSEL_PLL    (0x01UL<<CLK_CLKSEL0_SDHSEL_Pos)    /*!< Setting clock source as PLL2  \hideinitializer */
    116. 

  116. #define CLK_CLKSEL0_SDHSEL_HCLK   (0x02UL<<CLK_CLKSEL0_SDHSEL_Pos)    /*!< Setting clock source as HCLK  \hideinitializer */
    117. 

  117. #define CLK_CLKSEL0_SDHSEL_HIRC   (0x03UL<<CLK_CLKSEL0_SDHSEL_Pos)    /*!< Setting clock source as internal 22.1184MHz RC clock  \hideinitializer */
    118. 

  118. 

  119. /*---------------------------------------------------------------------------------------------------------*/
    120. 

  120. /*  CLKSEL1 constant definitions.                                                                          */
    121. 

  121. /*---------------------------------------------------------------------------------------------------------*/
    122. 

  122. #define CLK_CLKSEL1_WDTSEL_HXT       (0x0UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as external XTAL \hideinitializer */
    123. 

  123. #define CLK_CLKSEL1_WDTSEL_LXT       (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as external XTAL 32.768KHz \hideinitializer */
    124. 

  124. #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048  (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as HCLK/2048  \hideinitializer */
    125. 

  125. #define CLK_CLKSEL1_WDTSEL_LIRC        (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as internal 10KHz RC clock  \hideinitializer */
    126. 

  126. 

  127. #define CLK_CLKSEL1_ADCSEL_HXT          (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting ADC clock source as external XTAL  \hideinitializer */
    128. 

  128. #define CLK_CLKSEL1_ADCSEL_PLL           (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting ADC clock source as PLL  \hideinitializer */
    129. 

  129. #define CLK_CLKSEL1_ADCSEL_PCLK          (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting ADC clock source as PCLK  \hideinitializer */
    130. 

  130. #define CLK_CLKSEL1_ADCSEL_HIRC        (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting ADC clock source as internal 22.1184MHz RC clock  \hideinitializer */
    131. 

  131. 

  132. #define CLK_CLKSEL1_EADCSEL_HXT          (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting EADC clock source as external XTAL  \hideinitializer */
    133. 

  133. #define CLK_CLKSEL1_EADCSEL_PLL           (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting EADC clock source as PLL  \hideinitializer */
    134. 

  134. #define CLK_CLKSEL1_EADCSEL_PCLK          (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting EADC clock source as PCLK  \hideinitializer */
    135. 

  135. #define CLK_CLKSEL1_EADCSEL_HIRC        (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting EADC clock source as internal 22.1184MHz RC clock  \hideinitializer */
    136. 

  136. 

  137. #define CLK_CLKSEL1_SPI0SEL_PLL          (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos)       /*!< Setting SPI0 clock source as PLL  \hideinitializer */
    138. 

  138. #define CLK_CLKSEL1_SPI0SEL_PCLK         (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos)       /*!< Setting SPI0 clock source as PCLK  \hideinitializer */
    139. 

  139. 

  140. #define CLK_CLKSEL1_SPI1SEL_PLL          (0x0UL<<CLK_CLKSEL1_SPI1SEL_Pos)       /*!< Setting SPI1 clock source as PLL  \hideinitializer */
    141. 

  141. #define CLK_CLKSEL1_SPI1SEL_PCLK         (0x1UL<<CLK_CLKSEL1_SPI1SEL_Pos)       /*!< Setting SPI1 clock source as PCLK  \hideinitializer */
    142. 

  142. 

  143. #define CLK_CLKSEL1_SPI2SEL_PLL          (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos)       /*!< Setting SPI2 clock source as PLL  \hideinitializer */
    144. 

  144. #define CLK_CLKSEL1_SPI2SEL_PCLK         (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos)       /*!< Setting SPI2 clock source as PCLK  \hideinitializer */
    145. 

  145. 

  146. #define CLK_CLKSEL1_SPI3SEL_PLL          (0x0UL<<CLK_CLKSEL1_SPI3SEL_Pos)       /*!< Setting SPI3 clock source as PLL  \hideinitializer */
    147. 

  147. #define CLK_CLKSEL1_SPI3SEL_PCLK         (0x1UL<<CLK_CLKSEL1_SPI3SEL_Pos)       /*!< Setting SPI3 clock source as PCLK  \hideinitializer */
    148. 

  148. 

  149. #define CLK_CLKSEL1_TMR0SEL_HXT         (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)       /*!< Setting Timer 0 clock source as external XTAL  \hideinitializer */
    150. 

  150. #define CLK_CLKSEL1_TMR0SEL_LXT      (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)       /*!< Setting Timer 0 clock source as external XTAL 32.768KHz  \hideinitializer */
    151. 

  151. #define CLK_CLKSEL1_TMR0SEL_PCLK         (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)       /*!< Setting Timer 0 clock source as PCLK  \hideinitializer */
    152. 

  152. #define CLK_CLKSEL1_TMR0SEL_EXT      (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)       /*!< Setting Timer 0 clock source as external trigger  \hideinitializer */
    153. 

  153. #define CLK_CLKSEL1_TMR0SEL_LIRC       (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)       /*!< Setting Timer 0 clock source as internal 10KHz RC clock  \hideinitializer */
    154. 

  154. #define CLK_CLKSEL1_TMR0SEL_HIRC       (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos)       /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    155. 

  155. 

  156. #define CLK_CLKSEL1_TMR1SEL_HXT         (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as external XTAL  \hideinitializer */
    157. 

  157. #define CLK_CLKSEL1_TMR1SEL_LXT      (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as external XTAL 32.768KHz  \hideinitializer */
    158. 

  158. #define CLK_CLKSEL1_TMR1SEL_PCLK         (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as PCLK  \hideinitializer */
    159. 

  159. #define CLK_CLKSEL1_TMR1SEL_EXT     (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as external trigger  \hideinitializer */
    160. 

  160. #define CLK_CLKSEL1_TMR1SEL_LIRC       (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as internal 10KHz RC clock  \hideinitializer */
    161. 

  161. #define CLK_CLKSEL1_TMR1SEL_HIRC       (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    162. 

  162. 

  163. #define CLK_CLKSEL1_TMR2SEL_HXT         (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as external XTAL  \hideinitializer */
    164. 

  164. #define CLK_CLKSEL1_TMR2SEL_LXT      (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as external XTAL 32.768KHz  \hideinitializer */
    165. 

  165. #define CLK_CLKSEL1_TMR2SEL_PCLK         (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as PCLK  \hideinitializer */
    166. 

  166. #define CLK_CLKSEL1_TMR2SEL_EXT      (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as external trigger  \hideinitializer */
    167. 

  167. #define CLK_CLKSEL1_TMR2SEL_LIRC       (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as internal 10KHz RC clock  \hideinitializer */
    168. 

  168. #define CLK_CLKSEL1_TMR2SEL_HIRC       (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    169. 

  169. 

  170. #define CLK_CLKSEL1_TMR3SEL_HXT         (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos)      /*!< Setting Timer 3 clock source as external XTAL  \hideinitializer */
    171. 

  171. #define CLK_CLKSEL1_TMR3SEL_LXT      (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos)      /*!< Setting Timer 3 clock source as external XTAL 32.768KHz  \hideinitializer */
    172. 

  172. #define CLK_CLKSEL1_TMR3SEL_PCLK         (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos)      /*!< Setting Timer 3 clock source as PCLK  \hideinitializer */
    173. 

  173. #define CLK_CLKSEL1_TMR3SEL_EXT     (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos)      /*!< Setting Timer 3 clock source as external trigger  \hideinitializer */
    174. 

  174. #define CLK_CLKSEL1_TMR3SEL_LIRC       (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos)      /*!< Setting Timer 3 clock source as internal 10KHz RC clock  \hideinitializer */
    175. 

  175. #define CLK_CLKSEL1_TMR3SEL_HIRC       (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos)      /*!< Setting Timer 3 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    176. 

  176. 

  177. #define CLK_CLKSEL1_UARTSEL_HXT         (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos)      /*!< Setting UR clock source as external XTAL  \hideinitializer */
    178. 

  178. #define CLK_CLKSEL1_UARTSEL_PLL          (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos)      /*!< Setting UR clock source as external PLL  \hideinitializer */
    179. 

  179. #define CLK_CLKSEL1_UARTSEL_HIRC       (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos)      /*!< Setting UR clock source as external internal 22.1184MHz RC clock  \hideinitializer */
    180. 

  180. 

  181. #define CLK_CLKSEL1_CLKOSEL_HXT       (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos)      /*!< Setting CLKO clock source as external XTAL  \hideinitializer */
    182. 

  182. #define CLK_CLKSEL1_CLKOSEL_LXT    (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos)      /*!< Setting CLKO clock source as external XTAL 32.768KHz   \hideinitializer */
    183. 

  183. #define CLK_CLKSEL1_CLKOSEL_HCLK       (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos)      /*!< Setting CLKO clock source as HCLK  \hideinitializer */
    184. 

  184. #define CLK_CLKSEL1_CLKOSEL_HIRC     (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos)      /*!< Setting CLKO clock source as external internal 22.1184MHz RC clock  \hideinitializer */
    185. 

  185. 

  186. #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048  (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)       /*!< Setting CLKO clock source as  HCLK/2048  \hideinitializer */
    187. 

  187. #define CLK_CLKSEL1_WWDTSEL_LIRC        (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)       /*!< Setting CLKO clock source as internal 10KHz RC clock   \hideinitializer */
    188. 

  188. 

  189. 

  190. /*---------------------------------------------------------------------------------------------------------*/
    191. 

  191. /*  CLKSEL2 constant definitions.                                                                          */
    192. 

  192. /*---------------------------------------------------------------------------------------------------------*/
    193. 

  193. #define CLK_CLKSEL2_PWM0CH01SEL_HXT      (0x0UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as external XTAL  \hideinitializer */
    194. 

  194. #define CLK_CLKSEL2_PWM0CH01SEL_LXT    (0x1UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz  \hideinitializer */
    195. 

  195. #define CLK_CLKSEL2_PWM0CH01SEL_PCLK     (0x2UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as PCLK  \hideinitializer */
    196. 

  196. #define CLK_CLKSEL2_PWM0CH01SEL_HIRC   (0x3UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)     /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    197. 

  197. #define CLK_CLKSEL2_PWM0CH01SEL_LIRC   (0x7UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock  \hideinitializer */
    198. 

  198. 

  199. #define CLK_CLKSEL2_PWM0CH23SEL_HXT      (0x0UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as external XTAL  \hideinitializer */
    200. 

  200. #define CLK_CLKSEL2_PWM0CH23SEL_LXT    (0x1UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz  \hideinitializer */
    201. 

  201. #define CLK_CLKSEL2_PWM0CH23SEL_PCLK     (0x2UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as PCLK  \hideinitializer */
    202. 

  202. #define CLK_CLKSEL2_PWM0CH23SEL_HIRC   (0x3UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)     /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    203. 

  203. #define CLK_CLKSEL2_PWM0CH23SEL_LIRC   (0x7UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock  \hideinitializer */
    204. 

  204. 

  205. #define CLK_CLKSEL2_PWM0CH45SEL_HXT      (0x0UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as external XTAL  \hideinitializer */
    206. 

  206. #define CLK_CLKSEL2_PWM0CH45SEL_LXT    (0x1UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz  \hideinitializer */
    207. 

  207. #define CLK_CLKSEL2_PWM0CH45SEL_PCLK     (0x2UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as PCLK  \hideinitializer */
    208. 

  208. #define CLK_CLKSEL2_PWM0CH45SEL_HIRC   (0x3UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)     /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    209. 

  209. #define CLK_CLKSEL2_PWM0CH45SEL_LIRC   (0x7UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock  \hideinitializer */
    210. 

  210. 

  211. #define CLK_CLKSEL2_PWM1CH01SEL_HXT      (0x0UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as external XTAL  \hideinitializer */
    212. 

  212. #define CLK_CLKSEL2_PWM1CH01SEL_LXT    (0x1UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz  \hideinitializer */
    213. 

  213. #define CLK_CLKSEL2_PWM1CH01SEL_PCLK     (0x2UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as PCLK  \hideinitializer */
    214. 

  214. #define CLK_CLKSEL2_PWM1CH01SEL_HIRC   (0x3UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)     /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    215. 

  215. #define CLK_CLKSEL2_PWM1CH01SEL_LIRC   (0x7UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)   /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock  \hideinitializer */
    216. 

  216. 

  217. #define CLK_CLKSEL2_PWM1CH23SEL_HXT      (0x0UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as external XTAL  \hideinitializer */
    218. 

  218. #define CLK_CLKSEL2_PWM1CH23SEL_LXT    (0x1UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz  \hideinitializer */
    219. 

  219. #define CLK_CLKSEL2_PWM1CH23SEL_PCLK     (0x2UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as PCLK  \hideinitializer */
    220. 

  220. #define CLK_CLKSEL2_PWM1CH23SEL_HIRC   (0x3UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)     /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    221. 

  221. #define CLK_CLKSEL2_PWM1CH23SEL_LIRC   (0x7UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)   /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock  \hideinitializer */
    222. 

  222. 

  223. #define CLK_CLKSEL2_PWM1CH45SEL_HXT      (0x0UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as external XTAL  \hideinitializer */
    224. 

  224. #define CLK_CLKSEL2_PWM1CH45SEL_LXT    (0x1UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz  \hideinitializer */
    225. 

  225. #define CLK_CLKSEL2_PWM1CH45SEL_PCLK     (0x2UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as PCLK  \hideinitializer */
    226. 

  226. #define CLK_CLKSEL2_PWM1CH45SEL_HIRC   (0x3UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)     /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    227. 

  227. #define CLK_CLKSEL2_PWM1CH45SEL_LIRC   (0x7UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)   /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock  \hideinitializer */
    228. 

  228. 

  229. /*---------------------------------------------------------------------------------------------------------*/
    230. 

  230. /*  CLKSEL3 constant definitions.                                                                          */
    231. 

  231. /*---------------------------------------------------------------------------------------------------------*/
    232. 

  232. #define CLK_CLKSEL3_SC0SEL_HXT           (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos)      /*!< Setting SC0 clock source as external XTAL  \hideinitializer */
    233. 

  233. #define CLK_CLKSEL3_SC0SEL_PLL            (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos)      /*!< Setting SC0 clock source as PLL  \hideinitializer */
    234. 

  234. #define CLK_CLKSEL3_SC0SEL_PCLK           (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos)      /*!< Setting SC0 clock source as PCLK  \hideinitializer */
    235. 

  235. #define CLK_CLKSEL3_SC0SEL_HIRC         (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos)      /*!< Setting SC0 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    236. 

  236. 

  237. #define CLK_CLKSEL3_SC1SEL_HXT           (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos)      /*!< Setting SC1 clock source as external XTAL  \hideinitializer */
    238. 

  238. #define CLK_CLKSEL3_SC1SEL_PLL            (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos)      /*!< Setting SC1 clock source as PLL  \hideinitializer */
    239. 

  239. #define CLK_CLKSEL3_SC1SEL_PCLK           (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos)      /*!< Setting SC1 clock source as PCLK  \hideinitializer */
    240. 

  240. #define CLK_CLKSEL3_SC1SEL_HIRC         (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos)      /*!< Setting SC1 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    241. 

  241. 

  242. #define CLK_CLKSEL3_SC2SEL_HXT           (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos)    /*!< Setting SC2 clock source as external XTAL  \hideinitializer */
    243. 

  243. #define CLK_CLKSEL3_SC2SEL_PLL            (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos)      /*!< Setting SC2 clock source as PLL  \hideinitializer */
    244. 

  244. #define CLK_CLKSEL3_SC2SEL_PCLK           (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos)      /*!< Setting SC2 clock source as PCLK  \hideinitializer */
    245. 

  245. #define CLK_CLKSEL3_SC2SEL_HIRC         (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos)      /*!< Setting SC2 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    246. 

  246. 

  247. #define CLK_CLKSEL3_SC3SEL_HXT           (0x0UL<<CLK_CLKSEL3_SC3SEL_Pos)      /*!< Setting SC3 clock source as external XTAL  \hideinitializer */
    248. 

  248. #define CLK_CLKSEL3_SC3SEL_PLL            (0x1UL<<CLK_CLKSEL3_SC3SEL_Pos)      /*!< Setting SC3 clock source as PLL  \hideinitializer */
    249. 

  249. #define CLK_CLKSEL3_SC3SEL_PCLK           (0x2UL<<CLK_CLKSEL3_SC3SEL_Pos)      /*!< Setting SC3 clock source as PCLK  \hideinitializer */
    250. 

  250. #define CLK_CLKSEL3_SC3SEL_HIRC         (0x3UL<<CLK_CLKSEL3_SC3SEL_Pos)      /*!< Setting SC3 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    251. 

  251. 

  252. #define CLK_CLKSEL3_SC4SEL_HXT           (0x0UL<<CLK_CLKSEL3_SC4SEL_Pos)      /*!< Setting SC4 clock source as external XTAL  \hideinitializer */
    253. 

  253. #define CLK_CLKSEL3_SC4SEL_PLL            (0x1UL<<CLK_CLKSEL3_SC4SEL_Pos)      /*!< Setting SC4 clock source as PLL  \hideinitializer */
    254. 

  254. #define CLK_CLKSEL3_SC4SEL_PCLK           (0x2UL<<CLK_CLKSEL3_SC4SEL_Pos)      /*!< Setting SC4 clock source as PCLK  \hideinitializer */
    255. 

  255. #define CLK_CLKSEL3_SC4SEL_HIRC         (0x3UL<<CLK_CLKSEL3_SC4SEL_Pos)      /*!< Setting SC4 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    256. 

  256. 

  257. #define CLK_CLKSEL3_SC5SEL_HXT           (0x0UL<<CLK_CLKSEL3_SC5SEL_Pos)    /*!< Setting SC5 clock source as external XTAL  \hideinitializer */
    258. 

  258. #define CLK_CLKSEL3_SC5SEL_PLL            (0x1UL<<CLK_CLKSEL3_SC5SEL_Pos)      /*!< Setting SC5 clock source as PLL  \hideinitializer */
    259. 

  259. #define CLK_CLKSEL3_SC5SEL_PCLK           (0x2UL<<CLK_CLKSEL3_SC5SEL_Pos)      /*!< Setting SC5 clock source as PCLK  \hideinitializer */
    260. 

  260. #define CLK_CLKSEL3_SC5SEL_HIRC         (0x3UL<<CLK_CLKSEL3_SC5SEL_Pos)      /*!< Setting SC5 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    261. 

  261. 

  262. #define CLK_CLKSEL3_I2S0SEL_HXT           (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos)       /*!< Setting I2S0 clock source as external XTAL  \hideinitializer */
    263. 

  263. #define CLK_CLKSEL3_I2S0SEL_PLL            (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos)      /*!< Setting I2S0 clock source as PLL  \hideinitializer */
    264. 

  264. #define CLK_CLKSEL3_I2S0SEL_PCLK           (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos)      /*!< Setting I2S0 clock source as PCLK  \hideinitializer */
    265. 

  265. #define CLK_CLKSEL3_I2S0SEL_HIRC         (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos)      /*!< Setting I2S0 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    266. 

  266. 

  267. #define CLK_CLKSEL3_I2S1SEL_HXT           (0x0UL<<CLK_CLKSEL3_I2S1SEL_Pos)    /*!< Setting I2S1 clock source as external XTAL  \hideinitializer */
    268. 

  268. #define CLK_CLKSEL3_I2S1SEL_PLL            (0x1UL<<CLK_CLKSEL3_I2S1SEL_Pos)      /*!< Setting I2S1 clock source as PLL  \hideinitializer */
    269. 

  269. #define CLK_CLKSEL3_I2S1SEL_PCLK           (0x2UL<<CLK_CLKSEL3_I2S1SEL_Pos)      /*!< Setting I2S1 clock source as PCLK  \hideinitializer */
    270. 

  270. #define CLK_CLKSEL3_I2S1SEL_HIRC         (0x3UL<<CLK_CLKSEL3_I2S1SEL_Pos)      /*!< Setting I2S1 clock source as internal 22.1184MHz RC clock  \hideinitializer */
    271. 

  271. 

  272. /*---------------------------------------------------------------------------------------------------------*/
    273. 

  273. /*  CLKDIV0 constant definitions.                                                                          */
    274. 

  274. /*---------------------------------------------------------------------------------------------------------*/
    275. 

  275. #define CLK_CLKDIV0_HCLK(x)    (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos)    /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16  \hideinitializer */
    276. 

  276. #define CLK_CLKDIV0_USB(x)     (((x)-1) << CLK_CLKDIV0_USBHDIV_Pos)    /*!< CLKDIV Setting for USB clock divider. It could be 1~16   \hideinitializer */
    277. 

  277. #define CLK_CLKDIV0_UART(x)    (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos)      /*!< CLKDIV Setting for UR clock divider. It could be 1~16  \hideinitializer */
    278. 

  278. #define CLK_CLKDIV0_ADC(x)     (((x)-1) << CLK_CLKDIV0_ADCDIV_Pos)     /*!< CLKDIV Setting for ADC clock divider. It could be 1~256  \hideinitializer */
    279. 

  279. #define CLK_CLKDIV0_SDH(x)     (((x)-1) << CLK_CLKDIV0_SDHDIV_Pos)     /*!< CLKDIV Setting for SDIO clock divider. It could be 1~256  \hideinitializer */
    280. 

  280. 

  281. /*---------------------------------------------------------------------------------------------------------*/
    282. 

  282. /*  CLKDIV1 constant definitions.                                                                          */
    283. 

  283. /*---------------------------------------------------------------------------------------------------------*/
    284. 

  284. #define CLK_CLKDIV1_SC0(x)  (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV Setting for SC0 clock divider. It could be 1~256  \hideinitializer */
    285. 

  285. #define CLK_CLKDIV1_SC1(x)  (((x)-1) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV Setting for SC1 clock divider. It could be 1~256  \hideinitializer */
    286. 

  286. #define CLK_CLKDIV1_SC2(x)  (((x)-1) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV Setting for SC2 clock divider. It could be 1~256  \hideinitializer */
    287. 

  287. #define CLK_CLKDIV1_SC3(x)  (((x)-1) << CLK_CLKDIV1_SC3DIV_Pos) /*!< CLKDIV Setting for SC3 clock divider. It could be 1~256  \hideinitializer */
    288. 

  288. 

  289. /*---------------------------------------------------------------------------------------------------------*/
    290. 

  290. /*  CLKDIV2 constant definitions.                                                                          */
    291. 

  291. /*---------------------------------------------------------------------------------------------------------*/
    292. 

  292. #define CLK_CLKDIV2_SC4(x)  (((x)-1) << CLK_CLKDIV2_SC4DIV_Pos) /*!< CLKDIV Setting for SC4 clock divider. It could be 1~256  \hideinitializer */
    293. 

  293. #define CLK_CLKDIV2_SC5(x)  (((x)-1) << CLK_CLKDIV2_SC5DIV_Pos) /*!< CLKDIV Setting for SC5 clock divider. It could be 1~256  \hideinitializer */
    294. 

  294. 

  295. /*---------------------------------------------------------------------------------------------------------*/
    296. 

  296. /*  CLKDIV3 constant definitions.                                                                          */
    297. 

  297. /*---------------------------------------------------------------------------------------------------------*/
    298. 

  298. #define CLK_CLKDIV3_CAP(x)      (((x)-1) << CLK_CLKDIV3_CAPDIV_Pos) /*!< CLKDIV Setting for CAP Engine clock divider. It could be 1~256  \hideinitializer */
    299. 

  299. #define CLK_CLKDIV3_VSENSE(x)   (((x)-1) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV Setting for Video Pixel clock divider. It could be 1~256  \hideinitializer */
    300. 

  300. #define CLK_CLKDIV3_EMAC(x)  (((x)-1) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV Setting for EMAC_MDCLK clock divider. It could be 1~256  \hideinitializer */
    301. 

  301. 

  302. 

  303. /*---------------------------------------------------------------------------------------------------------*/
    304. 

  304. /*  MODULE constant definitions.                                                                           */
    305. 

  305. /*---------------------------------------------------------------------------------------------------------*/
    306. 

  306. #define MODULE_APBCLK(x)                   ((x >>30) & 0x3)    /*!< Calculate AHBCLK/APBCLK offset on MODULE index  \hideinitializer */
    307. 

  307. #define MODULE_CLKSEL(x)                   ((x >>28) & 0x3)    /*!< Calculate CLKSEL offset on MODULE index  \hideinitializer */
    308. 

  308. #define MODULE_CLKSEL_Msk(x)               ((x >>25) & 0x7)    /*!< Calculate CLKSEL mask offset on MODULE index  \hideinitializer */
    309. 

  309. #define MODULE_CLKSEL_Pos(x)               ((x >>20) & 0x1f)   /*!< Calculate CLKSEL position offset on MODULE index  \hideinitializer */
    310. 

  310. #define MODULE_CLKDIV(x)                   ((x >>18) & 0x3)    /*!< Calculate APBCLK CLKDIV on MODULE index  \hideinitializer */
    311. 

  311. #define MODULE_CLKDIV_Msk(x)               ((x >>10) & 0xff)   /*!< Calculate CLKDIV mask offset on MODULE index  \hideinitializer */
    312. 

  312. #define MODULE_CLKDIV_Pos(x)               ((x >>5 ) & 0x1f)   /*!< Calculate CLKDIV position offset on MODULE index  \hideinitializer */
    313. 

  313. #define MODULE_IP_EN_Pos(x)                ((x >>0 ) & 0x1f)   /*!< Calculate APBCLK offset on MODULE index  \hideinitializer */
    314. 

  314. #define MODULE_NoMsk                       0x0                 /*!< Not mask on MODULE index  \hideinitializer */
    315. 

  315. #define NA                                 MODULE_NoMsk        /*!< Not Available  \hideinitializer */
    316. 

  316. 

  317. #define MODULE_APBCLK_ENC(x)               (((x) & 0x03) << 30)   /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
    318. 

  318. #define MODULE_CLKSEL_ENC(x)               (((x) & 0x03) << 28)   /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
    319. 

  319. #define MODULE_CLKSEL_Msk_ENC(x)           (((x) & 0x07) << 25)   /*!< CLKSEL mask offset on MODULE index */
    320. 

  320. #define MODULE_CLKSEL_Pos_ENC(x)           (((x) & 0x1f) << 20)   /*!< CLKSEL position offset on MODULE index */
    321. 

  321. #define MODULE_CLKDIV_ENC(x)               (((x) & 0x03) << 18)   /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
    322. 

  322. #define MODULE_CLKDIV_Msk_ENC(x)           (((x) & 0xff) << 10)   /*!< CLKDIV mask offset on MODULE index */
    323. 

  323. #define MODULE_CLKDIV_Pos_ENC(x)           (((x) & 0x1f) <<  5)   /*!< CLKDIV position offset on MODULE index */
    324. 

  324. #define MODULE_IP_EN_Pos_ENC(x)            (((x) & 0x1f) <<  0)   /*!< AHBCLK/APBCLK offset on MODULE index */
    325. 

  325. /*--------------------------------------------------------------------------------------------------------------------------------------*/
    326. 

  326. /*   AHBCLK/APBCLK(2) | CLKSEL(2) | CLKSEL_Msk(3) |    CLKSEL_Pos(5)    | CLKDIV(2) | CLKDIV_Msk(8) |     CLKDIV_Pos(5)  |  IP_EN_Pos(5)*/
    327. 

  327. /*--------------------------------------------------------------------------------------------------------------------------------------*/
    328. 

  328. #define PDMA_MODULE      ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_PDMACKEN_Pos)    /*!< PDMA Module  \hideinitializer */
    329. 

  329. #define ISP_MODULE       ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos)     /*!< ISP Module  \hideinitializer */
    330. 

  330. #define EBI_MODULE       ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBICKEN_Pos)     /*!< EBI Module  \hideinitializer */
    331. 

  331. #define USBH_MODULE      ((0UL<<30)|(0<<28)|(1<<25)           |( 8<<20)|(0<<18)|(0xF<<10)         |( 4<<5)|CLK_AHBCLK_USBHCKEN_Pos)    /*!< USBH Module  \hideinitializer */
    332. 

  332. #define EMAC_MODULE      ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|(10<<20)|(3<<18)|(0xFF<<10)        |(16<<5)|CLK_AHBCLK_EMACCKEN_Pos)    /*!< EMAC Module  \hideinitializer */
    333. 

  333. #define SDH_MODULE       ((0UL<<30)|(0<<28)|(3<<25)           |(20<<20)|(0<<18)|(0xFF<<10)        |(24<<5)|CLK_AHBCLK_SDHCKEN_Pos)     /*!< SDH Module  \hideinitializer */
    334. 

  334. #define CRC_MODULE       ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRCCKEN_Pos)     /*!< CRC Module  \hideinitializer */
    335. 

  335. #define CAP_MODULE       ((0UL<<30)|(0<<28)|(3<<25)           |(16<<20)|(3<<18)|(0xFF<<10)        |( 0<<5)|CLK_AHBCLK_CAPCKEN_Pos)     /*!< CAP Module  \hideinitializer */
    336. 

  336. #define SEN_MODULE       ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(3<<18)|(0xFF<<10)        |( 8<<5)|CLK_AHBCLK_SENCKEN_Pos)     /*!< Sensor Clock Module  \hideinitializer */
    337. 

  337. #define USBD_MODULE      ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_USBDCKEN_Pos)    /*!< USBD Module  \hideinitializer */
    338. 

  338. #define CRPT_MODULE      ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRPTCKEN_Pos)    /*!< CRYPTO Module  \hideinitializer */
    339. 

  339. 

  340. #define WDT_MODULE       ((1UL<<30)|(1<<28)|(3<<25)           |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos)    /*!< Watchdog Timer Module  \hideinitializer */
    341. 

  341. #define WWDT_MODULE      ((1UL<<30)|(1<<28)|(3<<25)           |(30<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos)    /*!< Window Watchdog Timer Module  \hideinitializer */
    342. 

  342. #define RTC_MODULE       ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_RTCCKEN_Pos)    /*!< RTC Module  \hideinitializer */
    343. 

  343. #define TMR0_MODULE      ((1UL<<30)|(1<<28)|(7<<25)           |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR0CKEN_Pos)   /*!< Timer0 Module  \hideinitializer */
    344. 

  344. #define TMR1_MODULE      ((1UL<<30)|(1<<28)|(7<<25)           |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR1CKEN_Pos)   /*!< Timer1 Module  \hideinitializer */
    345. 

  345. #define TMR2_MODULE      ((1UL<<30)|(1<<28)|(7<<25)           |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR2CKEN_Pos)   /*!< Timer2 Module  \hideinitializer */
    346. 

  346. #define TMR3_MODULE      ((1UL<<30)|(1<<28)|(7<<25)           |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR3CKEN_Pos)   /*!< Timer3 Module  \hideinitializer */
    347. 

  347. #define CLKO_MODULE      ((1UL<<30)|(1<<28)|(3<<25)           |(28<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CLKOCKEN_Pos)   /*!< CLKO Module  \hideinitializer */
    348. 

  348. #define ACMP_MODULE      ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_ACMPCKEN_Pos)   /*!< ACMP Module  \hideinitializer */
    349. 

  349. #define I2C0_MODULE      ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C0CKEN_Pos)   /*!< I2C0 Module  \hideinitializer */
    350. 

  350. #define I2C1_MODULE      ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C1CKEN_Pos)   /*!< I2C1 Module  \hideinitializer */
    351. 

  351. #define I2C2_MODULE      ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C2CKEN_Pos)   /*!< I2C2 Module  \hideinitializer */
    352. 

  352. #define I2C3_MODULE      ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C3CKEN_Pos)   /*!< I2C3 Module  \hideinitializer */
    353. 

  353. #define SPI0_MODULE      ((1UL<<30)|(1<<28)|(1<<25)           |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI0CKEN_Pos)   /*!< SPI0 Module  \hideinitializer */
    354. 

  354. #define SPI1_MODULE      ((1UL<<30)|(1<<28)|(1<<25)           |( 5<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI1CKEN_Pos)   /*!< SPI1 Module  \hideinitializer */
    355. 

  355. #define SPI2_MODULE      ((1UL<<30)|(1<<28)|(1<<25)           |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI2CKEN_Pos)   /*!< SPI2 Module  \hideinitializer */
    356. 

  356. #define SPI3_MODULE      ((1UL<<30)|(1<<28)|(1<<25)           |( 7<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI3CKEN_Pos)   /*!< SPI3 Module  \hideinitializer */
    357. 

  357. #define UART0_MODULE     ((1UL<<30)|(1<<28)|(3<<25)           |(24<<20)|(0<<18)|(0xF<<10)         |( 8<<5)|CLK_APBCLK0_UART0CKEN_Pos)  /*!< UART0 Module  \hideinitializer */
    358. 

  358. #define UART1_MODULE     ((1UL<<30)|(1<<28)|(3<<25)           |(24<<20)|(0<<18)|(0xF<<10)         |( 8<<5)|CLK_APBCLK0_UART1CKEN_Pos)  /*!< UART1 Module  \hideinitializer */
    359. 

  359. #define UART2_MODULE     ((1UL<<30)|(1<<28)|(3<<25)           |(24<<20)|(0<<18)|(0xF<<10)         |( 8<<5)|CLK_APBCLK0_UART2CKEN_Pos)  /*!< UART2 Module  \hideinitializer */
    360. 

  360. #define UART3_MODULE     ((1UL<<30)|(1<<28)|(3<<25)           |(24<<20)|(0<<18)|(0xF<<10)         |( 8<<5)|CLK_APBCLK0_UART3CKEN_Pos)  /*!< UART3 Module  \hideinitializer */
    361. 

  361. #define UART4_MODULE     ((1UL<<30)|(1<<28)|(3<<25)           |(24<<20)|(0<<18)|(0xF<<10)         |( 8<<5)|CLK_APBCLK0_UART4CKEN_Pos)  /*!< UART4 Module  \hideinitializer */
    362. 

  362. #define UART5_MODULE     ((1UL<<30)|(1<<28)|(3<<25)           |(24<<20)|(0<<18)|(0xF<<10)         |( 8<<5)|CLK_APBCLK0_UART5CKEN_Pos)  /*!< UART5 Module  \hideinitializer */
    363. 

  363. #define CAN0_MODULE      ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN0CKEN_Pos)   /*!< CAN0 Module  \hideinitializer */
    364. 

  364. #define CAN1_MODULE      ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN1CKEN_Pos)   /*!< CAN1 Module  \hideinitializer */
    365. 

  365. #define OTG_MODULE       ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_OTGCKEN_Pos)    /*!< OTG Module  \hideinitializer */
    366. 

  366. #define ADC_MODULE       ((1UL<<30)|(1<<28)|(3<<25)           |( 2<<20)|(0<<18)|(0xFF<<10)        |(16<<5)|CLK_APBCLK0_ADCCKEN_Pos)    /*!< ADC Module  \hideinitializer */
    367. 

  367. #define I2S0_MODULE      ((1UL<<30)|(3<<28)|(3<<25)           |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S0CKEN_Pos)   /*!< I2S0 Module  \hideinitializer */
    368. 

  368. #define I2S1_MODULE      ((1UL<<30)|(3<<28)|(3<<25)           |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S1CKEN_Pos)   /*!< I2S1 Module  \hideinitializer */
    369. 

  369. #define PS2_MODULE       ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_PS2CKEN_Pos)    /*!< PS2 Module  \hideinitializer */
    370. 

  370. 

  371. #define SC0_MODULE       ((2UL<<30)|(3<<28)|(3<<25)           |( 0<<20)|(1<<18)|(0xFF<<10)        |( 0<<5)|CLK_APBCLK1_SC0CKEN_Pos)    /*!< SmartCard0 Module  \hideinitializer */
    372. 

  372. #define SC1_MODULE       ((2UL<<30)|(3<<28)|(3<<25)           |( 2<<20)|(1<<18)|(0xFF<<10)        |( 8<<5)|CLK_APBCLK1_SC1CKEN_Pos)    /*!< SmartCard1 Module  \hideinitializer */
    373. 

  373. #define SC2_MODULE       ((2UL<<30)|(3<<28)|(3<<25)           |( 4<<20)|(1<<18)|(0xFF<<10)        |(16<<5)|CLK_APBCLK1_SC2CKEN_Pos)    /*!< SmartCard2 Module  \hideinitializer */
    374. 

  374. #define SC3_MODULE       ((2UL<<30)|(3<<28)|(3<<25)           |( 6<<20)|(1<<18)|(0xFF<<10)        |(24<<5)|CLK_APBCLK1_SC3CKEN_Pos)    /*!< SmartCard3 Module  \hideinitializer */
    375. 

  375. #define SC4_MODULE       ((2UL<<30)|(3<<28)|(3<<25)           |( 8<<20)|(2<<18)|(0xFF<<10)        |( 0<<5)|CLK_APBCLK1_SC4CKEN_Pos)    /*!< SmartCard4 Module  \hideinitializer */
    376. 

  376. #define SC5_MODULE       ((2UL<<30)|(3<<28)|(3<<25)           |(10<<20)|(2<<18)|(0xFF<<10)        |( 8<<5)|CLK_APBCLK1_SC5CKEN_Pos)    /*!< SmartCard5 Module  \hideinitializer */
    377. 

  377. #define I2C4_MODULE      ((2UL<<30)|(0<<28)|(0<<25)           |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos)   /*!< I2C4 Module */
    378. 

  378. #define PWM0CH01_MODULE  ((2UL<<30)|(2<<28)|(7<<25)           |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH01CKEN_Pos) /*!< PWM0CH01 Module  \hideinitializer */
    379. 

  379. #define PWM0CH23_MODULE  ((2UL<<30)|(2<<28)|(7<<25)           |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH23CKEN_Pos) /*!< PWM0CH23 Module  \hideinitializer */
    380. 

  380. #define PWM0CH45_MODULE  ((2UL<<30)|(2<<28)|(7<<25)           |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH45CKEN_Pos) /*!< PWM0CH45 Module  \hideinitializer */
    381. 

  381. #define PWM1CH01_MODULE  ((2UL<<30)|(2<<28)|(7<<25)           |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH01CKEN_Pos) /*!< PWM1CH01 Module  \hideinitializer */
    382. 

  382. #define PWM1CH23_MODULE  ((2UL<<30)|(2<<28)|(7<<25)           |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH2345CKEN_Pos) /*!< PWM1CH23 Module  \hideinitializer */
    383. 

  383. #define PWM1CH45_MODULE  ((2UL<<30)|(2<<28)|(7<<25)           |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH2345CKEN_Pos) /*!< PWM1CH45 Module  \hideinitializer */
    384. 

  384. #define QEI0_MODULE      ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI0CKEN_Pos)   /*!< QEI0 Module  \hideinitializer */
    385. 

  385. #define QEI1_MODULE      ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI1CKEN_Pos)   /*!< QEI1 Module  \hideinitializer */
    386. 

  386. #define ECAP0_MODULE     ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP0CKEN_Pos)  /*!< ECAP0 Module  \hideinitializer */
    387. 

  387. #define ECAP1_MODULE     ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP1CKEN_Pos)  /*!< ECAP1 Module  \hideinitializer */
    388. 

  388. #define EPWM0_MODULE     ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM0CKEN_Pos)  /*!< EPWM0 Module  \hideinitializer */
    389. 

  389. #define EPWM1_MODULE     ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM1CKEN_Pos)  /*!< EPWM1 Module  \hideinitializer */
    390. 

  390. #define OPA_MODULE       ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_OPACKEN_Pos)    /*!< OPA Module  \hideinitializer */
    391. 

  391. #define EADC_MODULE      ((2UL<<30)|(1<<28)|(3<<25)           |( 2<<20)|(0<<18)|(0xFF<<10)        |(16<<5)|CLK_APBCLK1_EADCCKEN_Pos)   /*!< EADC Module  \hideinitializer */
    392. 

  392. 

  393. /*@}*/ /* end of group NUC472_442_CLK_EXPORTED_CONSTANTS */
    394. 

  394. 

  395. 

  396. /** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
    397. 

  397.   @{
    398. 

  398. */
    399. 

  399. 

  400. void CLK_DisableCKO(void);
    401. 

  401. void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
    402. 

  402. void CLK_PowerDown(void);
    403. 

  403. void CLK_Idle(void);
    404. 

  404. uint32_t CLK_GetHXTFreq(void);
    405. 

  405. uint32_t CLK_GetLXTFreq(void);
    406. 

  406. uint32_t CLK_GetHCLKFreq(void);
    407. 

  407. uint32_t CLK_GetPCLKFreq(void);
    408. 

  408. uint32_t CLK_GetCPUFreq(void);
    409. 

  409. uint32_t CLK_GetPLLClockFreq(void);
    410. 

  410. uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
    411. 

  411. void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
    412. 

  412. void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
    413. 

  413. void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
    414. 

  414. void CLK_EnableXtalRC(uint32_t u32ClkMask);
    415. 

  415. void CLK_DisableXtalRC(uint32_t u32ClkMask);
    416. 

  416. void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
    417. 

  417. void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
    418. 

  418. uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
    419. 

  419. void CLK_DisablePLL(void);
    420. 

  420. void CLK_SysTickDelay(uint32_t us);
    421. 

  421. uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
    422. 

  422. void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
    423. 

  423. void CLK_DisableSysTick(void);
    424. 

  424. 

  425. /*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
    426. 

  426. 

  427. /*@}*/ /* end of group NUC472_442_CLK_Driver */
    428. 

  428. 

  429. /*@}*/ /* end of group NUC472_442_Device_Driver */
    430. 

  430. 

  431. #ifdef __cplusplus
    432. 

  432. }
    433. 

  433. #endif
    434. 

  434. 

  435. #endif //__CLK_H__
    436. 

  436. 

  437. /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
    438.