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sys.h

sys.h 111 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file     SYS.h
    3. 

  3.  * @version  V1.0
    4. 

  4.  * $Revision  1 $
    5. 

  5.  * $Date: 15/10/21 1:35p $
    6. 

  6.  * @brief    NUC472/NUC442 SYS Header File
    7. 

  7.  *
    8. 

  8.  * @note
    9. 

  9.  * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
    10. 

  10.  ******************************************************************************/
    11. 

  11. 

  12. #ifndef __SYS_H__
    13. 

  13. #define __SYS_H__
    14. 

  14. 

  15. #ifdef __cplusplus
    16. 

  16. extern "C"
    17. 

  17. {
    18. 

  18. #endif
    19. 

  19. 

  20. /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
    21. 

  21.   @{
    22. 

  22. */
    23. 

  23. 

  24. /** @addtogroup NUC472_442_SYS_Driver SYS Driver
    25. 

  25.   @{
    26. 

  26. */
    27. 

  27. 

  28. /** @addtogroup NUC472_442_SYS_EXPORTED_CONSTANTS SYS Exported Constants
    29. 

  29.   @{
    30. 

  30. */
    31. 

  31. 

  32. /*---------------------------------------------------------------------------------------------------------*/
    33. 

  33. /*  Module Reset Control Resister constant definitions.                                                    */
    34. 

  34. /*---------------------------------------------------------------------------------------------------------*/
    35. 

  35. #define PDMA_RST  ((0x0<<24)|SYS_IPRST0_PDMARST_Pos)    /*!<Reset PDMA  \hideinitializer */
    36. 

  36. #define EBI_RST   ((0x0<<24)|SYS_IPRST0_EBIRST_Pos)     /*!<Reset EBI  \hideinitializer  */
    37. 

  37. #define USBH_RST  ((0x0<<24)|SYS_IPRST0_USBHRST_Pos)    /*!<Reset USBH  \hideinitializer  */
    38. 

  38. #define EMAC_RST  ((0x0<<24)|SYS_IPRST0_EMACRST_Pos)    /*!<Reset EMAC  \hideinitializer */
    39. 

  39. #define SDH_RST   ((0x0<<24)|SYS_IPRST0_SDHRST_Pos)     /*!<Reset SDIO  \hideinitializer */
    40. 

  40. #define CRC_RST   ((0x0<<24)|SYS_IPRST0_CRCRST_Pos)     /*!<Reset CRC  \hideinitializer  */
    41. 

  41. #define CAP_RST   ((0x0<<24)|SYS_IPRST0_CAPRST_Pos)     /*!<Reset CAP  \hideinitializer  */
    42. 

  42. #define CRYPTO_RST ((0x0<<24)|SYS_IPRST0_CRYPTORST_Pos)  /*!<Reset CRYPTO  \hideinitializer */
    43. 

  43. #define GPIO_RST  ((0x4<<24)|SYS_IPRST1_GPIORST_Pos)    /*!<Reset GPIO  \hideinitializer  */
    44. 

  44. #define TMR0_RST  ((0x4<<24)|SYS_IPRST1_TMR0RST_Pos)    /*!<Reset TMR0  \hideinitializer */
    45. 

  45. #define TMR1_RST  ((0x4<<24)|SYS_IPRST1_TMR1RST_Pos)    /*!<Reset TMR1 \hideinitializer */
    46. 

  46. #define TMR2_RST  ((0x4<<24)|SYS_IPRST1_TMR2RST_Pos)    /*!<Reset TMR2 \hideinitializer */
    47. 

  47. #define TMR3_RST  ((0x4<<24)|SYS_IPRST1_TMR3RST_Pos)    /*!<Reset TMR3 \hideinitializer */
    48. 

  48. #define ACMP_RST  ((0x4<<24)|SYS_IPRST1_ACMPRST_Pos)    /*!<Reset ACMP \hideinitializer */
    49. 

  49. #define I2C0_RST  ((0x4<<24)|SYS_IPRST1_I2C0RST_Pos)    /*!<Reset I2C0 \hideinitializer */
    50. 

  50. #define I2C1_RST  ((0x4<<24)|SYS_IPRST1_I2C1RST_Pos)    /*!<Reset I2C1 \hideinitializer */
    51. 

  51. #define I2C2_RST  ((0x4<<24)|SYS_IPRST1_I2C2RST_Pos)    /*!<Reset I2C2 \hideinitializer */
    52. 

  52. #define I2C3_RST  ((0x4<<24)|SYS_IPRST1_I2C3RST_Pos)    /*!<Reset I2C3 \hideinitializer */
    53. 

  53. #define SPI0_RST  ((0x4<<24)|SYS_IPRST1_SPI0RST_Pos)    /*!<Reset SPI0 \hideinitializer */
    54. 

  54. #define SPI1_RST  ((0x4<<24)|SYS_IPRST1_SPI1RST_Pos)    /*!<Reset SPI1 \hideinitializer */
    55. 

  55. #define SPI2_RST  ((0x4<<24)|SYS_IPRST1_SPI2RST_Pos)    /*!<Reset SPI2 \hideinitializer */
    56. 

  56. #define SPI3_RST  ((0x4<<24)|SYS_IPRST1_SPI3RST_Pos)    /*!<Reset SPI3 \hideinitializer */
    57. 

  57. #define UART0_RST ((0x4<<24)|SYS_IPRST1_UART0RST_Pos)   /*!<Reset UART0 \hideinitializer */
    58. 

  58. #define UART1_RST ((0x4<<24)|SYS_IPRST1_UART1RST_Pos)   /*!<Reset UART1 \hideinitializer */
    59. 

  59. #define UART2_RST ((0x4<<24)|SYS_IPRST1_UART2RST_Pos)   /*!<Reset UART2 \hideinitializer */
    60. 

  60. #define UART3_RST ((0x4<<24)|SYS_IPRST1_UART3RST_Pos)   /*!<Reset UART3 \hideinitializer */
    61. 

  61. #define UART4_RST ((0x4<<24)|SYS_IPRST1_UART4RST_Pos)   /*!<Reset UART4 \hideinitializer */
    62. 

  62. #define UART5_RST ((0x4<<24)|SYS_IPRST1_UART5RST_Pos)   /*!<Reset UART5 \hideinitializer */
    63. 

  63. #define CAN0_RST  ((0x4<<24)|SYS_IPRST1_CAN0RST_Pos)    /*!<Reset CAN0 \hideinitializer */
    64. 

  64. #define CAN1_RST  ((0x4<<24)|SYS_IPRST1_CAN1RST_Pos)    /*!<Reset CAN1 \hideinitializer */
    65. 

  65. #define OTG_RST   ((0x4<<24)|SYS_IPRST1_OTGRST_Pos)     /*!<Reset OTG \hideinitializer */
    66. 

  66. #define USBD_RST  ((0x4<<24)|SYS_IPRST1_USBDRST_Pos)    /*!<Reset USBD \hideinitializer */
    67. 

  67. #define ADC_RST   ((0x4<<24)|SYS_IPRST1_ADCRST_Pos)     /*!<Reset ADC \hideinitializer */
    68. 

  68. #define I2S0_RST  ((0x4<<24)|SYS_IPRST1_I2S0RST_Pos)    /*!<Reset I2S0 \hideinitializer */
    69. 

  69. #define I2S1_RST  ((0x4<<24)|SYS_IPRST1_I2S1RST_Pos)    /*!<Reset I2S1 \hideinitializer */
    70. 

  70. #define PS2_RST   ((0x4<<24)|SYS_IPRST1_PS2RST_Pos)     /*!<Reset PS2 \hideinitializer */
    71. 

  71. #define SC0_RST   ((0x8<<24)|SYS_IPRST2_SC0RST_Pos)     /*!<Reset SC0 \hideinitializer */
    72. 

  72. #define SC1_RST   ((0x8<<24)|SYS_IPRST2_SC1RST_Pos)     /*!<Reset SC1 \hideinitializer */
    73. 

  73. #define SC2_RST   ((0x8<<24)|SYS_IPRST2_SC2RST_Pos)     /*!<Reset SC2 \hideinitializer */
    74. 

  74. #define SC3_RST   ((0x8<<24)|SYS_IPRST2_SC3RST_Pos)     /*!<Reset SC3 \hideinitializer */
    75. 

  75. #define SC4_RST   ((0x8<<24)|SYS_IPRST2_SC4RST_Pos)     /*!<Reset SC4 \hideinitializer */
    76. 

  76. #define SC5_RST   ((0x8<<24)|SYS_IPRST2_SC5RST_Pos)     /*!<Reset SC5 \hideinitializer */
    77. 

  77. #define I2C4_RST  ((0x8<<24)|SYS_IPRST2_I2C4RST_Pos)    /*!<Reset I2C4 \hideinitializer */
    78. 

  78. #define PWM0_RST  ((0x8<<24)|SYS_IPRST2_PWM0RST_Pos)    /*!<Reset PWM0 \hideinitializer */
    79. 

  79. #define PWM1_RST  ((0x8<<24)|SYS_IPRST2_PWM1RST_Pos)    /*!<Reset PWM1 \hideinitializer */
    80. 

  80. #define QEI0_RST  ((0x8<<24)|SYS_IPRST2_QEI0RST_Pos)    /*!<Reset QEI0 \hideinitializer */
    81. 

  81. #define QEI1_RST  ((0x8<<24)|SYS_IPRST2_QEI1RST_Pos)    /*!<Reset QEI1 \hideinitializer */
    82. 

  82. 

  83. /*---------------------------------------------------------------------------------------------------------*/
    84. 

  84. /*  BODCTL constant definitions.                                                                            */
    85. 

  85. /*---------------------------------------------------------------------------------------------------------*/
    86. 

  86. #define  SYS_BODCTL_BODVL_2_2V        (0x0UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 2.2V \hideinitializer */
    87. 

  87. #define  SYS_BODCTL_BODVL_2_7V        (0x1UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 2.7V \hideinitializer */
    88. 

  88. #define  SYS_BODCTL_BODVL_3_8V        (0x2UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 3.82V \hideinitializer */
    89. 

  89. #define  SYS_BODCTL_BODVL_4_5V        (0x3UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 4.5V \hideinitializer */
    90. 

  90. #define  SYS_BODCTL_BODRSTEN          (0x1UL<<SYS_BODCTL_BODRSTEN_Pos)     /*!<Enable reset function of BOD. \hideinitializer */
    91. 

  91. #define  SYS_BODCTL_BODINTEN          (0x0UL<<SYS_BODCTL_BODRSTEN_Pos)     /*!<Enable interrupt function of BOD. \hideinitializer */
    92. 

  92. #define  SYS_BODCTL_BODLPM            (0x1UL<<SYS_BODCTL_BODLPM_Pos)       /*!<BOD work in low power mode. \hideinitializer */
    93. 

  93. #define  SYS_BODCTL_BODOUT            (0x1UL<<SYS_BODCTL_BODOUT_Pos)       /*!<Output of BOD IP. \hideinitializer */
    94. 

  94. #define  SYS_BODCTL_LVREN             (0x1UL<<SYS_BODCTL_LVREN_Pos)        /*!<Enable LVR function. \hideinitializer */
    95. 

  95. 

  96. /*---------------------------------------------------------------------------------------------------------*/
    97. 

  97. /*  VREFCTL constant definitions. (Write-Protection Register)                                               */
    98. 

  98. /*---------------------------------------------------------------------------------------------------------*/
    99. 

  99. #define SYS_VREFCTL_VREF_2_65V         (0x03UL<<SYS_VREFCTL_VREFCTL_Pos)    /*!<  VOUT= 2.56V  \hideinitializer */
    100. 

  100. #define SYS_VREFCTL_VREF_2_048V        (0x07UL<<SYS_VREFCTL_VREFCTL_Pos)    /*!< VOUT= 2.048V  \hideinitializer */
    101. 

  101. #define SYS_VREFCTL_VREF_3_072V        (0x0BUL<<SYS_VREFCTL_VREFCTL_Pos)    /*!< VOUT= 3.072V  \hideinitializer */
    102. 

  102. #define SYS_VREFCTL_VREF_4_096V        (0x0FUL<<SYS_VREFCTL_VREFCTL_Pos)    /*!< VOUT= 4.096V  \hideinitializer */
    103. 

  103. #define SYS_VREFCTL_VREF_AVDD          (0x10UL<<SYS_VREFCTL_VREFCTL_Pos)   /*!< VOUT= AVDD  \hideinitializer */
    104. 

  104. #define SYS_VREFCTL_ADCMODESEL_EADC    (0x1UL<<SYS_VREFCTL_ADCMODESEL_Pos) /*!< EADC mode  \hideinitializer */
    105. 

  105. #define SYS_VREFCTL_ADCMODESEL_ADC     (0x0UL<<SYS_VREFCTL_ADCMODESEL_Pos) /*!< ADC mode  \hideinitializer */
    106. 

  106. #define SYS_VREFCTL_PWMSYNCMODE_EN     (0x1UL<<SYS_VREFCTL_PWMSYNCMODE_Pos)/*!<PWM SYNC MODE ENABLED, PWM engine clock is same as HCLK  \hideinitializer */
    107. 

  107. 

  108. /*---------------------------------------------------------------------------------------------------------*/
    109. 

  109. /*  USBROLE constant definitions. (Write-Protection Register)                                                */
    110. 

  110. /*---------------------------------------------------------------------------------------------------------*/
    111. 

  111. #define SYS_USBPHY_USBROLE_OTG_V33_EN (0x1UL<<SYS_USBPHY_LDO33EN_Pos)   /*!<   USB LDO33 Enabled  \hideinitializer */
    112. 

  112. #define SYS_USBPHY_USBROLE_STD_USBD   (0x0UL<<SYS_USBPHY_USBROLE_Pos)   /*!<    Standard USB device  \hideinitializer */
    113. 

  113. #define SYS_USBPHY_USBROLE_STD_USBH   (0x1UL<<SYS_USBPHY_USBROLE_Pos)   /*!<   Standard USB host  \hideinitializer */
    114. 

  114. #define SYS_USBPHY_USBROLE_ID_DEPH    (0x2UL<<SYS_USBPHY_USBROLE_Pos)   /*!<   ID dependent device  \hideinitializer */
    115. 

  115. #define SYS_USBPHY_USBROLE_ON_THE_GO  (0x3UL<<SYS_USBPHY_USBROLE_Pos)   /*!<   On-The-Go device  \hideinitializer */
    116. 

  116. 

  117. 

  118. 

  119. /*---------------------------------------------------------------------------------------------------------*/
    120. 

  120. /*  Multi-Function constant definitions.                                                                   */
    121. 

  121. /*---------------------------------------------------------------------------------------------------------*/
    122. 

  122. /* How to use below #define?
    123. 

  123. Example 1: If user want to set PA.0 as SC0_CD in initial function,
    124. 

  124.            user can issue following command to achieve it.
    125. 

  125. 

  126.            SYS->GPA_MFPL  = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD  ;
    127. 

  127. 

  128. */
    129. 

  129. //GPA_MFPL_PA0MFP
    130. 

  130. #define SYS_GPA_MFPL_PA0MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA0MFP_Pos)           /*!< GPA_MFPL PA0 setting for GPIO   \hideinitializer */
    131. 

  131. #define SYS_GPA_MFPL_PA0MFP_TAMPER0     (0x1UL<<SYS_GPA_MFPL_PA0MFP_Pos)           /*!< GPA_MFPL PA0 setting for TAMPER0    \hideinitializer */
    132. 

  132. #define SYS_GPA_MFPL_PA0MFP_SC0_CD      (0x2UL<<SYS_GPA_MFPL_PA0MFP_Pos)           /*!< GPA_MFPL PA0 setting for SC0_CD   \hideinitializer */
    133. 

  133. #define SYS_GPA_MFPL_PA0MFP_CAN1_RXD    (0x3UL<<SYS_GPA_MFPL_PA0MFP_Pos)           /*!< GPA_MFPL PA0 setting for CAN1_RXD  \hideinitializer */
    134. 

  134. #define SYS_GPA_MFPL_PA0MFP_INT0        (0x8UL<<SYS_GPA_MFPL_PA0MFP_Pos)           /*!< GPA_MFPL PA0 setting for INT0  \hideinitializer */
    135. 

  135. 

  136. //GPA_MFPL_PA1MFP
    137. 

  137. #define SYS_GPA_MFPL_PA1MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for GPIO    \hideinitializer */
    138. 

  138. #define SYS_GPA_MFPL_PA1MFP_TAMPER1     (0x1UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for TAMPER1   \hideinitializer */
    139. 

  139. #define SYS_GPA_MFPL_PA1MFP_SC5_CD      (0x2UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for SC5_CD  \hideinitializer */
    140. 

  140. #define SYS_GPA_MFPL_PA1MFP_CAN1_TXD    (0x3UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for CAN1_TXD  \hideinitializer */
    141. 

  141. #define SYS_GPA_MFPL_PA1MFP_EBI_A22     (0x7UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for EBI_A22 \hideinitializer */
    142. 

  142. 

  143. //GPA_MFPL_PA2MFP
    144. 

  144. #define SYS_GPA_MFPL_PA2MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA2MFP_Pos)           /*!< GPA_MFPL PA2 setting for GPIO     \hideinitializer */
    145. 

  145. #define SYS_GPA_MFPL_PA2MFP_SC2_DAT     (0x1UL<<SYS_GPA_MFPL_PA2MFP_Pos)           /*!< GPA_MFPL PA2 setting for SC2_DAT    \hideinitializer */
    146. 

  146. #define SYS_GPA_MFPL_PA2MFP_SPI3_MISO0  (0x2UL<<SYS_GPA_MFPL_PA2MFP_Pos)           /*!< GPA_MFPL PA2 setting for SPI3_MISO0     \hideinitializer */
    147. 

  147. #define SYS_GPA_MFPL_PA2MFP_I2S0_MCLK   (0x3UL<<SYS_GPA_MFPL_PA2MFP_Pos)           /*!< GPA_MFPL PA2 setting for I2S0_MCLK    \hideinitializer */
    148. 

  148. #define SYS_GPA_MFPL_PA2MFP_BRAKE11     (0x4UL<<SYS_GPA_MFPL_PA2MFP_Pos)           /*!< GPA_MFPL PA2 setting for BRAKE11    \hideinitializer */
    149. 

  149. #define SYS_GPA_MFPL_PA2MFP_CAP_SFIELD  (0x5UL<<SYS_GPA_MFPL_PA2MFP_Pos)           /*!< GPA_MFPL PA2 setting for CAP_SFIELD    \hideinitializer */
    150. 

  150. #define SYS_GPA_MFPL_PA2MFP_EBI_A12     (0x7UL<<SYS_GPA_MFPL_PA2MFP_Pos)           /*!< GPA_MFPL PA2 setting for EBI_A12    \hideinitializer */
    151. 

  151. 

  152. //GPA_MFPL_PA3MFP
    153. 

  153. #define SYS_GPA_MFPL_PA3MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for GPIO     \hideinitializer */
    154. 

  154. #define SYS_GPA_MFPL_PA3MFP_SC2_CLK     (0x1UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for SC2_CLK      \hideinitializer */
    155. 

  155. #define SYS_GPA_MFPL_PA3MFP_SPI3_MOSI0  (0x2UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for SPI3_MOSI0      \hideinitializer */
    156. 

  156. #define SYS_GPA_MFPL_PA3MFP_I2S0_DO     (0x3UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for I2S0_D0     \hideinitializer */
    157. 

  157. #define SYS_GPA_MFPL_PA3MFP_BRAKE10     (0x4UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for BRAKE10    \hideinitializer */
    158. 

  158. #define SYS_GPA_MFPL_PA3MFP_EBI_A13     (0x7UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for EBI_A13    \hideinitializer */
    159. 

  159. 

  160. //GPA_MFPL_PA4MFP
    161. 

  161. #define SYS_GPA_MFPL_PA4MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA4MFP_Pos)           /*!< GPA_MFPL PA4 setting for GPIO     \hideinitializer */
    162. 

  162. #define SYS_GPA_MFPL_PA4MFP_SC2_PWR     (0x1UL<<SYS_GPA_MFPL_PA4MFP_Pos)            /*!< GPA_MFPL PA4 setting for SC2_PWR     \hideinitializer */
    163. 

  163. #define SYS_GPA_MFPL_PA4MFP_SPI3_CLK    (0x2UL<<SYS_GPA_MFPL_PA4MFP_Pos)            /*!< GPA_MFPL PA4 setting for SPI3_CLK    \hideinitializer */
    164. 

  164. #define SYS_GPA_MFPL_PA4MFP_I2S0_DI     (0x3UL<<SYS_GPA_MFPL_PA4MFP_Pos)            /*!< GPA_MFPL PA4 setting for I2S0_DI     \hideinitializer */
    165. 

  165. #define SYS_GPA_MFPL_PA4MFP_QEI1_Z      (0x5UL<<SYS_GPA_MFPL_PA4MFP_Pos)            /*!< GPA_MFPL PA4 setting for QEI1_Z      \hideinitializer */
    166. 

  166. #define SYS_GPA_MFPL_PA4MFP_EBI_A14     (0x7UL<<SYS_GPA_MFPL_PA4MFP_Pos)            /*!< GPA_MFPL PA4 setting for EBI_A14     \hideinitializer */
    167. 

  167. #define SYS_GPA_MFPL_PA4MFP_ECAP1_IC2   (0x8UL<<SYS_GPA_MFPL_PA4MFP_Pos)             /*!< GPA_MFPL PA4 setting for ECAP1_IC2   \hideinitializer */
    168. 

  168. 

  169. //GPA_MFPL_PA5MFP
    170. 

  170. #define SYS_GPA_MFPL_PA5MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA5MFP_Pos)           /*!< GPA_MFPL PA5 setting for GPIO     \hideinitializer */
    171. 

  171. #define SYS_GPA_MFPL_PA5MFP_SC2_RST     (0x1UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for SC2_RST     \hideinitializer */
    172. 

  172. #define SYS_GPA_MFPL_PA5MFP_SPI3_SS0    (0x2UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for SPI3_SS0    \hideinitializer */
    173. 

  173. #define SYS_GPA_MFPL_PA5MFP_I2S0_BCLK   (0x3UL<<SYS_GPA_MFPL_PA5MFP_Pos)          /*!< GPA_MFPL PA5 setting for I2S0_BCLK    \hideinitializer */
    174. 

  174. #define SYS_GPA_MFPL_PA5MFP_PWM0_CH0    (0x4UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for PWM0 CH0     \hideinitializer */
    175. 

  175. #define SYS_GPA_MFPL_PA5MFP_QEI1_B      (0x5UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for QEI1_B    \hideinitializer */
    176. 

  176. #define SYS_GPA_MFPL_PA5MFP_EBI_A15     (0x7UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for EBI_A15    \hideinitializer */
    177. 

  177. #define SYS_GPA_MFPL_PA5MFP_ECAP1_IC1   (0x8UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for ECAP1_IC1    \hideinitializer */
    178. 

  178. 

  179. //GPA_MFPL_PA6MFP
    180. 

  180. #define SYS_GPA_MFPL_PA6MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for GPIO     \hideinitializer */
    181. 

  181. #define SYS_GPA_MFPL_PA6MFP_SC2_CD      (0x1UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for SC2_CD     \hideinitializer */
    182. 

  182. #define SYS_GPA_MFPL_PA6MFP_I2S0_LRCK   (0x3UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for I2S0_LRCK    \hideinitializer */
    183. 

  183. #define SYS_GPA_MFPL_PA6MFP_PWM0_CH1    (0x4UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for PWM1 CH1    \hideinitializer */
    184. 

  184. #define SYS_GPA_MFPL_PA6MFP_QEI1_A      (0x5UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for QEI1_A     \hideinitializer */
    185. 

  185. #define SYS_GPA_MFPL_PA6MFP_CAN1_TXD    (0x6UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for CAN1_TXD    \hideinitializer */
    186. 

  186. #define SYS_GPA_MFPL_PA6MFP_EBI_A16     (0x7UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for EBI_A16    \hideinitializer */
    187. 

  187. #define SYS_GPA_MFPL_PA6MFP_ECAP1_IC0   (0x8UL<<SYS_GPA_MFPL_PA6MFP_Pos)           /*!< GPA_MFPL PA6 setting for ECAP1_IC0    \hideinitializer */
    188. 

  188. 

  189. //GPA_MFPL_PA7MFP
    190. 

  190. #define SYS_GPA_MFPL_PA7MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA7MFP_Pos)           /*!< GPA_MFPL PA7 setting for GPIO     \hideinitializer */
    191. 

  191. #define SYS_GPA_MFPL_PA7MFP_SC0_CLK     (0x2UL<<SYS_GPA_MFPL_PA7MFP_Pos)           /*!< GPA_MFPL PA7 setting for SC0_CLK    \hideinitializer */
    192. 

  192. #define SYS_GPA_MFPL_PA7MFP_SPI3_SS0    (0x3UL<<SYS_GPA_MFPL_PA7MFP_Pos)           /*!< GPA_MFPL PA7 setting for SPI3_SS0     \hideinitializer */
    193. 

  193. #define SYS_GPA_MFPL_PA7MFP_PWM1_CH3    (0x4UL<<SYS_GPA_MFPL_PA7MFP_Pos)          /*!< GPA_MFPL PA7 setting for PWM1 CH3     \hideinitializer */
    194. 

  194. #define SYS_GPA_MFPL_PA7MFP_EPWM0_CH5   (0x5UL<<SYS_GPA_MFPL_PA7MFP_Pos)           /*!< GPA_MFPL PA7 setting for EPWM0 CH5     \hideinitializer */
    195. 

  195. #define SYS_GPA_MFPL_PA7MFP_EBI_A17     (0x7UL<<SYS_GPA_MFPL_PA7MFP_Pos)           /*!< GPA_MFPL PA7 setting for EBI_A17     \hideinitializer */
    196. 

  196. 

  197. //GPA_MFPL_PA8MFP
    198. 

  198. #define SYS_GPA_MFPH_PA8MFP_GPIO        (0x0UL<<SYS_GPA_MFPH_PA8MFP_Pos)           /*!< GPA_MFPH PA8 setting for GPIO     \hideinitializer */
    199. 

  199. #define SYS_GPA_MFPH_PA8MFP_SC0_RST     (0x2UL<<SYS_GPA_MFPH_PA8MFP_Pos)           /*!< GPA_MFPH PA8 setting for SC0_RST    \hideinitializer */
    200. 

  200. #define SYS_GPA_MFPH_PA8MFP_SPI3_CLK    (0x3UL<<SYS_GPA_MFPH_PA8MFP_Pos)           /*!< GPA_MFPH PA8 setting for SPI3_CLK     \hideinitializer */
    201. 

  201. #define SYS_GPA_MFPH_PA8MFP_PWM1_CH2    (0x4UL<<SYS_GPA_MFPH_PA8MFP_Pos)           /*!< GPA_MFPH PA8 setting for PWM1 CH2    \hideinitializer */
    202. 

  202. #define SYS_GPA_MFPH_PA8MFP_EPWM0_CH4   (0x5UL<<SYS_GPA_MFPH_PA8MFP_Pos)           /*!< GPA_MFPH PA8 setting for EPWM0_CH4     \hideinitializer */
    203. 

  203. #define SYS_GPA_MFPH_PA8MFP_EBI_A18     (0x7UL<<SYS_GPA_MFPH_PA8MFP_Pos)           /*!< GPA_MFPH PA8 setting for EBI_A18    \hideinitializer */
    204. 

  204. 

  205. //GPA_MFPH_PA9MFP
    206. 

  206. #define SYS_GPA_MFPH_PA9MFP_GPIO        (0x0UL<<SYS_GPA_MFPH_PA9MFP_Pos)           /*!< GPA_MFPH PA9 setting for GPIO     \hideinitializer */
    207. 

  207. #define SYS_GPA_MFPH_PA9MFP_SC0_PWR     (0x2UL<<SYS_GPA_MFPH_PA9MFP_Pos)           /*!< GPA_MFPH PA9 setting for SC0_PWR    \hideinitializer */
    208. 

  208. #define SYS_GPA_MFPH_PA9MFP_SPI3_MISO0  (0x3UL<<SYS_GPA_MFPH_PA9MFP_Pos)           /*!< GPA_MFPH PA9 setting for SPI3_MISO0     \hideinitializer */
    209. 

  209. #define SYS_GPA_MFPH_PA9MFP_PWM1_CH1    (0x4UL<<SYS_GPA_MFPH_PA9MFP_Pos)           /*!< GPA_MFPH PA9 setting for PWM1 CH1    \hideinitializer */
    210. 

  210. #define SYS_GPA_MFPH_PA9MFP_EPWM0_CH3   (0x5UL<<SYS_GPA_MFPH_PA9MFP_Pos)           /*!< GPA_MFPH PA9 setting for EPWM0 CH3     \hideinitializer */
    211. 

  211. #define SYS_GPA_MFPH_PA9MFP_EBI_A19     (0x7UL<<SYS_GPA_MFPH_PA9MFP_Pos)           /*!< GPA_MFPH PA9 setting for EBI_A19    \hideinitializer */
    212. 

  212. 

  213. //GPA_MFPH_PA10MFP
    214. 

  214. #define SYS_GPA_MFPH_PA10MFP_GPIO       (0x0UL<<SYS_GPA_MFPH_PA10MFP_Pos)           /*!< GPA_MFPH PA10 setting for GPIO   \hideinitializer */
    215. 

  215. #define SYS_GPA_MFPH_PA10MFP_SC0_DAT    (0x2UL<<SYS_GPA_MFPH_PA10MFP_Pos)           /*!< GPA_MFPH PA10 setting for SC0_DAT  \hideinitializer */
    216. 

  216. #define SYS_GPA_MFPH_PA10MFP_SPI3_MOSI0 (0x3UL<<SYS_GPA_MFPH_PA10MFP_Pos)           /*!< GPA_MFPH PA10 setting for SPI3_MOSI0   \hideinitializer */
    217. 

  217. #define SYS_GPA_MFPH_PA10MFP_PWM1_CH0   (0x4UL<<SYS_GPA_MFPH_PA10MFP_Pos)           /*!< GPA_MFPH PA10 setting for PWM1_CH0  \hideinitializer */
    218. 

  218. #define SYS_GPA_MFPH_PA10MFP_EPWM0_CH2  (0x5UL<<SYS_GPA_MFPH_PA10MFP_Pos)           /*!< GPA_MFPH PA10 setting for EPWM0_CH2   \hideinitializer */
    219. 

  219. #define SYS_GPA_MFPH_PA10MFP_EBI_A20    (0x7UL<<SYS_GPA_MFPH_PA10MFP_Pos)           /*!< GPA_MFPH PA10 setting for EBI_A20  \hideinitializer */
    220. 

  220. 

  221. //GPA_MFPH_PA11MFP
    222. 

  222. #define SYS_GPA_MFPH_PA11MFP_GPIO       (0x0UL<<SYS_GPA_MFPH_PA11MFP_Pos)           /*!< GPA_MFPH PA11 setting for GPIO   \hideinitializer */
    223. 

  223. #define SYS_GPA_MFPH_PA11MFP_UART0_RTS    (0x1UL<<SYS_GPA_MFPH_PA11MFP_Pos)           /*!< GPA_MFPH PA11 setting for UART0_RTS   \hideinitializer */
    224. 

  224. #define SYS_GPA_MFPH_PA11MFP_SPI3_MISO1 (0x3UL<<SYS_GPA_MFPH_PA11MFP_Pos)           /*!< GPA_MFPH PA11 setting for SPI3_MISO1   \hideinitializer */
    225. 

  225. #define SYS_GPA_MFPH_PA11MFP_PWM0_CH5   (0x4UL<<SYS_GPA_MFPH_PA11MFP_Pos)           /*!< GPA_MFPH PA11 setting for PWM0_CH5   \hideinitializer */
    226. 

  226. #define SYS_GPA_MFPH_PA11MFP_EPWM0_CH1  (0x5UL<<SYS_GPA_MFPH_PA11MFP_Pos)           /*!< GPA_MFPH PA11 setting for EPWM0_CH1   \hideinitializer */
    227. 

  227. #define SYS_GPA_MFPH_PA11MFP_EBI_AD0    (0x7UL<<SYS_GPA_MFPH_PA11MFP_Pos)           /*!< GPA_MFPH PA11 setting for EBI_AD0   \hideinitializer */
    228. 

  228. 

  229. //GPA_MFPH_PA12MFP
    230. 

  230. #define SYS_GPA_MFPH_PA12MFP_GPIO       (0x0UL<<SYS_GPA_MFPH_PA12MFP_Pos)           /*!< GPA_MFPH PA12 setting for GPIO   \hideinitializer */
    231. 

  231. #define SYS_GPA_MFPH_PA12MFP_UART0_CTS    (0x1UL<<SYS_GPA_MFPH_PA12MFP_Pos)           /*!< GPA_MFPH PA12 setting for UART0_CTS   \hideinitializer */
    232. 

  232. #define SYS_GPA_MFPH_PA12MFP_SPI3_MOSI1 (0x3UL<<SYS_GPA_MFPH_PA12MFP_Pos)           /*!< GPA_MFPH PA12 setting for SPI3_MOSI1   \hideinitializer */
    233. 

  233. #define SYS_GPA_MFPH_PA12MFP_PWM0_CH4   (0x4UL<<SYS_GPA_MFPH_PA12MFP_Pos)           /*!< GPA_MFPH PA12 setting for PWM0_CH4   \hideinitializer */
    234. 

  234. #define SYS_GPA_MFPH_PA12MFP_EPWM0_CH0  (0x5UL<<SYS_GPA_MFPH_PA12MFP_Pos)           /*!< GPA_MFPH PA12 setting for EPWM0_CH0   \hideinitializer */
    235. 

  235. #define SYS_GPA_MFPH_PA12MFP_EBI_AD1    (0x7UL<<SYS_GPA_MFPH_PA12MFP_Pos)           /*!< GPA_MFPH PA12 setting for EBI_AD1   \hideinitializer */
    236. 

  236. 

  237. //GPA_MFPH_PA13MFP
    238. 

  238. #define SYS_GPA_MFPH_PA13MFP_GPIO       (0x0UL<<SYS_GPA_MFPH_PA13MFP_Pos)           /*!< GPA_MFPH PA13 setting for GPIO   \hideinitializer */
    239. 

  239. #define SYS_GPA_MFPH_PA13MFP_UART0_RXD    (0x1UL<<SYS_GPA_MFPH_PA13MFP_Pos)           /*!< GPA_MFPH PA13 setting for UART0_RXD   \hideinitializer */
    240. 

  240. #define SYS_GPA_MFPH_PA13MFP_SC3_DAT    (0x3UL<<SYS_GPA_MFPH_PA13MFP_Pos)           /*!< GPA_MFPH PA13 setting for SC3_DAT   \hideinitializer */
    241. 

  241. #define SYS_GPA_MFPH_PA13MFP_PWM1_CH4   (0x4UL<<SYS_GPA_MFPH_PA13MFP_Pos)           /*!< GPA_MFPH PA13 setting for PWM1_CH4   \hideinitializer */
    242. 

  242. #define SYS_GPA_MFPH_PA13MFP_EBI_AD2    (0x7UL<<SYS_GPA_MFPH_PA13MFP_Pos)           /*!< GPA_MFPH PA13 setting for EBI_AD2   \hideinitializer */
    243. 

  243. 

  244. //GPA_MFPH_PA14MFP
    245. 

  245. #define SYS_GPA_MFPH_PA14MFP_GPIO       (0x0UL<<SYS_GPA_MFPH_PA14MFP_Pos)           /*!< GPA_MFPH PA14 setting for GPIO   \hideinitializer */
    246. 

  246. #define SYS_GPA_MFPH_PA14MFP_UART0_TXD    (0x1UL<<SYS_GPA_MFPH_PA14MFP_Pos)           /*!< GPA_MFPH PA14 setting for UART0_TXD   \hideinitializer */
    247. 

  247. #define SYS_GPA_MFPH_PA14MFP_SC3_CLK    (0x3UL<<SYS_GPA_MFPH_PA14MFP_Pos)           /*!< GPA_MFPH PA14 setting for SC3_CLK   \hideinitializer */
    248. 

  248. #define SYS_GPA_MFPH_PA14MFP_PWM1_CH5   (0x4UL<<SYS_GPA_MFPH_PA14MFP_Pos)           /*!< GPA_MFPH PA14 setting for PWM1_CH5   \hideinitializer */
    249. 

  249. #define SYS_GPA_MFPH_PA14MFP_EBI_AD3    (0x7UL<<SYS_GPA_MFPH_PA14MFP_Pos)           /*!< GPA_MFPH PA14 setting for EBI_AD3   \hideinitializer */
    250. 

  250. //GPA_MFPH_PA15MFP
    251. 

  251. #define SYS_GPA_MFPH_PA15MFP_GPIO       (0x0UL<<SYS_GPA_MFPH_PA15MFP_Pos)           /*!< GPA_MFPH PA15 setting for GPIO   \hideinitializer */
    252. 

  252. #define SYS_GPA_MFPH_PA15MFP_SC3_PWR    (0x1UL<<SYS_GPA_MFPH_PA15MFP_Pos)           /*!< GPA_MFPH PA15 setting for SC3_PWR   \hideinitializer */
    253. 

  253. #define SYS_GPA_MFPH_PA15MFP_UART2_RTS    (0x2UL<<SYS_GPA_MFPH_PA15MFP_Pos)           /*!< GPA_MFPH PA15 setting for UART2_RTS   \hideinitializer */
    254. 

  254. #define SYS_GPA_MFPH_PA15MFP_I2C0_SCL   (0x4UL<<SYS_GPA_MFPH_PA15MFP_Pos)           /*!< GPA_MFPH PA15 setting for I2C0_SCL   \hideinitializer */
    255. 

  255. #define SYS_GPA_MFPH_PA15MFP_EBI_A21    (0x7UL<<SYS_GPA_MFPH_PA15MFP_Pos)           /*!< GPA_MFPH PA15 setting for EBI_A21   \hideinitializer */
    256. 

  256. 

  257. 

  258. //GPB_MFPL_PB0MFP
    259. 

  259. #define SYS_GPB_MFPL_PB0MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for GPIO     \hideinitializer */
    260. 

  260. #define SYS_GPB_MFPL_PB0MFP_USB0_OTG5V_ST  (0x1UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for USB0_OTG5V_ST    \hideinitializer */
    261. 

  261. #define SYS_GPB_MFPL_PB0MFP_I2C4_SCL       (0x2UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for I2C4_SCL     \hideinitializer */
    262. 

  262. #define SYS_GPB_MFPL_PB0MFP_INT1           (0x8UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for INT1     \hideinitializer */
    263. 

  263. 

  264. //GPB_MFPL_PB1MFP
    265. 

  265. #define SYS_GPB_MFPL_PB1MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB1MFP_Pos)           /*!< GPB_MFPL PB1 setting for GPIO     \hideinitializer */
    266. 

  266. #define SYS_GPB_MFPL_PB1MFP_USB0_OTG5V_EN  (0x1UL<<SYS_GPB_MFPL_PB1MFP_Pos)           /*!< GPB_MFPL PB1 setting for USB0_OTG5V_EN    \hideinitializer */
    267. 

  267. #define SYS_GPB_MFPL_PB1MFP_I2C4_SDA       (0x2UL<<SYS_GPB_MFPL_PB1MFP_Pos)           /*!< GPB_MFPL PB1 setting for I2C4_SDA     \hideinitializer */
    268. 

  268. #define SYS_GPB_MFPL_PB1MFP_TM1_CNT_OUT    (0x3UL<<SYS_GPB_MFPL_PB1MFP_Pos)           /*!< GPB_MFPL PB1 setting for TM1_CNT_OUT    \hideinitializer */
    269. 

  269. 

  270. //GPB_MFPL_PB2MFP
    271. 

  271. #define SYS_GPB_MFPL_PB2MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB2MFP_Pos)           /*!< GPB_MFPL PB2 setting for GPIO     \hideinitializer */
    272. 

  272. #define SYS_GPB_MFPL_PB2MFP_UART1_RXD      (0x1UL<<SYS_GPB_MFPL_PB2MFP_Pos)           /*!< GPB_MFPL PB2 setting for UART1_RXD    \hideinitializer */
    273. 

  273. #define SYS_GPB_MFPL_PB2MFP_SPI2_SS0       (0x2UL<<SYS_GPB_MFPL_PB2MFP_Pos)           /*!< GPB_MFPL PB2 setting for SPI2_SS0     \hideinitializer */
    274. 

  274. #define SYS_GPB_MFPL_PB2MFP_USB1_D_N       (0x3UL<<SYS_GPB_MFPL_PB2MFP_Pos)           /*!< GPB_MFPL PB2 setting for USB1_D_N     \hideinitializer */
    275. 

  275. #define SYS_GPB_MFPL_PB2MFP_EBI_AD4        (0x7UL<<SYS_GPB_MFPL_PB2MFP_Pos)           /*!< GPB_MFPL PB2 setting for EBI_AD4    \hideinitializer */
    276. 

  276. 

  277. //GPB_MFPL_PB3MFP
    278. 

  278. #define SYS_GPB_MFPL_PB3MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB3MFP_Pos)           /*!< GPB_MFPL PB3 setting for GPIO     \hideinitializer */
    279. 

  279. #define SYS_GPB_MFPL_PB3MFP_UART1_TXD        (0x1UL<<SYS_GPB_MFPL_PB3MFP_Pos)           /*!< GPB_MFPL PB3 setting for UART1_TXD    \hideinitializer */
    280. 

  280. #define SYS_GPB_MFPL_PB3MFP_SPI2_CLK       (0x2UL<<SYS_GPB_MFPL_PB3MFP_Pos)           /*!< GPB_MFPL PB3 setting for SPI2_CLK     \hideinitializer */
    281. 

  281. #define SYS_GPB_MFPL_PB3MFP_USB1_D_P       (0x3UL<<SYS_GPB_MFPL_PB3MFP_Pos)           /*!< GPB_MFPL PB3 setting for USB1_D_P     \hideinitializer */
    282. 

  282. #define SYS_GPB_MFPL_PB3MFP_EBI_AD5        (0x7UL<<SYS_GPB_MFPL_PB3MFP_Pos)           /*!< GPB_MFPL PB3 setting for EBI_AD5    \hideinitializer */
    283. 

  283. 

  284. //GPB_MFPL_PB4MFP
    285. 

  285. #define SYS_GPB_MFPL_PB4MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB4MFP_Pos)           /*!< GPB_MFPL PB4 setting for GPIO     \hideinitializer */
    286. 

  286. #define SYS_GPB_MFPL_PB4MFP_UART1_RTS      (0x1UL<<SYS_GPB_MFPL_PB4MFP_Pos)           /*!< GPB_MFPL PB4 setting for UART1_RTS    \hideinitializer */
    287. 

  287. #define SYS_GPB_MFPL_PB4MFP_SPI2_MISO0     (0x2UL<<SYS_GPB_MFPL_PB4MFP_Pos)           /*!< GPB_MFPL PB4 setting for SPI2_MISO0     \hideinitializer */
    288. 

  288. #define SYS_GPB_MFPL_PB4MFP_UART4_RXD      (0x3UL<<SYS_GPB_MFPL_PB4MFP_Pos)           /*!< GPB_MFPL PB4 setting for UART4_RXD    \hideinitializer */
    289. 

  289. #define SYS_GPB_MFPL_PB4MFP_TM0_CNT_OUT    (0x4UL<<SYS_GPB_MFPL_PB4MFP_Pos)           /*!< GPB_MFPL PB4 setting for TM0_CNT_OUT      \hideinitializer */
    290. 

  290. #define SYS_GPB_MFPL_PB4MFP_EBI_AD6        (0x7UL<<SYS_GPB_MFPL_PB4MFP_Pos)           /*!< GPB_MFPL PB4 setting for EBI_AD6    \hideinitializer */
    291. 

  291. 

  292. //GPB_MFPL_PB5MFP
    293. 

  293. #define SYS_GPB_MFPL_PB5MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB5MFP_Pos)           /*!< GPB_MFPL PB5 setting for GPIO     \hideinitializer */
    294. 

  294. #define SYS_GPB_MFPL_PB5MFP_UART1_CTS      (0x1UL<<SYS_GPB_MFPL_PB5MFP_Pos)           /*!< GPB_MFPL PB5 setting for UART1_CTS    \hideinitializer */
    295. 

  295. #define SYS_GPB_MFPL_PB5MFP_SPI2_MOSI0     (0x2UL<<SYS_GPB_MFPL_PB5MFP_Pos)           /*!< GPB_MFPL PB5 setting for SPI2_MOSI0     \hideinitializer */
    296. 

  296. #define SYS_GPB_MFPL_PB5MFP_UART4_TXD      (0x3UL<<SYS_GPB_MFPL_PB5MFP_Pos)           /*!< GPB_MFPL PB5 setting for UART4_TXD    \hideinitializer */
    297. 

  297. #define SYS_GPB_MFPL_PB5MFP_EBI_AD7        (0x7UL<<SYS_GPB_MFPL_PB5MFP_Pos)           /*!< GPB_MFPL PB5 setting for EBI_AD7    \hideinitializer */
    298. 

  298. 

  299. //GPB_MFPL_PB6MFP
    300. 

  300. #define SYS_GPB_MFPL_PB6MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB6MFP_Pos)           /*!< GPB_MFPL PB6 setting for GPIO     \hideinitializer */
    301. 

  301. #define SYS_GPB_MFPL_PB6MFP_I2C2_SCL       (0x1UL<<SYS_GPB_MFPL_PB6MFP_Pos)           /*!< GPB_MFPL PB6 setting for I2C2_SCL     \hideinitializer */
    302. 

  302. #define SYS_GPB_MFPL_PB6MFP_BRAKE01        (0x2UL<<SYS_GPB_MFPL_PB6MFP_Pos)           /*!< GPB_MFPL PB6 setting for BRAKE01      \hideinitializer */
    303. 

  303. #define SYS_GPB_MFPL_PB6MFP_UART4_RTS      (0x3UL<<SYS_GPB_MFPL_PB6MFP_Pos)           /*!< GPB_MFPL PB6 setting for UART4_RTS    \hideinitializer */
    304. 

  304. #define SYS_GPB_MFPL_PB6MFP_PWM1_CH4       (0x4UL<<SYS_GPB_MFPL_PB6MFP_Pos)           /*!< GPB_MFPL PB6 setting for PWM1_CH4     \hideinitializer */
    305. 

  305. #define SYS_GPB_MFPL_PB6MFP_EPWM1_CH0      (0x5UL<<SYS_GPB_MFPL_PB6MFP_Pos)           /*!< GPB_MFPL PB6 setting for EPWM1_CH0     \hideinitializer */
    306. 

  306. #define SYS_GPB_MFPL_PB6MFP_EBI_AD8        (0x7UL<<SYS_GPB_MFPL_PB6MFP_Pos)           /*!< GPB_MFPL PB6 setting for EBI_AD8    \hideinitializer */
    307. 

  307. 

  308. //GPB_MFPL_PB7MFP
    309. 

  309. #define SYS_GPB_MFPL_PB7MFP_GPIO            (0x0UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for GPIO     \hideinitializer */
    310. 

  310. #define SYS_GPB_MFPL_PB7MFP_I2C2_SDA        (0x1UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for I2C2_SDA     \hideinitializer */
    311. 

  311. #define SYS_GPB_MFPL_PB7MFP_BRAKE00         (0x2UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for BRAKE00    \hideinitializer */
    312. 

  312. #define SYS_GPB_MFPL_PB7MFP_UART4_CTS       (0x3UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for UART4_CTS    \hideinitializer */
    313. 

  313. #define SYS_GPB_MFPL_PB7MFP_PWM1_CH5        (0x4UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for PWM1_CH5    \hideinitializer */
    314. 

  314. #define SYS_GPB_MFPL_PB7MFP_EPWM1_CH1       (0x5UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for EPWM1_CH1     \hideinitializer */
    315. 

  315. #define SYS_GPB_MFPL_PB7MFP_ETM_TRACE_DATA3 (0x6UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for ETM_TRACE_DATA3    \hideinitializer */
    316. 

  316. #define SYS_GPB_MFPL_PB7MFP_EBI_AD9         (0x7UL<<SYS_GPB_MFPL_PB7MFP_Pos)           /*!< GPB_MFPL PB7 setting for EBI_AD9    \hideinitializer */
    317. 

  317. 

  318. //GPB_MFPL_PB8MFP
    319. 

  319. #define SYS_GPB_MFPH_PB8MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB8MFP_Pos)           /*!< GPB_MFPH PB8 setting for GPIO     \hideinitializer */
    320. 

  320. #define SYS_GPB_MFPH_PB8MFP_UART5_CTS       (0x1UL<<SYS_GPB_MFPH_PB8MFP_Pos)           /*!< GPB_MFPH PB8 setting for UART5_CTS     \hideinitializer */
    321. 

  321. #define SYS_GPB_MFPH_PB8MFP_EPWM1_CH2       (0x5UL<<SYS_GPB_MFPH_PB8MFP_Pos)           /*!< GPB_MFPH PB8 setting for EPWM1_CH2    \hideinitializer */
    322. 

  322. #define SYS_GPB_MFPH_PB8MFP_ETM_TRACE_DATA2 (0x6UL<<SYS_GPB_MFPH_PB8MFP_Pos)           /*!< GPB_MFPH PB8 setting for ETM_TRACE_DATA2     \hideinitializer */
    323. 

  323. #define SYS_GPB_MFPH_PB8MFP_EBI_AD10        (0x7UL<<SYS_GPB_MFPH_PB8MFP_Pos)           /*!< GPB_MFPH PB8 setting for EBI_AD10    \hideinitializer */
    324. 

  324. 

  325. //GPB_MFPH_PB9MFP
    326. 

  326. #define SYS_GPB_MFPH_PB9MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB9MFP_Pos)           /*!< GPB_MFPH PB9 setting for GPIO    \hideinitializer */
    327. 

  327. #define SYS_GPB_MFPH_PB9MFP_UART5_RTS       (0x1UL<<SYS_GPB_MFPH_PB9MFP_Pos)           /*!< GPB_MFPH PB9 setting for UART5_RTS    \hideinitializer */
    328. 

  328. #define SYS_GPB_MFPH_PB9MFP_EPWM1_CH3       (0x5UL<<SYS_GPB_MFPH_PB9MFP_Pos)           /*!< GPB_MFPH PB9 setting for EPWM1_CH3     \hideinitializer */
    329. 

  329. #define SYS_GPB_MFPH_PB9MFP_ETM_TRACE_DATA1 (0x6UL<<SYS_GPB_MFPH_PB9MFP_Pos)           /*!< GPB_MFPH PB9 setting for ETM_TRACE_DATA1      \hideinitializer */
    330. 

  330. #define SYS_GPB_MFPH_PB9MFP_EBI_AD11        (0x7UL<<SYS_GPB_MFPH_PB9MFP_Pos)           /*!< GPB_MFPH PB9 setting for EBI_AD11     \hideinitializer */
    331. 

  331. 

  332. //GPB_MFPH_PB10MFP
    333. 

  333. #define SYS_GPB_MFPH_PB10MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB10MFP_Pos)           /*!< GPB_MFPH PB10 setting for GPIO   \hideinitializer */
    334. 

  334. #define SYS_GPB_MFPH_PB10MFP_UART5_TXD       (0x1UL<<SYS_GPB_MFPH_PB10MFP_Pos)           /*!< GPB_MFPH PB10 setting for UART5_TXD  \hideinitializer */
    335. 

  335. #define SYS_GPB_MFPH_PB10MFP_EPWM1_CH4       (0x5UL<<SYS_GPB_MFPH_PB10MFP_Pos)           /*!< GPB_MFPH PB10 setting for EPWM1_CH4   \hideinitializer */
    336. 

  336. #define SYS_GPB_MFPH_PB10MFP_ETM_TRACE_DATA0 (0x6UL<<SYS_GPB_MFPH_PB10MFP_Pos)           /*!< GPB_MFPH PB10 setting for ETM_TRACE_DATA0  \hideinitializer */
    337. 

  337. #define SYS_GPB_MFPH_PB10MFP_EBI_AD12        (0x7UL<<SYS_GPB_MFPH_PB10MFP_Pos)           /*!< GPB_MFPH PB10 setting for EBI_AD12   \hideinitializer */
    338. 

  338. 

  339. //GPB_MFPH_PB11MFP
    340. 

  340. #define SYS_GPB_MFPH_PB11MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB11MFP_Pos)           /*!< GPB_MFPH PB11 setting for GPIO   \hideinitializer */
    341. 

  341. #define SYS_GPB_MFPH_PB11MFP_UART5_RXD       (0x1UL<<SYS_GPB_MFPH_PB11MFP_Pos)           /*!< GPB_MFPH PB11 setting for UART5_RXD   \hideinitializer */
    342. 

  342. #define SYS_GPB_MFPH_PB11MFP_EPWM1_CH5       (0x5UL<<SYS_GPB_MFPH_PB11MFP_Pos)           /*!< GPB_MFPH PB11 setting for EPWM1_CH5   \hideinitializer */
    343. 

  343. #define SYS_GPB_MFPH_PB11MFP_ETM_TRACE_CLK   (0x6UL<<SYS_GPB_MFPH_PB11MFP_Pos)           /*!< GPB_MFPH PB11 setting for ETM_TRACE_CLK   \hideinitializer */
    344. 

  344. #define SYS_GPB_MFPH_PB11MFP_EBI_AD13        (0x7UL<<SYS_GPB_MFPH_PB11MFP_Pos)           /*!< GPB_MFPH PB11 setting for EBI_AD13   \hideinitializer */
    345. 

  345. 

  346. //GPB_MFPH_PB12MFP
    347. 

  347. #define SYS_GPB_MFPH_PB12MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB12MFP_Pos)           /*!< GPB_MFPH PB12 setting for GPIO   \hideinitializer */
    348. 

  348. #define SYS_GPB_MFPH_PB12MFP_UART4_RTS       (0x1UL<<SYS_GPB_MFPH_PB12MFP_Pos)           /*!< GPB_MFPH PB12 setting for UART4_RTS   \hideinitializer */
    349. 

  349. #define SYS_GPB_MFPH_PB12MFP_SPI2_MISO1      (0x2UL<<SYS_GPB_MFPH_PB12MFP_Pos)           /*!< GPB_MFPH PB12 setting for _SPI2_MISO1  \hideinitializer */
    350. 

  350. #define SYS_GPB_MFPH_PB12MFP_CAN0_RXD        (0x3UL<<SYS_GPB_MFPH_PB12MFP_Pos)           /*!< GPB_MFPH PB12 setting for CAN0_RXD   \hideinitializer */
    351. 

  351. #define SYS_GPB_MFPH_PB12MFP_EMAC_MII_MDC    (0x6UL<<SYS_GPB_MFPH_PB12MFP_Pos)           /*!< GPB_MFPH PB12 setting for EMAC_MII_MDC   \hideinitializer */
    352. 

  352. #define SYS_GPB_MFPH_PB12MFP_EBI_AD14        (0x7UL<<SYS_GPB_MFPH_PB12MFP_Pos)           /*!< GPB_MFPH PB12 setting for EBI_AD4  \hideinitializer */
    353. 

  353. 

  354. //GPB_MFPH_PB13MFP
    355. 

  355. #define SYS_GPB_MFPH_PB13MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB13MFP_Pos)           /*!< GPB_MFPH PB13 setting for GPIO   \hideinitializer */
    356. 

  356. #define SYS_GPB_MFPH_PB13MFP_UART4_CTS       (0x1UL<<SYS_GPB_MFPH_PB13MFP_Pos)           /*!< GPB_MFPH PB13 setting for UART4_CTS   \hideinitializer */
    357. 

  357. #define SYS_GPB_MFPH_PB13MFP_SPI2_MOSI1      (0x2UL<<SYS_GPB_MFPH_PB13MFP_Pos)           /*!< GPB_MFPH PB13 setting for SPI2_MOSI1   \hideinitializer */
    358. 

  358. #define SYS_GPB_MFPH_PB13MFP_CAN0_TXD        (0x3UL<<SYS_GPB_MFPH_PB13MFP_Pos)           /*!< GPB_MFPH PB13 setting for CAN0_TXD   \hideinitializer */
    359. 

  359. #define SYS_GPB_MFPH_PB13MFP_EMAC_MII_MDIO   (0x6UL<<SYS_GPB_MFPH_PB13MFP_Pos)           /*!< GPB_MFPH PB13 setting for EMAC_MII_MDIO   \hideinitializer */
    360. 

  360. #define SYS_GPB_MFPH_PB13MFP_EBI_AD15        (0x7UL<<SYS_GPB_MFPH_PB13MFP_Pos)           /*!< GPB_MFPH PB13 setting for EBI_AD15   \hideinitializer */
    361. 

  361. 

  362. //GPB_MFPH_PB14MFP
    363. 

  363. #define SYS_GPB_MFPH_PB14MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB14MFP_Pos)           /*!< GPB_MFPH PB14 setting for GPIO   \hideinitializer */
    364. 

  364. #define SYS_GPB_MFPH_PB14MFP_I2S1_MCLK       (0x1UL<<SYS_GPB_MFPH_PB14MFP_Pos)           /*!< GPB_MFPH PB14 setting for I2S1_MCLK   \hideinitializer */
    365. 

  365. #define SYS_GPB_MFPH_PB14MFP_SC1_RST         (0x2UL<<SYS_GPB_MFPH_PB14MFP_Pos)           /*!< GPB_MFPH PB14 setting for SC1_RST   \hideinitializer */
    366. 

  366. #define SYS_GPB_MFPH_PB14MFP_BRAKE01         (0x4UL<<SYS_GPB_MFPH_PB14MFP_Pos)           /*!< GPB_MFPH PB14 setting for BRAKE01   \hideinitializer */
    367. 

  367. #define SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC    (0x6UL<<SYS_GPB_MFPH_PB14MFP_Pos)           /*!< GPB_MFPH PB14 setting for EMAC_MII_MDC   \hideinitializer */
    368. 

  368. 

  369. //GPB_MFPH_PB15MFP
    370. 

  370. #define SYS_GPB_MFPH_PB15MFP_GPIO            (0x0UL<<SYS_GPB_MFPH_PB15MFP_Pos)           /*!< GPA_MFPH PB15 setting for GPIO   \hideinitializer */
    371. 

  371. #define SYS_GPB_MFPH_PB15MFP_I2S1_DO         (0x1UL<<SYS_GPB_MFPH_PB15MFP_Pos)           /*!< GPA_MFPH PB15 setting for I2S1_DO  \hideinitializer */
    372. 

  372. #define SYS_GPB_MFPH_PB15MFP_SC1_DAT         (0x2UL<<SYS_GPB_MFPH_PB15MFP_Pos)           /*!< GPA_MFPH PB15 setting for SC1_DAT  \hideinitializer */
    373. 

  373. #define SYS_GPB_MFPH_PB15MFP_BRAKE00         (0x4UL<<SYS_GPB_MFPH_PB15MFP_Pos)           /*!< GPA_MFPH PB15 setting for BRAKE00   \hideinitializer */
    374. 

  374. #define SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO   (0x6UL<<SYS_GPB_MFPH_PB15MFP_Pos)           /*!< GPA_MFPH PB15 setting for EMAC_MII_MDIO  \hideinitializer */
    375. 

  375. 

  376. 

  377. //GPC_MFPL_PC0MFP
    378. 

  378. #define SYS_GPC_MFPL_PC0MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC0MFP_Pos)           /*!< GPC_MFPL PC0 setting for GPIO     \hideinitializer */
    379. 

  379. #define SYS_GPC_MFPL_PC0MFP_I2S1_DI          (0x1UL<<SYS_GPC_MFPL_PC0MFP_Pos)           /*!< GPC_MFPL PC0 setting for I2S1_D1    \hideinitializer */
    380. 

  380. #define SYS_GPC_MFPL_PC0MFP_SC1_DAT          (0x2UL<<SYS_GPC_MFPL_PC0MFP_Pos)           /*!< GPC_MFPL PC0 setting for SC1_DAT    \hideinitializer */
    381. 

  381. #define SYS_GPC_MFPL_PC0MFP_UART4_RXD        (0x3UL<<SYS_GPC_MFPL_PC0MFP_Pos)           /*!< GPC_MFPL PC0 setting for UART4_RXD    \hideinitializer */
    382. 

  382. #define SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK      (0x6UL<<SYS_GPC_MFPL_PC0MFP_Pos)           /*!< GPC_MFPL PC0 setting for EMAC_REFCLK    \hideinitializer */
    383. 

  383. #define SYS_GPC_MFPL_PC0MFP_EBI_MCLK         (0x7UL<<SYS_GPC_MFPL_PC0MFP_Pos)           /*!< GPC_MFPL PC0 setting for EBI_MCLK     \hideinitializer */
    384. 

  384. #define SYS_GPC_MFPL_PC0MFP_INT2             (0x8UL<<SYS_GPC_MFPL_PC0MFP_Pos)           /*!< GPC_MFPL PC0 setting for INT2     \hideinitializer */
    385. 

  385. 

  386. 

  387. //GPC_MFPL_PC1MFP
    388. 

  388. #define SYS_GPC_MFPL_PC1MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC1MFP_Pos)           /*!< GPC_MFPL PC1 setting for GPIO     \hideinitializer */
    389. 

  389. #define SYS_GPC_MFPL_PC1MFP_I2S1_BCLK        (0x1UL<<SYS_GPC_MFPL_PC1MFP_Pos)           /*!< GPC_MFPL PC1 setting for I2S1_BCLK    \hideinitializer */
    390. 

  390. #define SYS_GPC_MFPL_PC1MFP_SC1_CLK          (0x2UL<<SYS_GPC_MFPL_PC1MFP_Pos)           /*!< GPC_MFPL PC1 setting for SC1_CLK    \hideinitializer */
    391. 

  391. #define SYS_GPC_MFPL_PC1MFP_UART4_TXD        (0x3UL<<SYS_GPC_MFPL_PC1MFP_Pos)           /*!< GPC_MFPL PC1 setting for UART4_TXD      \hideinitializer */
    392. 

  392. #define SYS_GPC_MFPL_PC1MFP_TM3_CNT_OUT      (0x5UL<<SYS_GPC_MFPL_PC1MFP_Pos)           /*!< GPC_MFPL PC1 setting for TM3_CNT_OUT    \hideinitializer */
    393. 

  393. #define SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR   (0x6UL<<SYS_GPC_MFPL_PC1MFP_Pos)           /*!< GPC_MFPL PC1 setting for EMAC_MII_RXERR     \hideinitializer */
    394. 

  394. #define SYS_GPC_MFPL_PC1MFP_EBI_AD13         (0x7UL<<SYS_GPC_MFPL_PC1MFP_Pos)           /*!< GPC_MFPL PC1 setting for EBI_AD13     \hideinitializer */
    395. 

  395. 

  396. //GPC_MFPL_PC2MFP
    397. 

  397. #define SYS_GPC_MFPL_PC2MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC2MFP_Pos)           /*!< GPC_MFPL PC2 setting for GPIO     \hideinitializer */
    398. 

  398. #define SYS_GPC_MFPL_PC2MFP_I2S1_LRCK        (0x1UL<<SYS_GPC_MFPL_PC2MFP_Pos)           /*!< GPC_MFPL PC2 setting for I2S1_LRCK    \hideinitializer */
    399. 

  399. #define SYS_GPC_MFPL_PC2MFP_SC1_PWR          (0x2UL<<SYS_GPC_MFPL_PC2MFP_Pos)           /*!< GPC_MFPL PC2 setting for SC1_PWR    \hideinitializer */
    400. 

  400. #define SYS_GPC_MFPL_PC2MFP_UART4_RTS        (0x3UL<<SYS_GPC_MFPL_PC2MFP_Pos)           /*!< GPC_MFPL PC2 setting for UART4_RTS    \hideinitializer */
    401. 

  401. #define SYS_GPC_MFPL_PC2MFP_SPI0_SS0         (0x4UL<<SYS_GPC_MFPL_PC2MFP_Pos)           /*!< GPC_MFPL PC2 setting for SPI0_SS0     \hideinitializer */
    402. 

  402. #define SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV    (0x6UL<<SYS_GPC_MFPL_PC2MFP_Pos)           /*!< GPC_MFPL PC2 setting for EMAC_MII_RXDV    \hideinitializer */
    403. 

  403. #define SYS_GPC_MFPL_PC2MFP_EBI_AD12         (0x7UL<<SYS_GPC_MFPL_PC2MFP_Pos)           /*!< GPC_MFPL PC2 setting for EBI_AD12     \hideinitializer */
    404. 

  404. 

  405. //GPC_MFPL_PC3MFP
    406. 

  406. #define SYS_GPC_MFPL_PC3MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for GPIO     \hideinitializer */
    407. 

  407. #define SYS_GPC_MFPL_PC3MFP_I2S1_MCLK        (0x1UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for I2S1_MCLK    \hideinitializer */
    408. 

  408. #define SYS_GPC_MFPL_PC3MFP_SC1_CD           (0x2UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for SC1_CD     \hideinitializer */
    409. 

  409. #define SYS_GPC_MFPL_PC3MFP_UART4_CTS        (0x3UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for UART4_CTS    \hideinitializer */
    410. 

  410. #define SYS_GPC_MFPL_PC3MFP_SPI0_MISO1       (0x4UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for SPI0_MISO1     \hideinitializer */
    411. 

  411. #define SYS_GPC_MFPL_PC3MFP_QEI0_Z           (0x5UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for QEI0_Z     \hideinitializer */
    412. 

  412. #define SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1    (0x6UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for EMAC_MII_RXD1    \hideinitializer */
    413. 

  413. #define SYS_GPC_MFPL_PC3MFP_EBI_AD11         (0x7UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for EBI_AD11     \hideinitializer */
    414. 

  414. #define SYS_GPC_MFPL_PC3MFP_ECAP0_IC2        (0x8UL<<SYS_GPC_MFPL_PC3MFP_Pos)           /*!< GPC_MFPL PC3 setting for ECAP0_IC2    \hideinitializer */
    415. 

  415. 

  416. //GPC_MFPL_PC4MFP
    417. 

  417. #define SYS_GPC_MFPL_PC4MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for GPIO     \hideinitializer */
    418. 

  418. #define SYS_GPC_MFPL_PC4MFP_I2S1_DO          (0x1UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for I2S1_DO    \hideinitializer */
    419. 

  419. #define SYS_GPC_MFPL_PC4MFP_SC1_RST          (0x2UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for SC1_RST    \hideinitializer */
    420. 

  420. #define SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1       (0x4UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for SPI0_MOSI1     \hideinitializer */
    421. 

  421. #define SYS_GPC_MFPL_PC4MFP_QEI0_B           (0x5UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for QEI0_B     \hideinitializer */
    422. 

  422. #define SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0    (0x6UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for EMAC_MII_RXD0    \hideinitializer */
    423. 

  423. #define SYS_GPC_MFPL_PC4MFP_EBI_AD10         (0x7UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for EBI_AD10     \hideinitializer */
    424. 

  424. #define SYS_GPC_MFPL_PC4MFP_ECAP0_IC1        (0x8UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for ECAP0_IC1    \hideinitializer */
    425. 

  425. 

  426. //GPC_MFPL_PC5MFP
    427. 

  427. #define SYS_GPC_MFPL_PC5MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC5MFP_Pos)           /*!< GPC_MFPL PC5 setting for GPIO     \hideinitializer */
    428. 

  428. #define SYS_GPC_MFPL_PC5MFP_CLK_O            (0x1UL<<SYS_GPC_MFPL_PC5MFP_Pos)           /*!< GPC_MFPL PC5 setting for CLK_O    \hideinitializer */
    429. 

  429. #define SYS_GPC_MFPL_PC5MFP_QEI0_A           (0x5UL<<SYS_GPC_MFPL_PC5MFP_Pos)           /*!< GPC_MFPL PC5 setting for QEI0_A     \hideinitializer */
    430. 

  430. #define SYS_GPC_MFPL_PC5MFP_EMAC_MII_RXCLK   (0x6UL<<SYS_GPC_MFPL_PC5MFP_Pos)           /*!< GPC_MFPL PC5 setting for EMAC_MII_RXCLK     \hideinitializer */
    431. 

  431. #define SYS_GPC_MFPL_PC5MFP_EBI_MCLK         (0x7UL<<SYS_GPC_MFPL_PC5MFP_Pos)           /*!< GPC_MFPL PC5 setting for EBI_MCLK     \hideinitializer */
    432. 

  432. #define SYS_GPC_MFPL_PC5MFP_ECAP0_IC0        (0x8UL<<SYS_GPC_MFPL_PC5MFP_Pos)           /*!< GPC_MFPL PC5 setting for ECAP0_IC0    \hideinitializer */
    433. 

  433. 

  434. //GPC_MFPL_PC6MFP
    435. 

  435. #define SYS_GPC_MFPL_PC6MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC6MFP_Pos)           /*!< GPC_MFPL PC6 setting for GPIO     \hideinitializer */
    436. 

  436. #define SYS_GPC_MFPL_PC6MFP_TM2_EXT          (0x1UL<<SYS_GPC_MFPL_PC6MFP_Pos)           /*!< GPC_MFPL PC6 setting for TM2_EXT    \hideinitializer */
    437. 

  437. #define SYS_GPC_MFPL_PC6MFP_SPI0_MISO0       (0x4UL<<SYS_GPC_MFPL_PC6MFP_Pos)           /*!< GPC_MFPL PC6 setting for SPI0_MISO0     \hideinitializer */
    438. 

  438. #define SYS_GPC_MFPL_PC6MFP_TM2_CNT_OUT      (0x5UL<<SYS_GPC_MFPL_PC6MFP_Pos)           /*!< GPC_MFPL PC6 setting for TM2_CNT_OUT    \hideinitializer */
    439. 

  439. #define SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0    (0x6UL<<SYS_GPC_MFPL_PC6MFP_Pos)           /*!< GPC_MFPL PC6 setting for EMAC_MII_TXD0    \hideinitializer */
    440. 

  440. #define SYS_GPC_MFPL_PC6MFP_EBI_AD9          (0x7UL<<SYS_GPC_MFPL_PC6MFP_Pos)           /*!< GPC_MFPL PC6 setting for EBI_AD9    \hideinitializer */
    441. 

  441. 

  442. //GPC_MFPL_PC7MFP
    443. 

  443. #define SYS_GPC_MFPL_PC7MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC7MFP_Pos)           /*!< GPC_MFPL PC7 setting for GPIO     \hideinitializer */
    444. 

  444. #define SYS_GPC_MFPL_PC7MFP_TM1_EXT          (0x1UL<<SYS_GPC_MFPL_PC7MFP_Pos)           /*!< GPC_MFPL PC7 setting for TM1_EXT    \hideinitializer */
    445. 

  445. #define SYS_GPC_MFPL_PC7MFP_SPI0_MOSI0       (0x4UL<<SYS_GPC_MFPL_PC7MFP_Pos)           /*!< GPC_MFPL PC7 setting for SPI0_MOSI0     \hideinitializer */
    446. 

  446. #define SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1    (0x6UL<<SYS_GPC_MFPL_PC7MFP_Pos)           /*!< GPC_MFPL PC7 setting for EMAC_MII_TXD1    \hideinitializer */
    447. 

  447. #define SYS_GPC_MFPL_PC7MFP_EBI_AD8          (0x7UL<<SYS_GPC_MFPL_PC7MFP_Pos)           /*!< GPC_MFPL PC7 setting for EBI_AD8    \hideinitializer */
    448. 

  448. 

  449. //GPC_MFPL_PC8MFP
    450. 

  450. #define SYS_GPC_MFPH_PC8MFP_GPIO             (0x0UL<<SYS_GPC_MFPH_PC8MFP_Pos)           /*!< GPC_MFPH PC8 setting for GPIO     \hideinitializer */
    451. 

  451. #define SYS_GPC_MFPH_PC8MFP_TM0_EXT          (0x1UL<<SYS_GPC_MFPH_PC8MFP_Pos)           /*!< GPC_MFPH PC8 setting for TM0_EXT    \hideinitializer */
    452. 

  452. #define SYS_GPC_MFPH_PC8MFP_SPI0_CLK         (0x4UL<<SYS_GPC_MFPH_PC8MFP_Pos)           /*!< GPC_MFPH PC8 setting for SPI0_CLK     \hideinitializer */
    453. 

  453. #define SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN    (0x6UL<<SYS_GPC_MFPH_PC8MFP_Pos)           /*!< GPC_MFPH PC8 setting for EMAC_MII_TXEN    \hideinitializer */
    454. 

  454. 

  455. //GPC_MFPH_PC9MFP
    456. 

  456. #define SYS_GPC_MFPH_PC9MFP_GPIO             (0x0UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for GPIO     \hideinitializer */
    457. 

  457. #define SYS_GPC_MFPH_PC9MFP_STADC            (0x1UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for STADC    \hideinitializer */
    458. 

  458. #define SYS_GPC_MFPH_PC9MFP_UART2_CTS        (0x2UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for UART2_CTS    \hideinitializer */
    459. 

  459. #define SYS_GPC_MFPH_PC9MFP_SC3_RST          (0x3UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for SC3_RST    \hideinitializer */
    460. 

  460. #define SYS_GPC_MFPH_PC9MFP_I2C0_SDA         (0x4UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for I2C0_SDA     \hideinitializer */
    461. 

  461. #define SYS_GPC_MFPH_PC9MFP_CAP_DATA1        (0x5UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for CAP_DATA1    \hideinitializer */
    462. 

  462. #define SYS_GPC_MFPH_PC9MFP_I2C3_SCL         (0x6UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for I2C3_SCL     \hideinitializer */
    463. 

  463. #define SYS_GPC_MFPH_PC9MFP_EBI_A22          (0x7UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for EBI_A22    \hideinitializer */
    464. 

  464. #define SYS_GPC_MFPH_PC9MFP_SD1_DAT0         (0x8UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for SD1_DAT0     \hideinitializer */
    465. 

  465. #define SYS_GPC_MFPH_PC9MFP_EBI_A6           (0x9UL<<SYS_GPC_MFPH_PC9MFP_Pos)           /*!< GPC_MFPH PC9 setting for EBI_A6     \hideinitializer */
    466. 

  466. //GPC_MFPH_PC10MFP
    467. 

  467. #define SYS_GPC_MFPH_PC10MFP_GPIO            (0x0UL<<SYS_GPC_MFPH_PC10MFP_Pos)           /*!< GPC_MFPH PC10 setting for GPIO   \hideinitializer */
    468. 

  468. #define SYS_GPC_MFPH_PC10MFP_SC3_CD          (0x1UL<<SYS_GPC_MFPH_PC10MFP_Pos)           /*!< GPC_MFPH PC10 setting for SC3_CD   \hideinitializer */
    469. 

  469. #define SYS_GPC_MFPH_PC10MFP_UART2_RXD       (0x2UL<<SYS_GPC_MFPH_PC10MFP_Pos)           /*!< GPC_MFPH PC10 setting for UART2_RXD  \hideinitializer */
    470. 

  470. #define SYS_GPC_MFPH_PC10MFP_PWM0_CH2        (0x4UL<<SYS_GPC_MFPH_PC10MFP_Pos)           /*!< GPC_MFPH PC10 setting for PWM0_CH2  \hideinitializer */
    471. 

  471. #define SYS_GPC_MFPH_PC10MFP_EBI_A23         (0x6UL<<SYS_GPC_MFPH_PC10MFP_Pos)           /*!< GPC_MFPH PC10 setting for EBI_A23  \hideinitializer */
    472. 

  472. #define SYS_GPC_MFPH_PC10MFP_EBI_AD2         (0x7UL<<SYS_GPC_MFPH_PC10MFP_Pos)           /*!< GPC_MFPH PC10 setting for EBI_AD2  \hideinitializer */
    473. 

  473. 

  474. //GPC_MFPH_PC11MFP
    475. 

  475. #define SYS_GPC_MFPH_PC11MFP_GPIO            (0x0UL<<SYS_GPC_MFPH_PC11MFP_Pos)           /*!< GPC_MFPH PC11 setting for GPIO   \hideinitializer */
    476. 

  476. #define SYS_GPC_MFPH_PC11MFP_UART2_TXD       (0x2UL<<SYS_GPC_MFPH_PC11MFP_Pos)           /*!< GPC_MFPH PC11 setting for UART2_TXD   \hideinitializer */
    477. 

  477. #define SYS_GPC_MFPH_PC11MFP_PWM0_CH3        (0x4UL<<SYS_GPC_MFPH_PC11MFP_Pos)           /*!< GPC_MFPH PC11 setting for PWM0_CH3   \hideinitializer */
    478. 

  478. #define SYS_GPC_MFPH_PC11MFP_EBI_A24         (0x6UL<<SYS_GPC_MFPH_PC11MFP_Pos)           /*!< GPC_MFPH PC11 setting for EBI_A24   \hideinitializer */
    479. 

  479. #define SYS_GPC_MFPH_PC11MFP_EBI_AD3         (0x7UL<<SYS_GPC_MFPH_PC11MFP_Pos)           /*!< GPC_MFPH PC11 setting for EBI_AD3   \hideinitializer */
    480. 

  480. 

  481. //GPC_MFPH_PC12MFP
    482. 

  482. #define SYS_GPC_MFPH_PC12MFP_GPIO            (0x0UL<<SYS_GPC_MFPH_PC12MFP_Pos)           /*!< GPC_MFPH PC12 setting for GPIO   \hideinitializer */
    483. 

  483. #define SYS_GPC_MFPH_PC12MFP_SPI1_SS0        (0x1UL<<SYS_GPC_MFPH_PC12MFP_Pos)           /*!< GPC_MFPH PC12 setting for SPI1_SS0   \hideinitializer */
    484. 

  484. #define SYS_GPC_MFPH_PC12MFP_SC4_CD          (0x2UL<<SYS_GPC_MFPH_PC12MFP_Pos)           /*!< GPC_MFPH PC12 setting for SC4_CD   \hideinitializer */
    485. 

  485. #define SYS_GPC_MFPH_PC12MFP_SD1_CDn         (0x4UL<<SYS_GPC_MFPH_PC12MFP_Pos)          /*!< GPC_MFPH PC12 setting for SD1_CDn  \hideinitializer */
    486. 

  486. #define SYS_GPC_MFPH_PC12MFP_CAP_DATA7       (0x5UL<<SYS_GPC_MFPH_PC12MFP_Pos)           /*!< GPC_MFPH PC12 setting for CAP_DATA7   \hideinitializer */
    487. 

  487. #define SYS_GPC_MFPH_PC12MFP_ETM_TRACE_DATA3 (0x6UL<<SYS_GPC_MFPH_PC12MFP_Pos)           /*!< GPC_MFPH PC12 setting for ETM_TRACE_DATA3   \hideinitializer */
    488. 

  488. #define SYS_GPC_MFPH_PC12MFP_EBI_A0          (0x7UL<<SYS_GPC_MFPH_PC12MFP_Pos)           /*!< GPC_MFPH PC12 setting for MFP_EBI_A0   \hideinitializer */
    489. 

  489. 

  490. //GPC_MFPH_PC13MFP
    491. 

  491. #define SYS_GPC_MFPH_PC13MFP_GPIO            (0x0UL<<SYS_GPC_MFPH_PC13MFP_Pos)           /*!< GPC_MFPH PC13 setting for GPIO   \hideinitializer */
    492. 

  492. #define SYS_GPC_MFPH_PC13MFP_SPI1_MOSI1      (0x1UL<<SYS_GPC_MFPH_PC13MFP_Pos)           /*!< GPC_MFPH PC13 setting for SPI1_MOSI1   \hideinitializer */
    493. 

  493. #define SYS_GPC_MFPH_PC13MFP_SC4_RST         (0x2UL<<SYS_GPC_MFPH_PC13MFP_Pos)           /*!< GPC_MFPH PC13 setting for SC4_RST   \hideinitializer */
    494. 

  494. #define SYS_GPC_MFPH_PC13MFP_SD1_CMD         (0x4UL<<SYS_GPC_MFPH_PC13MFP_Pos)           /*!< GPC_MFPH PC13 setting for SD1_CMD   \hideinitializer */
    495. 

  495. #define SYS_GPC_MFPH_PC13MFP_CAP_DATA6       (0x5UL<<SYS_GPC_MFPH_PC13MFP_Pos)           /*!< GPC_MFPH PC13 setting for CAP_DATA6   \hideinitializer */
    496. 

  496. #define SYS_GPC_MFPH_PC13MFP_ETM_TRACE_DATA2 (0x6UL<<SYS_GPC_MFPH_PC13MFP_Pos)           /*!< GPC_MFPH PC13 setting for ETM_TRACE_DATA2   \hideinitializer */
    497. 

  497. #define SYS_GPC_MFPH_PC13MFP_EBI_A1          (0x7UL<<SYS_GPC_MFPH_PC13MFP_Pos)           /*!< GPC_MFPH PC13 setting for EBI_A1   \hideinitializer */
    498. 

  498. 

  499. //GPC_MFPH_PC14MFP
    500. 

  500. #define SYS_GPC_MFPH_PC14MFP_GPIO            (0x0UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for GPIO   \hideinitializer */
    501. 

  501. #define SYS_GPC_MFPH_PC14MFP_SPI1_MISO1      (0x1UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for SPI1_MISO1   \hideinitializer */
    502. 

  502. #define SYS_GPC_MFPH_PC14MFP_SC4_PWR         (0x2UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for SC4_PWR   \hideinitializer */
    503. 

  503. #define SYS_GPC_MFPH_PC14MFP_TM3_EXT         (0x3UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for TM3_EXT   \hideinitializer */
    504. 

  504. #define SYS_GPC_MFPH_PC14MFP_SD1_CLK         (0x4UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for SD1_CLK   \hideinitializer */
    505. 

  505. #define SYS_GPC_MFPH_PC14MFP_CAP_DATA5       (0x5UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for CAP_DATA5   \hideinitializer */
    506. 

  506. #define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_DATA1 (0x6UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for ETM_TRACE_DATA1   \hideinitializer */
    507. 

  507. #define SYS_GPC_MFPH_PC14MFP_EBI_A2          (0x7UL<<SYS_GPC_MFPH_PC14MFP_Pos)           /*!< GPC_MFPH PC14 setting for EBI_A2   \hideinitializer */
    508. 

  508. 

  509. //GPC_MFPH_PC15MFP
    510. 

  510. #define SYS_GPC_MFPH_PC15MFP_GPIO            (0x0UL<<SYS_GPC_MFPH_PC15MFP_Pos)           /*!< GPC_MFPH PC15 setting for GPIO   \hideinitializer */
    511. 

  511. #define SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0      (0x1UL<<SYS_GPC_MFPH_PC15MFP_Pos)           /*!< GPC_MFPH PC15 setting for SPI1_MOSI0   \hideinitializer */
    512. 

  512. #define SYS_GPC_MFPH_PC15MFP_SC4_DAT         (0x2UL<<SYS_GPC_MFPH_PC15MFP_Pos)           /*!< GPC_MFPH PC15 setting for SC4_DAT   \hideinitializer */
    513. 

  513. #define SYS_GPC_MFPH_PC15MFP_SD1_DAT3        (0x4UL<<SYS_GPC_MFPH_PC15MFP_Pos)           /*!< GPC_MFPH PC15 setting for SD1_DAT3   \hideinitializer */
    514. 

  514. #define SYS_GPC_MFPH_PC15MFP_CAP_DATA4       (0x5UL<<SYS_GPC_MFPH_PC15MFP_Pos)           /*!< GPC_MFPH PC15 setting for CAP_DATA4   \hideinitializer */
    515. 

  515. #define SYS_GPC_MFPH_PC15MFP_ETM_TRACE_DATA0 (0x6UL<<SYS_GPC_MFPH_PC15MFP_Pos)           /*!< GPC_MFPH PC15 setting for ETM_TRACE_DATA0   \hideinitializer */
    516. 

  516. #define SYS_GPC_MFPH_PC15MFP_EBI_A3          (0x7UL<<SYS_GPC_MFPH_PC15MFP_Pos)           /*!< GPC_MFPH PC15 setting for EBI_A3   \hideinitializer */
    517. 

  517. 

  518. //GPD_MFPL_PD0MFP
    519. 

  519. #define SYS_GPD_MFPL_PD0MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for GPIO     \hideinitializer */
    520. 

  520. #define SYS_GPD_MFPL_PD0MFP_SPI1_MISO0       (0x1UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for SPI1_MISO0     \hideinitializer */
    521. 

  521. #define SYS_GPD_MFPL_PD0MFP_SC4_CLK          (0x2UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for SC4_CLK    \hideinitializer */
    522. 

  522. #define SYS_GPD_MFPL_PD0MFP_SD1_DAT2         (0x4UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for SD1_DAT2     \hideinitializer */
    523. 

  523. #define SYS_GPD_MFPL_PD0MFP_CAP_DATA3        (0x5UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for CAP_DATA3    \hideinitializer */
    524. 

  524. #define SYS_GPD_MFPL_PD0MFP_ETM_TRACE_CLK    (0x6UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for ETM_TRACE_CLK    \hideinitializer */
    525. 

  525. #define SYS_GPD_MFPL_PD0MFP_EBI_A4           (0x7UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for EBI_A4     \hideinitializer */
    526. 

  526. #define SYS_GPD_MFPL_PD0MFP_INT3             (0x8UL<<SYS_GPD_MFPL_PD0MFP_Pos)           /*!< GPD_MFPL PD0 setting for INT3     \hideinitializer */
    527. 

  527. 

  528. //GPD_MFPL_PD1MFP
    529. 

  529. #define SYS_GPD_MFPL_PD1MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD1MFP_Pos)           /*!< GPD_MFPL PD1 setting for GPIO     \hideinitializer */
    530. 

  530. #define SYS_GPD_MFPL_PD1MFP_SPI1_CLK         (0x1UL<<SYS_GPD_MFPL_PD1MFP_Pos)           /*!< GPD_MFPL PD1 setting for SPI1_CLK     \hideinitializer */
    531. 

  531. #define SYS_GPD_MFPL_PD1MFP_TM0_CNT_OUT      (0x3UL<<SYS_GPD_MFPL_PD1MFP_Pos)           /*!< GPD_MFPL PD1 setting for TM0_CNT_OUT      \hideinitializer */
    532. 

  532. #define SYS_GPD_MFPL_PD1MFP_SD1_DAT1         (0x4UL<<SYS_GPD_MFPL_PD1MFP_Pos)           /*!< GPD_MFPL PD1 setting for SD1_DAT1     \hideinitializer */
    533. 

  533. #define SYS_GPD_MFPL_PD1MFP_CAP_DATA2        (0x5UL<<SYS_GPD_MFPL_PD1MFP_Pos)           /*!< GPD_MFPL PD1 setting for CAP_DATA2    \hideinitializer */
    534. 

  534. #define SYS_GPD_MFPL_PD1MFP_EBI_A5           (0x7UL<<SYS_GPD_MFPL_PD1MFP_Pos)           /*!< GPD_MFPL PD1 setting for EBI_A5     \hideinitializer */
    535. 

  535. 

  536. //GPD_MFPL_PD2MFP
    537. 

  537. #define SYS_GPD_MFPL_PD2MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD2MFP_Pos)           /*!< GPD_MFPL PD2 setting for GPIO     \hideinitializer */
    538. 

  538. #define SYS_GPD_MFPL_PD2MFP_STADC            (0x1UL<<SYS_GPD_MFPL_PD2MFP_Pos)           /*!< GPD_MFPL PD2 setting for STADC    \hideinitializer */
    539. 

  539. #define SYS_GPD_MFPL_PD2MFP_I2C3_SCL         (0x2UL<<SYS_GPD_MFPL_PD2MFP_Pos)           /*!< GPD_MFPL PD2 setting for I2C3_SCL     \hideinitializer */
    540. 

  540. #define SYS_GPD_MFPL_PD2MFP_SD1_DAT0         (0x4UL<<SYS_GPD_MFPL_PD2MFP_Pos)           /*!< GPD_MFPL PD2 setting for SD1_DAT0     \hideinitializer */
    541. 

  541. #define SYS_GPD_MFPL_PD2MFP_CAP_DATA1        (0x5UL<<SYS_GPD_MFPL_PD2MFP_Pos)           /*!< GPD_MFPL PD2 setting for CAP_DATA1    \hideinitializer */
    542. 

  542. #define SYS_GPD_MFPL_PD2MFP_EBI_A6           (0x7UL<<SYS_GPD_MFPL_PD2MFP_Pos)           /*!< GPD_MFPL PD2 setting for EBI_A6     \hideinitializer */
    543. 

  543. 

  544. //GPD_MFPL_PD3MFP
    545. 

  545. #define SYS_GPD_MFPL_PD3MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for GPIO     \hideinitializer */
    546. 

  546. #define SYS_GPD_MFPL_PD3MFP_SC5_CLK          (0x1UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for SC5_CLK    \hideinitializer */
    547. 

  547. #define SYS_GPD_MFPL_PD3MFP_I2C3_SDA         (0x2UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for I2C3_SDA     \hideinitializer */
    548. 

  548. #define SYS_GPD_MFPL_PD3MFP_ACMP2_O          (0x3UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for ACMP2_O    \hideinitializer */
    549. 

  549. #define SYS_GPD_MFPL_PD3MFP_SD0_CDn          (0x4UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for SD0_CDn    \hideinitializer */
    550. 

  550. #define SYS_GPD_MFPL_PD3MFP_CAP_DATA0        (0x5UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for CAP_DATA0    \hideinitializer */
    551. 

  551. #define SYS_GPD_MFPL_PD3MFP_JTAG_TDO         (0x6UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for JTAG_TDO     \hideinitializer */
    552. 

  552. #define SYS_GPD_MFPL_PD3MFP_EBI_A7           (0x7UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for EBI_A7     \hideinitializer */
    553. 

  553. 

  554. //GPD_MFPL_PD4MFP
    555. 

  555. #define SYS_GPD_MFPL_PD4MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD4MFP_Pos)           /*!< GPD_MFPL PD4 setting for GPIO     \hideinitializer */
    556. 

  556. #define SYS_GPD_MFPL_PD4MFP_SC5_CD           (0x1UL<<SYS_GPD_MFPL_PD4MFP_Pos)           /*!< GPD_MFPL PD4 setting for SC5_CD     \hideinitializer */
    557. 

  557. #define SYS_GPD_MFPL_PD4MFP_UART3_RXD        (0x2UL<<SYS_GPD_MFPL_PD4MFP_Pos)           /*!< GPD_MFPL PD4 setting for UART3_RXD    \hideinitializer */
    558. 

  558. #define SYS_GPD_MFPL_PD4MFP_ACMP1_O          (0x3UL<<SYS_GPD_MFPL_PD4MFP_Pos)           /*!< GPD_MFPL PD4 setting for ACMP1_O    \hideinitializer */
    559. 

  559. #define SYS_GPD_MFPL_PD4MFP_CAP_SCLK         (0x5UL<<SYS_GPD_MFPL_PD4MFP_Pos)           /*!< GPD_MFPL PD4 setting for CAP_SCLK     \hideinitializer */
    560. 

  560. #define SYS_GPD_MFPL_PD4MFP_JTAG_TDI         (0x6UL<<SYS_GPD_MFPL_PD4MFP_Pos)           /*!< GPD_MFPL PD4 setting for JTAG_TDI     \hideinitializer */
    561. 

  561. #define SYS_GPD_MFPL_PD4MFP_EBI_A8           (0x7UL<<SYS_GPD_MFPL_PD4MFP_Pos)           /*!< GPD_MFPL PD4 setting for EBI_A8     \hideinitializer */
    562. 

  562. 

  563. //GPD_MFPL_PD5MFP
    564. 

  564. #define SYS_GPD_MFPL_PD5MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD5MFP_Pos)           /*!< GPD_MFPL PD5 setting for GPIO     \hideinitializer */
    565. 

  565. #define SYS_GPD_MFPL_PD5MFP_SC5_RST          (0x1UL<<SYS_GPD_MFPL_PD5MFP_Pos)           /*!< GPD_MFPL PD5 setting for SC5_RST      \hideinitializer */
    566. 

  566. #define SYS_GPD_MFPL_PD5MFP_UART3_TXD        (0x2UL<<SYS_GPD_MFPL_PD5MFP_Pos)           /*!< GPD_MFPL PD5 setting for UART3_TXD    \hideinitializer */
    567. 

  567. #define SYS_GPD_MFPL_PD5MFP_CAP_VSYNC        (0x5UL<<SYS_GPD_MFPL_PD5MFP_Pos)           /*!< GPD_MFPL PD5 setting for CAP_VSYNC    \hideinitializer */
    568. 

  568. #define SYS_GPD_MFPL_PD5MFP_JTAG_nTRST       (0x6UL<<SYS_GPD_MFPL_PD5MFP_Pos)           /*!< GPD_MFPL PD5 setting for JTAG_nTRST     \hideinitializer */
    569. 

  569. #define SYS_GPD_MFPL_PD5MFP_EBI_A9           (0x7UL<<SYS_GPD_MFPL_PD5MFP_Pos)           /*!< GPD_MFPL PD5 setting for EBI_A9     \hideinitializer */
    570. 

  570. 

  571. //GPD_MFPL_PD6MFP
    572. 

  572. #define SYS_GPD_MFPL_PD6MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD6MFP_Pos)           /*!< GPD_MFPL PD6 setting for GPIO     \hideinitializer */
    573. 

  573. #define SYS_GPD_MFPL_PD6MFP_SC5_PWR          (0x1UL<<SYS_GPD_MFPL_PD6MFP_Pos)           /*!< GPD_MFPL PD6 setting for SC5_PWR    \hideinitializer */
    574. 

  574. #define SYS_GPD_MFPL_PD6MFP_UART3_RTS        (0x2UL<<SYS_GPD_MFPL_PD6MFP_Pos)           /*!< GPD_MFPL PD6 setting for UART3_RTS    \hideinitializer */
    575. 

  575. #define SYS_GPD_MFPL_PD6MFP_SD0_CMD          (0x4UL<<SYS_GPD_MFPL_PD6MFP_Pos)           /*!< GPD_MFPL PD6 setting for SD0_CMD      \hideinitializer */
    576. 

  576. #define SYS_GPD_MFPL_PD6MFP_CAP_HSYNC        (0x5UL<<SYS_GPD_MFPL_PD6MFP_Pos)           /*!< GPD_MFPL PD6 setting for CAP_HSYNC      \hideinitializer */
    577. 

  577. #define SYS_GPD_MFPL_PD6MFP_EBI_A10          (0x7UL<<SYS_GPD_MFPL_PD6MFP_Pos)           /*!< GPD_MFPL PD6 setting for EBI_A10    \hideinitializer */
    578. 

  578. 

  579. //GPD_MFPL_PD7MFP
    580. 

  580. #define SYS_GPD_MFPL_PD7MFP_GPIO             (0x0UL<<SYS_GPD_MFPL_PD7MFP_Pos)           /*!< GPD_MFPL PD7 setting for GPIO     \hideinitializer */
    581. 

  581. #define SYS_GPD_MFPL_PD7MFP_SC5_DAT          (0x1UL<<SYS_GPD_MFPL_PD7MFP_Pos)           /*!< GPD_MFPL PD7 setting for SC5_DAT    \hideinitializer */
    582. 

  582. #define SYS_GPD_MFPL_PD7MFP_UART3_CTS        (0x2UL<<SYS_GPD_MFPL_PD7MFP_Pos)           /*!< GPD_MFPL PD7 setting for UART3_CTS      \hideinitializer */
    583. 

  583. #define SYS_GPD_MFPL_PD7MFP_SD0_CLK          (0x4UL<<SYS_GPD_MFPL_PD7MFP_Pos)           /*!< GPD_MFPL PD7 setting for SD0_CLK    \hideinitializer */
    584. 

  584. #define SYS_GPD_MFPL_PD7MFP_CAP_PIXCLK       (0x5UL<<SYS_GPD_MFPL_PD7MFP_Pos)           /*!< GPD_MFPL PD7 setting for CAP_PIXCLK     \hideinitializer */
    585. 

  585. #define SYS_GPD_MFPL_PD7MFP_EBI_A11          (0x7UL<<SYS_GPD_MFPL_PD7MFP_Pos)           /*!< GPD_MFPL PD7 setting for EBI_A11    \hideinitializer */
    586. 

  586. 

  587. //GPD_MFPL_PD8MFP
    588. 

  588. #define SYS_GPD_MFPH_PD8MFP_GPIO             (0x0UL<<SYS_GPD_MFPH_PD8MFP_Pos)           /*!< GPD_MFPH PD8 setting for GPIO     \hideinitializer */
    589. 

  589. #define SYS_GPD_MFPH_PD8MFP_SPI3_MISO1       (0x1UL<<SYS_GPD_MFPH_PD8MFP_Pos)           /*!< GPD_MFPH PD8 setting for SPI3_MISO1     \hideinitializer */
    590. 

  590. #define SYS_GPD_MFPH_PD8MFP_I2C0_SCL         (0x2UL<<SYS_GPD_MFPH_PD8MFP_Pos)           /*!< GPD_MFPH PD8 setting for I2C0_SCL     \hideinitializer */
    591. 

  591. 

  592. //GPD_MFPH_PD9MFP
    593. 

  593. #define SYS_GPD_MFPH_PD9MFP_GPIO             (0x0UL<<SYS_GPD_MFPH_PD9MFP_Pos)           /*!< GPD_MFPH PD9 setting for GPIO     \hideinitializer */
    594. 

  594. #define SYS_GPD_MFPH_PD9MFP_SPI3_MOSI1       (0x1UL<<SYS_GPD_MFPH_PD9MFP_Pos)           /*!< GPD_MFPH PD9 setting for SPI3_MOSI1     \hideinitializer */
    595. 

  595. #define SYS_GPD_MFPH_PD9MFP_I2C0_SDA         (0x2UL<<SYS_GPD_MFPH_PD9MFP_Pos)           /*!< GPD_MFPH PD9 setting for I2C0_SDA     \hideinitializer */
    596. 

  596. 

  597. //GPD_MFPH_PD10MFP
    598. 

  598. #define SYS_GPD_MFPH_PD10MFP_GPIO            (0x0UL<<SYS_GPD_MFPH_PD10MFP_Pos)           /*!< GPD_MFPH PD10 setting for GPIO   \hideinitializer */
    599. 

  599. #define SYS_GPD_MFPH_PD10MFP_SC3_DAT         (0x1UL<<SYS_GPD_MFPH_PD10MFP_Pos)           /*!< GPD_MFPH PD10 setting for SC3_DAT    \hideinitializer */
    600. 

  600. #define SYS_GPD_MFPH_PD10MFP_I2C4_SCL        (0x2UL<<SYS_GPD_MFPH_PD10MFP_Pos)           /*!< GPD_MFPH PD10 setting for I2C4_SCL     \hideinitializer */
    601. 

  601. 

  602. //GPD_MFPH_PD11MFP
    603. 

  603. #define SYS_GPD_MFPH_PD11MFP_GPIO            (0x0UL<<SYS_GPD_MFPH_PD11MFP_Pos)           /*!< GPD_MFPH PD11 setting for GPIO   \hideinitializer */
    604. 

  604. #define SYS_GPD_MFPH_PD11MFP_SC3_RST         (0x1UL<<SYS_GPD_MFPH_PD11MFP_Pos)           /*!< GPD_MFPH PD11 setting for SC3_RST   \hideinitializer */
    605. 

  605. #define SYS_GPD_MFPH_PD11MFP_TM3_CNT_OUT     (0x3UL<<SYS_GPD_MFPH_PD11MFP_Pos)           /*!< GPD_MFPH PD11 setting for TM3_CNT_OUT   \hideinitializer */
    606. 

  606. 

  607. //GPD_MFPH_PD12MFP
    608. 

  608. #define SYS_GPD_MFPH_PD12MFP_GPIO            (0x0UL<<SYS_GPD_MFPH_PD12MFP_Pos)           /*!< GPD_MFPH PD12 setting for GPIO   \hideinitializer */
    609. 

  609. #define SYS_GPD_MFPH_PD12MFP_SC3_CLK         (0x1UL<<SYS_GPD_MFPH_PD12MFP_Pos)           /*!< GPD_MFPH PD12 setting for SC3_CLK   \hideinitializer */
    610. 

  610. #define SYS_GPD_MFPH_PD12MFP_I2C4_SDA        (0x2UL<<SYS_GPD_MFPH_PD12MFP_Pos)           /*!< GPD_MFPH PD12 setting for I2C4_SDA   \hideinitializer */
    611. 

  611. 

  612. //GPD_MFPH_PD13MFP
    613. 

  613. #define SYS_GPD_MFPH_PD13MFP_GPIO            (0x0UL<<SYS_GPD_MFPH_PD13MFP_Pos)           /*!< GPD_MFPH PD13 setting for GPIO   \hideinitializer */
    614. 

  614. #define SYS_GPD_MFPH_PD13MFP_SPI1_SS0        (0x1UL<<SYS_GPD_MFPH_PD13MFP_Pos)           /*!< GPD_MFPH PD13 setting for SPI1_SS0   \hideinitializer */
    615. 

  615. #define SYS_GPD_MFPH_PD13MFP_UART5_CTS       (0x2UL<<SYS_GPD_MFPH_PD13MFP_Pos)           /*!< GPD_MFPH PD13 setting for UART5_CTS   \hideinitializer */
    616. 

  616. #define SYS_GPD_MFPH_PD13MFP_ECAP0_IC2       (0x3UL<<SYS_GPD_MFPH_PD13MFP_Pos)           /*!< GPD_MFPH PD13 setting for ECAP0_IC2   \hideinitializer */
    617. 

  617. 

  618. //GPD_MFPH_PD14MFP
    619. 

  619. #define SYS_GPD_MFPH_PD14MFP_GPIO            (0x0UL<<SYS_GPD_MFPH_PD14MFP_Pos)           /*!< GPD_MFPH PD14 setting for GPIO   \hideinitializer */
    620. 

  620. #define SYS_GPD_MFPH_PD14MFP_SPI1_CLK        (0x1UL<<SYS_GPD_MFPH_PD14MFP_Pos)           /*!< GPD_MFPH PD14 setting for SPI1_CLK   \hideinitializer */
    621. 

  621. #define SYS_GPD_MFPH_PD14MFP_UART5_RTS       (0x2UL<<SYS_GPD_MFPH_PD14MFP_Pos)           /*!< GPD_MFPH PD14 setting for UART5_RTS   \hideinitializer */
    622. 

  622. #define SYS_GPD_MFPH_PD14MFP_ECAP0_IC1       (0x3UL<<SYS_GPD_MFPH_PD14MFP_Pos)           /*!< GPD_MFPH PD14 setting for ECAP0_IC1   \hideinitializer */
    623. 

  623. 

  624. //GPD_MFPH_PD15MFP
    625. 

  625. #define SYS_GPD_MFPH_PD15MFP_GPIO            (0x0UL<<SYS_GPD_MFPH_PD15MFP_Pos)           /*!< GPD_MFPH PD15 setting for GPIO  \hideinitializer */
    626. 

  626. #define SYS_GPD_MFPH_PD15MFP_SPI1_MISO0      (0x1UL<<SYS_GPD_MFPH_PD15MFP_Pos)           /*!< GPD_MFPH PD15 setting for SPI1_MISO0    \hideinitializer */
    627. 

  627. #define SYS_GPD_MFPH_PD15MFP_UART5_TXD       (0x2UL<<SYS_GPD_MFPH_PD15MFP_Pos)           /*!< GPD_MFPH PD15 setting for UART5_TXD  \hideinitializer */
    628. 

  628. #define SYS_GPD_MFPH_PD15MFP_ECAP0_IC0       (0x3UL<<SYS_GPD_MFPH_PD15MFP_Pos)           /*!< GPD_MFPH PD15 setting for ECAP0_IC0  \hideinitializer */
    629. 

  629. 

  630. //GPE_MFPL_PE0MFP
    631. 

  631. #define SYS_GPE_MFPL_PE0MFP_GPIO             (0x0UL<<SYS_GPE_MFPL_PE0MFP_Pos)           /*!< GPE_MFPL PE0 setting for GPIO     \hideinitializer */
    632. 

  632. #define SYS_GPE_MFPL_PE0MFP_ADC0_0           (0x1UL<<SYS_GPE_MFPL_PE0MFP_Pos)           /*!< GPE_MFPL PE0 setting for ADC0_0     \hideinitializer */
    633. 

  633. #define SYS_GPE_MFPL_PE0MFP_INT4             (0x8UL<<SYS_GPE_MFPL_PE0MFP_Pos)           /*!< GPE_MFPL PE0 setting for INT4     \hideinitializer */
    634. 

  634. 

  635. //GPE_MFPL_PE1MFP
    636. 

  636. #define SYS_GPE_MFPL_PE1MFP_GPIO             (0x0UL<<SYS_GPE_MFPL_PE1MFP_Pos)           /*!< GPE_MFPL PE1 setting for GPIO     \hideinitializer */
    637. 

  637. #define SYS_GPE_MFPL_PE1MFP_ADC0_1           (0x1UL<<SYS_GPE_MFPL_PE1MFP_Pos)           /*!< GPE_MFPL PE1 setting for ADC0_1     \hideinitializer */
    638. 

  638. #define SYS_GPE_MFPL_PE1MFP_TM2_CNT_OUT      (0x3UL<<SYS_GPE_MFPL_PE1MFP_Pos)           /*!< GPE_MFPL PE1 setting for TM2_CNT_OUT      \hideinitializer */
    639. 

  639. 

  640. //GPE_MFPL_PE2MFP
    641. 

  641. #define SYS_GPE_MFPL_PE2MFP_GPIO             (0x0UL<<SYS_GPE_MFPL_PE2MFP_Pos)           /*!< GPE_MFPL PE2 setting for GPIO     \hideinitializer */
    642. 

  642. #define SYS_GPE_MFPL_PE2MFP_ADC0_2           (0x1UL<<SYS_GPE_MFPL_PE2MFP_Pos)           /*!< GPE_MFPL PE2 setting for ADC0_2     \hideinitializer */
    643. 

  643. #define SYS_GPE_MFPL_PE2MFP_ACMP0_O          (0x2UL<<SYS_GPE_MFPL_PE2MFP_Pos)           /*!< GPE_MFPL PE2 setting for ACMP0_O      \hideinitializer */
    644. 

  644. #define SYS_GPE_MFPL_PE2MFP_SPI0_MISO0       (0x3UL<<SYS_GPE_MFPL_PE2MFP_Pos)           /*!< GPE_MFPL PE2 setting for SPI0_MISO0     \hideinitializer */
    645. 

  645. 

  646. //GPE_MFPL_PE3MFP
    647. 

  647. #define SYS_GPE_MFPL_PE3MFP_GPIO             (0x0UL<<SYS_GPE_MFPL_PE3MFP_Pos)           /*!< GPE_MFPL PE3 setting for GPIO     \hideinitializer */
    648. 

  648. #define SYS_GPE_MFPL_PE3MFP_ADC0_3           (0x1UL<<SYS_GPE_MFPL_PE3MFP_Pos)           /*!< GPE_MFPL PE3 setting for ADC0_3     \hideinitializer */
    649. 

  649. #define SYS_GPE_MFPL_PE3MFP_ACMP0_P3         (0x2UL<<SYS_GPE_MFPL_PE3MFP_Pos)           /*!< GPE_MFPL PE3 setting for ACMP0_P3     \hideinitializer */
    650. 

  650. #define SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0       (0x3UL<<SYS_GPE_MFPL_PE3MFP_Pos)           /*!< GPE_MFPL PE3 setting for SPI0_MOSI0     \hideinitializer */
    651. 

  651. 

  652. //GPE_MFPL_PE4MFP
    653. 

  653. #define SYS_GPE_MFPL_PE4MFP_GPIO            (0x0UL<<SYS_GPE_MFPL_PE4MFP_Pos)           /*!< GPE_MFPL PE4 setting for GPIO     \hideinitializer */
    654. 

  654. #define SYS_GPE_MFPL_PE4MFP_ADC0_4          (0x1UL<<SYS_GPE_MFPL_PE4MFP_Pos)           /*!< GPE_MFPL PE4 setting for ADC0_4     \hideinitializer */
    655. 

  655. #define SYS_GPE_MFPL_PE4MFP_ACMP0_P2        (0x2UL<<SYS_GPE_MFPL_PE4MFP_Pos)           /*!< GPE_MFPL PE4 setting for ACMP0_P2     \hideinitializer */
    656. 

  656. #define SYS_GPE_MFPL_PE4MFP_SPI0_SS0        (0x3UL<<SYS_GPE_MFPL_PE4MFP_Pos)           /*!< GPE_MFPL PE4 setting for SPI0_SS0     \hideinitializer */
    657. 

  657. 

  658. //GPE_MFPL_PE5MFP
    659. 

  659. #define SYS_GPE_MFPL_PE5MFP_GPIO            (0x0UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for GPIO     \hideinitializer */
    660. 

  660. #define SYS_GPE_MFPL_PE5MFP_ADC0_5          (0x1UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for ADC0_5     \hideinitializer */
    661. 

  661. #define SYS_GPE_MFPL_PE5MFP_ACMP0_P1        (0x2UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for ACMP0_P1     \hideinitializer */
    662. 

  662. #define SYS_GPE_MFPL_PE5MFP_SPI0_CLK        (0x3UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for SPI0_CLK     \hideinitializer */
    663. 

  663. #define SYS_GPE_MFPL_PE5MFP_SD0_CDn         (0x4UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for SD0_CDn      \hideinitializer */
    664. 

  664. 

  665. //GPE_MFPL_PE6MFP
    666. 

  666. #define SYS_GPE_MFPL_PE6MFP_GPIO            (0x0UL<<SYS_GPE_MFPL_PE6MFP_Pos)           /*!< GPE_MFPL PE6 setting for GPIO     \hideinitializer */
    667. 

  667. #define SYS_GPE_MFPL_PE6MFP_ADC0_6          (0x1UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for ADC0_6    \hideinitializer */
    668. 

  668. #define SYS_GPE_MFPL_PE6MFP_ACMP0_P0        (0x2UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for ACMP0_P0    \hideinitializer */
    669. 

  669. #define SYS_GPE_MFPL_PE6MFP_SPI0_MISO0      (0x3UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for SPI0_MISO0    \hideinitializer */
    670. 

  670. #define SYS_GPE_MFPL_PE6MFP_SD0_CMD         (0x4UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for SD0_CMD     \hideinitializer */
    671. 

  671. #define SYS_GPE_MFPL_PE6MFP_EBI_nWR         (0x7UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for EBI_nWR     \hideinitializer */
    672. 

  672. 

  673. //GPE_MFPL_PE7MFP
    674. 

  674. #define SYS_GPE_MFPL_PE7MFP_GPIO            (0x0UL<<SYS_GPE_MFPL_PE7MFP_Pos)            /*!< GPE_MFPL PE7 setting for GPIO    \hideinitializer */
    675. 

  675. #define SYS_GPE_MFPL_PE7MFP_ADC0_7          (0x1UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for ADC0_7     \hideinitializer */
    676. 

  676. #define SYS_GPE_MFPL_PE7MFP_ACMP0_N         (0x2UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for ACMP0_N      \hideinitializer */
    677. 

  677. #define SYS_GPE_MFPL_PE7MFP_SPI0_MOSI0      (0x3UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for SPI0_MOSI0     \hideinitializer */
    678. 

  678. #define SYS_GPE_MFPL_PE7MFP_SD0_CLK         (0x4UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for SD0_CLK      \hideinitializer */
    679. 

  679. #define SYS_GPE_MFPL_PE7MFP_EBI_nRD         (0x7UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for _EBI_nRD     \hideinitializer */
    680. 

  680. 

  681. //GPE_MFPL_PE8MFP
    682. 

  682. #define SYS_GPE_MFPH_PE8MFP_GPIO            (0x0UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for GPIO     \hideinitializer */
    683. 

  683. #define SYS_GPE_MFPH_PE8MFP_ADC0_8          (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for ADC0_8     \hideinitializer */
    684. 

  684. #define SYS_GPE_MFPH_PE8MFP_ADC1_0          (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for ADC1_0     \hideinitializer */
    685. 

  685. #define SYS_GPE_MFPH_PE8MFP_ACMP1_N         (0x2UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for ACMP1_N    \hideinitializer */
    686. 

  686. #define SYS_GPE_MFPH_PE8MFP_TM1_CNT_OUT     (0x3UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for TM1_CNT_OUT    \hideinitializer */
    687. 

  687. #define SYS_GPE_MFPH_PE8MFP_SD0_DAT3        (0x4UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for SD0_DAT3     \hideinitializer */
    688. 

  688. #define SYS_GPE_MFPH_PE8MFP_EBI_ALE         (0x7UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for EBI_ALE    \hideinitializer */
    689. 

  689. 

  690. //GPE_MFPH_PE9MFP
    691. 

  691. #define SYS_GPE_MFPH_PE9MFP_GPIO            (0x0UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for GPIO     \hideinitializer */
    692. 

  692. #define SYS_GPE_MFPH_PE9MFP_ADC0_9          (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for ADC0_9     \hideinitializer */
    693. 

  693. #define SYS_GPE_MFPH_PE9MFP_ADC1_1          (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for ADC1_1     \hideinitializer */
    694. 

  694. #define SYS_GPE_MFPH_PE9MFP_ACMP1_P0        (0x2UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for ACMP1_P0     \hideinitializer */
    695. 

  695. #define SYS_GPE_MFPH_PE9MFP_SD0_DAT2        (0x4UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for SD0_DAT2     \hideinitializer */
    696. 

  696. #define SYS_GPE_MFPH_PE9MFP_EBI_nWRH        (0x7UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for EBI_nWRH     \hideinitializer */
    697. 

  697. 

  698. //GPE_MFPH_PE10MFP
    699. 

  699. #define SYS_GPE_MFPH_PE10MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for GPIO   \hideinitializer */
    700. 

  700. #define SYS_GPE_MFPH_PE10MFP_ADC0_10        (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for ADC0_10     \hideinitializer */
    701. 

  701. #define SYS_GPE_MFPH_PE10MFP_ADC1_2         (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for ADC1_2   \hideinitializer */
    702. 

  702. #define SYS_GPE_MFPH_PE10MFP_ACMP1_P1       (0x2UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for ACMP1_P1   \hideinitializer */
    703. 

  703. #define SYS_GPE_MFPH_PE10MFP_SPI0_MISO1     (0x3UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for SPI0_MISO1   \hideinitializer */
    704. 

  704. #define SYS_GPE_MFPH_PE10MFP_SD0_DAT1       (0x4UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for SD0_DAT1     \hideinitializer */
    705. 

  705. #define SYS_GPE_MFPH_PE10MFP_EBI_nWRL       (0x7UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for EBI_nWRL   \hideinitializer */
    706. 

  706. 

  707. //GPE_MFPH_PE11MFP
    708. 

  708. #define SYS_GPE_MFPH_PE11MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for GPIO   \hideinitializer */
    709. 

  709. #define SYS_GPE_MFPH_PE11MFP_ADC0_11        (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ADC0_11     \hideinitializer */
    710. 

  710. #define SYS_GPE_MFPH_PE11MFP_ADC1_3         (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ADC1_3   \hideinitializer */
    711. 

  711. #define SYS_GPE_MFPH_PE11MFP_ACMP1_P2       (0x2UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ACMP1_P2   \hideinitializer */
    712. 

  712. #define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI1     (0x3UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for SPI0_MOSI1   \hideinitializer */
    713. 

  713. #define SYS_GPE_MFPH_PE11MFP_SD0_DAT0       (0x4UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for SD0_DAT0   \hideinitializer */
    714. 

  714. #define SYS_GPE_MFPH_PE11MFP_ACMP2_P3       (0x5UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ACMP2_P3   \hideinitializer */
    715. 

  715. #define SYS_GPE_MFPH_PE11MFP_EBI_nCS0       (0x7UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for EBI_nCS0   \hideinitializer */
    716. 

  716. 

  717. //GPE_MFPH_PE12MFP
    718. 

  718. #define SYS_GPE_MFPH_PE12MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE12MFP_Pos)           /*!< GPE_MFPH PE12 setting for GPIO   \hideinitializer */
    719. 

  719. #define SYS_GPE_MFPH_PE12MFP_ADC1_4         (0x1UL<<SYS_GPE_MFPH_PE12MFP_Pos)           /*!< GPE_MFPH PE12 setting for ADC1_4   \hideinitializer */
    720. 

  720. #define SYS_GPE_MFPH_PE12MFP_ACMP1_P3       (0x2UL<<SYS_GPE_MFPH_PE12MFP_Pos)           /*!< GPE_MFPH PE12 setting for ACMP1_P3   \hideinitializer */
    721. 

  721. #define SYS_GPE_MFPH_PE12MFP_ACMP2_P2       (0x3UL<<SYS_GPE_MFPH_PE12MFP_Pos)           /*!< GPE_MFPH PE12 setting for ACMP2_P2   \hideinitializer */
    722. 

  722. #define SYS_GPE_MFPH_PE12MFP_EBI_nCS1       (0x7UL<<SYS_GPE_MFPH_PE12MFP_Pos)           /*!< GPE_MFPH PE12 setting for EBI_nCS1   \hideinitializer */
    723. 

  723. //GPE_MFPH_PE13MFP
    724. 

  724. #define SYS_GPE_MFPH_PE13MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE13MFP_Pos)           /*!< GPE_MFPH PE13 setting for GPIO   \hideinitializer */
    725. 

  725. #define SYS_GPE_MFPH_PE13MFP_ADC1_5         (0x1UL<<SYS_GPE_MFPH_PE13MFP_Pos)           /*!< GPE_MFPH PE13 setting for ADC1_5   \hideinitializer */
    726. 

  726. #define SYS_GPE_MFPH_PE13MFP_ACMP2_P1       (0x3UL<<SYS_GPE_MFPH_PE13MFP_Pos)           /*!< GPE_MFPH PE13 setting for ACMP2_P1   \hideinitializer */
    727. 

  727. #define SYS_GPE_MFPH_PE13MFP_EBI_nCS2       (0x7UL<<SYS_GPE_MFPH_PE13MFP_Pos)           /*!< GPE_MFPH PE13 setting for EBI_nCS2   \hideinitializer */
    728. 

  728. 

  729. //GPE_MFPH_PE14MFP
    730. 

  730. #define SYS_GPE_MFPH_PE14MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE14MFP_Pos)           /*!< GPE_MFPH PE14 setting for GPIO   \hideinitializer */
    731. 

  731. #define SYS_GPE_MFPH_PE14MFP_ADC1_6         (0x1UL<<SYS_GPE_MFPH_PE14MFP_Pos)           /*!< GPE_MFPH PE14 setting for ADC1_6   \hideinitializer */
    732. 

  732. #define SYS_GPE_MFPH_PE14MFP_ACMP2_P0       (0x3UL<<SYS_GPE_MFPH_PE14MFP_Pos)           /*!< GPE_MFPH PE14 setting for ACMP2_P0   \hideinitializer */
    733. 

  733. #define SYS_GPE_MFPH_PE14MFP_EBI_nCS3       (0x7UL<<SYS_GPE_MFPH_PE14MFP_Pos)           /*!< GPE_MFPH PE14 setting for EBI_nCS3   \hideinitializer */
    734. 

  734. 

  735. //GPE_MFPH_PE15MFP
    736. 

  736. #define SYS_GPE_MFPH_PE15MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE15MFP_Pos)           /*!< GPE_MFPH PE15 setting for GPIO   \hideinitializer */
    737. 

  737. #define SYS_GPE_MFPH_PE15MFP_ADC1_7         (0x1UL<<SYS_GPE_MFPH_PE15MFP_Pos)            /*!< GPE_MFPH PE15 setting for ADC1_7    \hideinitializer */
    738. 

  738. #define SYS_GPE_MFPH_PE15MFP_ACMP2_N        (0x3UL<<SYS_GPE_MFPH_PE15MFP_Pos)            /*!< GPE_MFPH PE15 setting for ACMP2_N  \hideinitializer */
    739. 

  739. 

  740. //GPF_MFPL_PF0MFP
    741. 

  741. #define SYS_GPF_MFPL_PF0MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF0MFP_Pos)            /*!< GPF_MFPL PF0 setting for GPIO    \hideinitializer */
    742. 

  742. #define SYS_GPF_MFPL_PF0MFP_SPI1_MOSI0      (0x1UL<<SYS_GPF_MFPL_PF0MFP_Pos)           /*!< GPF_MFPL PF0 setting for SPI1_MOSI0     \hideinitializer */
    743. 

  743. #define SYS_GPF_MFPL_PF0MFP_UART5_RXD       (0x2UL<<SYS_GPF_MFPL_PF0MFP_Pos)           /*!< GPF_MFPL PF0 setting for UART5_RXD      \hideinitializer */
    744. 

  744. #define SYS_GPF_MFPL_PF0MFP_INT5            (0x8UL<<SYS_GPF_MFPL_PF0MFP_Pos)           /*!< GPF_MFPL PF0 setting for INT5     \hideinitializer */
    745. 

  745. 

  746. //GPF_MFPL_PF1MFP
    747. 

  747. #define SYS_GPF_MFPL_PF1MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF1MFP_Pos)           /*!< GPF_MFPL PF1 setting for GPIO     \hideinitializer */
    748. 

  748. #define SYS_GPF_MFPL_PF1MFP_SPI2_MOSI1      (0x1UL<<SYS_GPF_MFPL_PF1MFP_Pos)           /*!< GPF_MFPL PF1 setting for SPI2_MOSI1     \hideinitializer */
    749. 

  749. 

  750. //GPF_MFPL_PF2MFP
    751. 

  751. #define SYS_GPF_MFPL_PF2MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF2MFP_Pos)           /*!< GPF_MFPL PF2 setting for GPIO     \hideinitializer */
    752. 

  752. #define SYS_GPF_MFPL_PF2MFP_SPI3_SS0        (0x1UL<<SYS_GPF_MFPL_PF2MFP_Pos)           /*!< GPF_MFPL PF2 setting for SPI3_SS0     \hideinitializer */
    753. 

  753. #define SYS_GPF_MFPL_PF2MFP_SD0_DAT3        (0x4UL<<SYS_GPF_MFPL_PF2MFP_Pos)           /*!< GPF_MFPL PF2 setting for SD0_DAT3     \hideinitializer */
    754. 

  754. #define SYS_GPF_MFPL_PF2MFP_EMAC_MII_RXD3   (0x6UL<<SYS_GPF_MFPL_PF2MFP_Pos)           /*!< GPF_MFPL PF2 setting for EMAC_MII_RXD3    \hideinitializer */
    755. 

  755. 

  756. //GPF_MFPL_PF3MFP
    757. 

  757. #define SYS_GPF_MFPL_PF3MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF3MFP_Pos)           /*!< GPF_MFPL PF3 setting for GPIO     \hideinitializer */
    758. 

  758. #define SYS_GPF_MFPL_PF3MFP_SPI3_CLK        (0x1UL<<SYS_GPF_MFPL_PF3MFP_Pos)           /*!< GPF_MFPL PF3 setting for SPI3_CLK     \hideinitializer */
    759. 

  759. #define SYS_GPF_MFPL_PF3MFP_SD0_DAT2        (0x4UL<<SYS_GPF_MFPL_PF3MFP_Pos)           /*!< GPF_MFPL PF3 setting for SD0_DAT2     \hideinitializer */
    760. 

  760. #define SYS_GPF_MFPL_PF3MFP_EMAC_MII_RXD2   (0x6UL<<SYS_GPF_MFPL_PF3MFP_Pos)          /*!< GPF_MFPL PF3 setting for EMAC_MII_RXD2     \hideinitializer */
    761. 

  761. 

  762. //GPF_MFPL_PF4MFP
    763. 

  763. #define SYS_GPF_MFPL_PF4MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF4MFP_Pos)           /*!< GPF_MFPL PF4 setting for GPIO     \hideinitializer */
    764. 

  764. #define SYS_GPF_MFPL_PF4MFP_SPI3_MISO0      (0x1UL<<SYS_GPF_MFPL_PF4MFP_Pos)           /*!< GPF_MFPL PF4 setting for SPI3_MISO0     \hideinitializer */
    765. 

  765. #define SYS_GPF_MFPL_PF4MFP_SD0_DAT1        (0x4UL<<SYS_GPF_MFPL_PF4MFP_Pos)           /*!< GPF_MFPL PF4 setting for SD0_DAT1     \hideinitializer */
    766. 

  766. #define SYS_GPF_MFPL_PF4MFP_EMAC_MII_COL0   (0x6UL<<SYS_GPF_MFPL_PF4MFP_Pos)           /*!< GPF_MFPL PF4 setting for EMAC_MII_COL0    \hideinitializer */
    767. 

  767. 

  768. //GPF_MFPL_PF5MFP
    769. 

  769. #define SYS_GPF_MFPL_PF5MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF5MFP_Pos)           /*!< GPF_MFPL PF5 setting for GPIO     \hideinitializer */
    770. 

  770. #define SYS_GPF_MFPL_PF5MFP_SPI3_MOSI0      (0x1UL<<SYS_GPF_MFPL_PF5MFP_Pos)           /*!< GPF_MFPL PF5 setting for SPI3_MOSI0     \hideinitializer */
    771. 

  771. #define SYS_GPF_MFPL_PF5MFP_SD0_DAT0        (0x4UL<<SYS_GPF_MFPL_PF5MFP_Pos)           /*!< GPF_MFPL PF5 setting for SD0_DAT0     \hideinitializer */
    772. 

  772. #define SYS_GPF_MFPL_PF5MFP_EMAC_MII_CRS    (0x6UL<<SYS_GPF_MFPL_PF5MFP_Pos)           /*!< GPF_MFPL PF5 setting for EMAC_MII_CRS     \hideinitializer */
    773. 

  773. 

  774. //GPF_MFPL_PF6MFP
    775. 

  775. #define SYS_GPF_MFPL_PF6MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF6MFP_Pos)           /*!< GPF_MFPL PF6 setting for GPIO     \hideinitializer */
    776. 

  776. #define SYS_GPF_MFPL_PF6MFP_UART2_RXD       (0x1UL<<SYS_GPF_MFPL_PF6MFP_Pos)           /*!< GPF_MFPL PF6 setting for UART2_RXD    \hideinitializer */
    777. 

  777. #define SYS_GPF_MFPL_PF6MFP_SD0_CDn         (0x4UL<<SYS_GPF_MFPL_PF6MFP_Pos)           /*!< GPF_MFPL PF6 setting for SD0_CDn    \hideinitializer */
    778. 

  778. #define SYS_GPF_MFPL_PF6MFP_EMAC_MII_TXCLK  (0x6UL<<SYS_GPF_MFPL_PF6MFP_Pos)           /*!< GPF_MFPL PF6 setting for EMAC_MII_TXCLK     \hideinitializer */
    779. 

  779. 

  780. //GPF_MFPL_PF7MFP
    781. 

  781. #define SYS_GPF_MFPL_PF7MFP_GPIO          (0x0UL<<SYS_GPF_MFPL_PF7MFP_Pos)           /*!< GPF_MFPL PF7 setting for GPIO     \hideinitializer */
    782. 

  782. #define SYS_GPF_MFPL_PF7MFP_UART2_TXD     (0x1UL<<SYS_GPF_MFPL_PF7MFP_Pos)           /*!< GPF_MFPL PF7 setting for UART2_TXD    \hideinitializer */
    783. 

  783. #define SYS_GPF_MFPL_PF7MFP_SD0_CMD       (0x4UL<<SYS_GPF_MFPL_PF7MFP_Pos)           /*!< GPF_MFPL PF7 setting for SD0_CMD    \hideinitializer */
    784. 

  784. #define SYS_GPF_MFPL_PF7MFP_EMAC_MII_TXD3 (0x6UL<<SYS_GPF_MFPL_PF7MFP_Pos)           /*!< GPF_MFPL PF7 setting for EMAC_MII_TXD3    \hideinitializer */
    785. 

  785. 

  786. //GPF_MFPL_PF8MFP
    787. 

  787. #define SYS_GPF_MFPH_PF8MFP_GPIO          (0x0UL<<SYS_GPF_MFPH_PF8MFP_Pos)           /*!< GPF_MFPH PF8 setting for GPIO     \hideinitializer */
    788. 

  788. #define SYS_GPF_MFPH_PF8MFP_UART2_RTS     (0x1UL<<SYS_GPF_MFPH_PF8MFP_Pos)           /*!< GPF_MFPH PF8 setting for UART2_RTS    \hideinitializer */
    789. 

  789. #define SYS_GPF_MFPH_PF8MFP_SD0_CLK       (0x4UL<<SYS_GPF_MFPH_PF8MFP_Pos)           /*!< GPF_MFPH PF8 setting for SD0_CLK    \hideinitializer */
    790. 

  790. #define SYS_GPF_MFPH_PF8MFP_EMAC_MII_TXD2 (0x6UL<<SYS_GPF_MFPH_PF8MFP_Pos)           /*!< GPF_MFPH PF8 setting for EMAC_MII_TXD2    \hideinitializer */
    791. 

  791. 

  792. //GPF_MFPH_PF9MFP
    793. 

  793. #define SYS_GPF_MFPH_PF9MFP_GPIO          (0x0UL<<SYS_GPF_MFPH_PF9MFP_Pos)           /*!< GPF_MFPH PF9 setting for GPIO     \hideinitializer */
    794. 

  794. #define SYS_GPF_MFPH_PF9MFP_OPA0_IN_P     (0x1UL<<SYS_GPF_MFPH_PF9MFP_Pos)           /*!< GPF_MFPH PF9 setting for OPA0_IN_P      \hideinitializer */
    795. 

  795. #define SYS_GPF_MFPH_PF9MFP_PWM0_CH0      (0x4UL<<SYS_GPF_MFPH_PF9MFP_Pos)           /*!< GPF_MFPH PF9 setting for PWM0_CH0      \hideinitializer */
    796. 

  796. 

  797. //GPF_MFPH_PF10MFP
    798. 

  798. #define SYS_GPF_MFPH_PF10MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF10MFP_Pos)           /*!< GPF_MFPH PF10 setting for GPIO   \hideinitializer */
    799. 

  799. #define SYS_GPF_MFPH_PF10MFP_OPA0_IN_N    (0x1UL<<SYS_GPF_MFPH_PF10MFP_Pos)           /*!< GPF_MFPH PF10 setting for OPA0_IN_N    \hideinitializer */
    800. 

  800. #define SYS_GPF_MFPH_PF10MFP_PWM0_CH1     (0x4UL<<SYS_GPF_MFPH_PF10MFP_Pos)           /*!< GPF_MFPH PF10 setting for PWM0_CH1  \hideinitializer */
    801. 

  801. 

  802. //GPF_MFPH_PF11MFP
    803. 

  803. #define SYS_GPF_MFPH_PF11MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF11MFP_Pos)           /*!< GPF_MFPH PF11 setting for GPIO   \hideinitializer */
    804. 

  804. #define SYS_GPF_MFPH_PF11MFP_OPA0_O       (0x1UL<<SYS_GPF_MFPH_PF11MFP_Pos)           /*!< GPF_MFPH PF11 setting for OPA0_O   \hideinitializer */
    805. 

  805. #define SYS_GPF_MFPH_PF11MFP_UART1_RTS    (0x2UL<<SYS_GPF_MFPH_PF11MFP_Pos)           /*!< GPF_MFPH PF11 setting for UART1_RTS   \hideinitializer */
    806. 

  806. 

  807. //GPF_MFPH_PF12MFP
    808. 

  808. #define SYS_GPF_MFPH_PF12MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF12MFP_Pos)           /*!< GPF_MFPH PF12 setting for GPIO   \hideinitializer */
    809. 

  809. #define SYS_GPF_MFPH_PF12MFP_OPA1_IN_P    (0x1UL<<SYS_GPF_MFPH_PF12MFP_Pos)           /*!< GPF_MFPH PF12 setting for OPA1_IN_P   \hideinitializer */
    810. 

  810. #define SYS_GPF_MFPH_PF12MFP_UART1_CTS    (0x2UL<<SYS_GPF_MFPH_PF12MFP_Pos)           /*!< GPF_MFPH PF12 setting for UART1_CTS   \hideinitializer */
    811. 

  811. //GPF_MFPH_PF13MFP
    812. 

  812. #define SYS_GPF_MFPH_PF13MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF13MFP_Pos)           /*!< GPF_MFPH PF13 setting for GPIO   \hideinitializer */
    813. 

  813. #define SYS_GPF_MFPH_PF13MFP_OPA1_IN_N    (0x1UL<<SYS_GPF_MFPH_PF13MFP_Pos)            /*!< GPF_MFPH PF13 setting for OPA1_IN_N  \hideinitializer */
    814. 

  814. #define SYS_GPF_MFPH_PF13MFP_UART1_TXD    (0x2UL<<SYS_GPF_MFPH_PF13MFP_Pos)            /*!< GPF_MFPH PF13 setting for UART1_TXD    \hideinitializer */
    815. 

  815. 

  816. //GPF_MFPH_PF14MFP
    817. 

  817. #define SYS_GPF_MFPH_PF14MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF14MFP_Pos)            /*!< GPF_MFPH PF14 setting for GPIO  \hideinitializer */
    818. 

  818. #define SYS_GPF_MFPH_PF14MFP_OPA1_O       (0x1UL<<SYS_GPF_MFPH_PF14MFP_Pos)           /*!< GPF_MFPH PF14 setting for OPA1_O   \hideinitializer */
    819. 

  819. #define SYS_GPF_MFPH_PF14MFP_UART1_RXD    (0x2UL<<SYS_GPF_MFPH_PF14MFP_Pos)           /*!< GPF_MFPH PF14 setting for UART1_RXD   \hideinitializer */
    820. 

  820. 

  821. //GPF_MFPH_PF15MFP
    822. 

  822. #define SYS_GPF_MFPH_PF15MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF15MFP_Pos)          /*!< GPF_MFPH PF15 setting for GPIO  \hideinitializer */
    823. 

  823. #define SYS_GPF_MFPH_PF15MFP_UART0_RTS    (0x1UL<<SYS_GPF_MFPH_PF15MFP_Pos)            /*!< GPF_MFPH PF15 setting for UART0_RTS  \hideinitializer */
    824. 

  824. 

  825. 

  826. //GPG_MFPL_PG0MFP
    827. 

  827. #define SYS_GPG_MFPL_PG0MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG0MFP_Pos)            /*!< GPG_MFPL PG0 setting for GPIO    \hideinitializer */
    828. 

  828. #define SYS_GPG_MFPL_PG0MFP_UART0_CTS     (0x1UL<<SYS_GPG_MFPL_PG0MFP_Pos)           /*!< GPG_MFPL PG0 setting for UART0_CTS    \hideinitializer */
    829. 

  829. #define SYS_GPG_MFPL_PG0MFP_INT6          (0x8UL<<SYS_GPG_MFPL_PG0MFP_Pos)           /*!< GPG_MFPL PG0 setting for INT6     \hideinitializer */
    830. 

  830. 

  831. //GPG_MFPL_PG1MFP
    832. 

  832. #define SYS_GPG_MFPL_PG1MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG1MFP_Pos)           /*!< GPG_MFPL PG1 setting for GPIO     \hideinitializer */
    833. 

  833. #define SYS_GPG_MFPL_PG1MFP_UART0_RXD     (0x1UL<<SYS_GPG_MFPL_PG1MFP_Pos)           /*!< GPG_MFPL PG1 setting for UART0_RXD    \hideinitializer */
    834. 

  834. 

  835. //GPG_MFPL_PG2MFP
    836. 

  836. #define SYS_GPG_MFPL_PG2MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG2MFP_Pos)           /*!< GPG_MFPL PG2 setting for GPIO     \hideinitializer */
    837. 

  837. #define SYS_GPG_MFPL_PG2MFP_UART0_TXD     (0x1UL<<SYS_GPG_MFPL_PG2MFP_Pos)           /*!< GPG_MFPL PG2 setting for UART0_TXD      \hideinitializer */
    838. 

  838. 

  839. //GPG_MFPL_PG3MFP
    840. 

  840. #define SYS_GPG_MFPL_PG3MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG3MFP_Pos)           /*!< GPG_MFPL PG3 setting for GPIO     \hideinitializer */
    841. 

  841. #define SYS_GPG_MFPL_PG3MFP_PS2_CLK       (0x1UL<<SYS_GPG_MFPL_PG3MFP_Pos)            /*!< GPG_MFPL PG3 setting for PS2_CLK     \hideinitializer */
    842. 

  842. #define SYS_GPG_MFPL_PG3MFP_I2S1_DO       (0x2UL<<SYS_GPG_MFPL_PG3MFP_Pos)            /*!< GPG_MFPL PG3 setting for I2S1_DO     \hideinitializer */
    843. 

  843. #define SYS_GPG_MFPL_PG3MFP_SC1_RST       (0x3UL<<SYS_GPG_MFPL_PG3MFP_Pos)            /*!< GPG_MFPL PG3 setting for SC1_RST     \hideinitializer */
    844. 

  844. //GPG_MFPL_PG4MFP
    845. 

  845. #define SYS_GPG_MFPL_PG4MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG4MFP_Pos)            /*!< GPG_MFPL PG4 setting for GPIO    \hideinitializer */
    846. 

  846. #define SYS_GPG_MFPL_PG4MFP_PS2_DAT       (0x1UL<<SYS_GPG_MFPL_PG4MFP_Pos)           /*!< GPG_MFPL PG4 setting for PS2_DAT      \hideinitializer */
    847. 

  847. #define SYS_GPG_MFPL_PG4MFP_I2S1_DI       (0x2UL<<SYS_GPG_MFPL_PG4MFP_Pos)           /*!< GPG_MFPL PG4 setting for I2S1_DI      \hideinitializer */
    848. 

  848. #define SYS_GPG_MFPL_PG4MFP_SC1_PWR       (0x3UL<<SYS_GPG_MFPL_PG4MFP_Pos)           /*!< GPG_MFPL PG4 setting for SC1_PWR      \hideinitializer */
    849. 

  849. 

  850. //GPG_MFPL_PG5MFP
    851. 

  851. #define SYS_GPG_MFPL_PG5MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG5MFP_Pos)           /*!< GPG_MFPL PG5 setting for GPIO     \hideinitializer */
    852. 

  852. #define SYS_GPG_MFPL_PG5MFP_I2S1_BCLK     (0x2UL<<SYS_GPG_MFPL_PG5MFP_Pos)           /*!< GPG_MFPL PG5 setting for I2S1_BCLK      \hideinitializer */
    853. 

  853. #define SYS_GPG_MFPL_PG5MFP_SC1_DAT       (0x3UL<<SYS_GPG_MFPL_PG5MFP_Pos)           /*!< GPG_MFPL PG5 setting for SC1_DAT    \hideinitializer */
    854. 

  854. //GPG_MFPL_PG6MFP
    855. 

  855. #define SYS_GPG_MFPL_PG6MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG6MFP_Pos)           /*!< GPG_MFPL PG6 setting for GPIO     \hideinitializer */
    856. 

  856. #define SYS_GPG_MFPL_PG6MFP_I2S1_LRCK     (0x2UL<<SYS_GPG_MFPL_PG6MFP_Pos)           /*!< GPG_MFPL PG6 setting for I2S1_LRCK    \hideinitializer */
    857. 

  857. #define SYS_GPG_MFPL_PG6MFP_SC1_CLK       (0x3UL<<SYS_GPG_MFPL_PG6MFP_Pos)           /*!< GPG_MFPL PG6 setting for SC1_CLK    \hideinitializer */
    858. 

  858. 

  859. //GPG_MFPL_PG7MFP
    860. 

  860. #define SYS_GPG_MFPL_PG7MFP_GPIO          (0x0UL<<SYS_GPG_MFPL_PG7MFP_Pos)           /*!< GPG_MFPL PG7 setting for GPIO     \hideinitializer */
    861. 

  861. #define SYS_GPG_MFPL_PG7MFP_SPI2_MISO0    (0x1UL<<SYS_GPG_MFPL_PG7MFP_Pos)           /*!< GPG_MFPL PG7 setting for SPI2_MISO0     \hideinitializer */
    862. 

  862. #define SYS_GPG_MFPL_PG7MFP_I2S1_MCLK     (0x2UL<<SYS_GPG_MFPL_PG7MFP_Pos)           /*!< GPG_MFPL PG7 setting for I2S1_MCLK    \hideinitializer */
    863. 

  863. #define SYS_GPG_MFPL_PG7MFP_SC1_CD        (0x3UL<<SYS_GPG_MFPL_PG7MFP_Pos)           /*!< GPG_MFPL PG7 setting for SC1_CD     \hideinitializer */
    864. 

  864. #define SYS_GPG_MFPL_PG7MFP_SC3_RST       (0x4UL<<SYS_GPG_MFPL_PG7MFP_Pos)           /*!< GPG_MFPL PG7 setting for SC3_RST      \hideinitializer */
    865. 

  865. 

  866. //GPG_MFPL_PG8MFP
    867. 

  867. #define SYS_GPG_MFPH_PG8MFP_GPIO          (0x0UL<<SYS_GPG_MFPH_PG8MFP_Pos)           /*!< GPG_MFPH PG8 setting for GPIO     \hideinitializer */
    868. 

  868. #define SYS_GPG_MFPH_PG8MFP_SPI2_MOSI0    (0x1UL<<SYS_GPG_MFPH_PG8MFP_Pos)           /*!< GPG_MFPH PG8 setting for SPI2_MOSI0     \hideinitializer */
    869. 

  869. #define SYS_GPG_MFPH_PG8MFP_I2S1_DO       (0x2UL<<SYS_GPG_MFPH_PG8MFP_Pos)           /*!< GPG_MFPH PG8 setting for I2S1_DO    \hideinitializer */
    870. 

  870. #define SYS_GPG_MFPH_PG8MFP_UART4_RTS     (0x3UL<<SYS_GPG_MFPH_PG8MFP_Pos)           /*!< GPG_MFPH PG8 setting for UART4_RTS    \hideinitializer */
    871. 

  871. #define SYS_GPG_MFPH_PG8MFP_SC3_DAT       (0x4UL<<SYS_GPG_MFPH_PG8MFP_Pos)           /*!< GPG_MFPH PG8 setting for SC3_DAT    \hideinitializer */
    872. 

  872. 

  873. //GPG_MFPH_PG9MFP
    874. 

  874. #define SYS_GPG_MFPH_PG9MFP_GPIO          (0x0UL<<SYS_GPG_MFPH_PG9MFP_Pos)           /*!< GPG_MFPH PG9 setting for GPIO     \hideinitializer */
    875. 

  875. #define SYS_GPG_MFPH_PG9MFP_SPI2_CLK      (0x1UL<<SYS_GPG_MFPH_PG9MFP_Pos)           /*!< GPG_MFPH PG9 setting for SPI2_CLK     \hideinitializer */
    876. 

  876. #define SYS_GPG_MFPH_PG9MFP_I2S1_DI       (0x2UL<<SYS_GPG_MFPH_PG9MFP_Pos)           /*!< GPG_MFPH PG9 setting for I2S1_DI    \hideinitializer */
    877. 

  877. #define SYS_GPG_MFPH_PG9MFP_UART4_CTS     (0x3UL<<SYS_GPG_MFPH_PG9MFP_Pos)           /*!< GPG_MFPH PG9 setting for UART4_CTS    \hideinitializer */
    878. 

  878. #define SYS_GPG_MFPH_PG9MFP_SC3_CLK       (0x4UL<<SYS_GPG_MFPH_PG9MFP_Pos)           /*!< GPG_MFPH PG9 setting for SC3_CLK      \hideinitializer */
    879. 

  879. 

  880. //GPG_MFPH_PG10MFP
    881. 

  881. #define SYS_GPG_MFPH_PG10MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG10MFP_Pos)           /*!< GPG_MFPH PG10 setting for GPIO   \hideinitializer */
    882. 

  882. #define SYS_GPG_MFPH_PG10MFP_ICE_CLK      (0x1UL<<SYS_GPG_MFPH_PG10MFP_Pos)           /*!< GPG_MFPH PG10 setting for ICE_CLK    \hideinitializer */
    883. 

  883. #define SYS_GPG_MFPH_PG10MFP_JTAG_TCLK    (0x6UL<<SYS_GPG_MFPH_PG10MFP_Pos)           /*!< GPG_MFPH PG10 setting for JTAG_TCLK  \hideinitializer */
    884. 

  884. 

  885. //GPG_MFPH_PG11MFP
    886. 

  886. #define SYS_GPG_MFPH_PG11MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG11MFP_Pos)           /*!< GPG_MFPH PG11 setting for GPIO   \hideinitializer */
    887. 

  887. #define SYS_GPG_MFPH_PG11MFP_ICE_DAT      (0x1UL<<SYS_GPG_MFPH_PG11MFP_Pos)           /*!< GPG_MFPH PG11 setting for ICE_DAT   \hideinitializer */
    888. 

  888. #define SYS_GPG_MFPH_PG11MFP_JTAG_TMS     (0x6UL<<SYS_GPG_MFPH_PG11MFP_Pos)           /*!< GPG_MFPH PG11 setting for JTAG_TMS   \hideinitializer */
    889. 

  889. 

  890. //GPG_MFPH_PG12MFP
    891. 

  891. #define SYS_GPG_MFPH_PG12MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG12MFP_Pos)           /*!< GPG_MFPH PG12 setting for GPIO   \hideinitializer */
    892. 

  892. #define SYS_GPG_MFPH_PG12MFP_XT1_OUT      (0x1UL<<SYS_GPG_MFPH_PG12MFP_Pos)           /*!< GPG_MFPH PG12 setting for XT1_OUT   \hideinitializer */
    893. 

  893. 

  894. //GPG_MFPH_PG13MFP
    895. 

  895. #define SYS_GPG_MFPH_PG13MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG13MFP_Pos)           /*!< GPG_MFPH PG13 setting for GPIO   \hideinitializer */
    896. 

  896. #define SYS_GPG_MFPH_PG13MFP_XT1_IN       (0x1UL<<SYS_GPG_MFPH_PG13MFP_Pos)           /*!< GPG_MFPH PG13 setting for XT1_IN   \hideinitializer */
    897. 

  897. 

  898. //GPG_MFPH_PG14MFP
    899. 

  899. #define SYS_GPG_MFPH_PG14MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for GPIO   \hideinitializer */
    900. 

  900. #define SYS_GPG_MFPH_PG14MFP_X32K_OUT     (0x1UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for X32K_OUT   \hideinitializer */
    901. 

  901. #define SYS_GPG_MFPH_PG14MFP_I2C1_SDA     (0x3UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for I2C1_SDA   \hideinitializer */
    902. 

  902. 

  903. //GPG_MFPH_PG15MFP
    904. 

  904. #define SYS_GPG_MFPH_PG15MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for GPIO   \hideinitializer */
    905. 

  905. #define SYS_GPG_MFPH_PG15MFP_X32K_IN      (0x1UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for X32K_IN   \hideinitializer */
    906. 

  906. #define SYS_GPG_MFPH_PG15MFP_I2C1_SCL     (0x3UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for I2C1_SCL   \hideinitializer */
    907. 

  907. 

  908. 

  909. //GPH_MFPL_PH0MFP
    910. 

  910. #define SYS_GPH_MFPL_PH0MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH0MFP_Pos)           /*!< GPH_MFPL PH0 setting for GPIO     \hideinitializer */
    911. 

  911. #define SYS_GPH_MFPL_PH0MFP_I2C1_SCL      (0x1UL<<SYS_GPH_MFPL_PH0MFP_Pos)           /*!< GPH_MFPL PH0 setting for I2C1_SCL     \hideinitializer */
    912. 

  912. #define SYS_GPH_MFPL_PH0MFP_UART4_RXD     (0x2UL<<SYS_GPH_MFPL_PH0MFP_Pos)           /*!< GPH_MFPL PH0 setting for UART4_RXD    \hideinitializer */
    913. 

  913. #define SYS_GPH_MFPL_PH0MFP_CAN1_RXD      (0x3UL<<SYS_GPH_MFPL_PH0MFP_Pos)           /*!< GPH_MFPL PH0 setting for CAN1_RXD     \hideinitializer */
    914. 

  914. #define SYS_GPH_MFPL_PH0MFP_INT7          (0x8UL<<SYS_GPH_MFPL_PH0MFP_Pos)           /*!< GPH_MFPL PH0 setting for INT7     \hideinitializer */
    915. 

  915. 

  916. //GPH_MFPL_PH1MFP
    917. 

  917. #define SYS_GPH_MFPL_PH1MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH1MFP_Pos)           /*!< GPH_MFPL PH1 setting for GPIO     \hideinitializer */
    918. 

  918. #define SYS_GPH_MFPL_PH1MFP_UART4_TXD     (0x1UL<<SYS_GPH_MFPL_PH1MFP_Pos)            /*!< GPH_MFPL PH1 setting for UART4_TXD     \hideinitializer */
    919. 

  919. #define SYS_GPH_MFPL_PH1MFP_I2C1_SDA      (0x2UL<<SYS_GPH_MFPL_PH1MFP_Pos)            /*!< GPH_MFPL PH1 setting for I2C1_SDA    \hideinitializer */
    920. 

  920. #define SYS_GPH_MFPL_PH1MFP_CAN1_TXD      (0x3UL<<SYS_GPH_MFPL_PH1MFP_Pos)            /*!< GPH_MFPL PH1 setting for CAN1_TXD    \hideinitializer */
    921. 

  921. 

  922. //GPH_MFPL_PH2MFP
    923. 

  923. #define SYS_GPH_MFPL_PH2MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH2MFP_Pos)            /*!< GPH_MFPL PH2 setting for GPIO    \hideinitializer */
    924. 

  924. #define SYS_GPH_MFPL_PH2MFP_UART2_CTS     (0x1UL<<SYS_GPH_MFPL_PH2MFP_Pos)           /*!< GPH_MFPL PH2 setting for UART2_CTS    \hideinitializer */
    925. 

  925. 

  926. //GPH_MFPL_PH3MFP
    927. 

  927. #define SYS_GPH_MFPL_PH3MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH3MFP_Pos)           /*!< GPH_MFPL PH3 setting for GPIO     \hideinitializer */
    928. 

  928. #define SYS_GPH_MFPL_PH3MFP_I2C3_SCL      (0x1UL<<SYS_GPH_MFPL_PH3MFP_Pos)           /*!< GPH_MFPL PH3 setting for I2C3_SCL     \hideinitializer */
    929. 

  929. 

  930. //GPH_MFPL_PH4MFP
    931. 

  931. #define SYS_GPH_MFPL_PH4MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH4MFP_Pos)           /*!< GPH_MFPL PH4 setting for GPIO     \hideinitializer */
    932. 

  932. #define SYS_GPH_MFPL_PH4MFP_I2C3_SDA      (0x1UL<<SYS_GPH_MFPL_PH4MFP_Pos)           /*!< GPH_MFPL PH4 setting for I2C3_SDA     \hideinitializer */
    933. 

  933. 

  934. //GPH_MFPL_PH5MFP
    935. 

  935. #define SYS_GPH_MFPL_PH5MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH5MFP_Pos)           /*!< GPH_MFPL PH5 setting for GPIO     \hideinitializer */
    936. 

  936. #define SYS_GPH_MFPL_PH5MFP_SPI2_SS0      (0x1UL<<SYS_GPH_MFPL_PH5MFP_Pos)           /*!< GPH_MFPL PH5 setting for SPI2_SS0     \hideinitializer */
    937. 

  937. 

  938. //GPH_MFPL_PH6MFP
    939. 

  939. #define SYS_GPH_MFPL_PH6MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH6MFP_Pos)           /*!< GPH_MFPL PH6 setting for GPIO     \hideinitializer */
    940. 

  940. #define SYS_GPH_MFPL_PH6MFP_SPI2_CLK      (0x1UL<<SYS_GPH_MFPL_PH6MFP_Pos)            /*!< GPH_MFPL PH6 setting for SPI2_CLK    \hideinitializer */
    941. 

  941. 

  942. //GPH_MFPL_PH7MFP
    943. 

  943. #define SYS_GPH_MFPL_PH7MFP_GPIO          (0x0UL<<SYS_GPH_MFPL_PH7MFP_Pos)            /*!< GPH_MFPL PH7 setting for GPIO    \hideinitializer */
    944. 

  944. #define SYS_GPH_MFPL_PH7MFP_SPI2_MISO0    (0x1UL<<SYS_GPH_MFPL_PH7MFP_Pos)            /*!< GPH_MFPL PH7 setting for SPI2_MISO0    \hideinitializer */
    945. 

  945. 

  946. //GPH_MFPL_PH8MFP
    947. 

  947. #define SYS_GPH_MFPH_PH8MFP_GPIO          (0x0UL<<SYS_GPH_MFPH_PH8MFP_Pos)            /*!< GPH_MFPH PH8 setting for GPIO    \hideinitializer */
    948. 

  948. #define SYS_GPH_MFPH_PH8MFP_SPI2_MOSI0    (0x1UL<<SYS_GPH_MFPH_PH8MFP_Pos)           /*!< GPH_MFPH PH8 setting for SPI2_MOSI0     \hideinitializer */
    949. 

  949. 

  950. //GPH_MFPH_PH9MFP
    951. 

  951. #define SYS_GPH_MFPH_PH9MFP_GPIO          (0x0UL<<SYS_GPH_MFPH_PH9MFP_Pos)           /*!< GPH_MFPH PH9 setting for GPIO     \hideinitializer */
    952. 

  952. #define SYS_GPH_MFPH_PH9MFP_SPI2_MISO1    (0x1UL<<SYS_GPH_MFPH_PH9MFP_Pos)           /*!< GPH_MFPH PH9 setting for SPI2_MISO1     \hideinitializer */
    953. 

  953. 

  954. //GPH_MFPH_PH10MFP
    955. 

  955. #define SYS_GPH_MFPH_PH10MFP_GPIO         (0x0UL<<SYS_GPH_MFPH_PH10MFP_Pos)           /*!< GPH_MFPH PH10 setting for GPIO   \hideinitializer */
    956. 

  956. #define SYS_GPH_MFPH_PH10MFP_SPI2_MOSI1   (0x1UL<<SYS_GPH_MFPH_PH10MFP_Pos)           /*!< GPH_MFPH PH10 setting for SPI2_MOSI1   \hideinitializer */
    957. 

  957. 

  958. //GPH_MFPH_PH11MFP
    959. 

  959. #define SYS_GPH_MFPH_PH11MFP_GPIO         (0x0UL<<SYS_GPH_MFPH_PH11MFP_Pos)           /*!< GPH_MFPH PH11 setting for GPIO   \hideinitializer */
    960. 

  960. #define SYS_GPH_MFPH_PH11MFP_UART3_RXD    (0x1UL<<SYS_GPH_MFPH_PH11MFP_Pos)           /*!< GPH_MFPH PH11 setting for UART3_RXD   \hideinitializer */
    961. 

  961. 

  962. //GPH_MFPH_PH12MFP
    963. 

  963. #define SYS_GPH_MFPH_PH12MFP_GPIO         (0x0UL<<SYS_GPH_MFPH_PH12MFP_Pos)           /*!< GPH_MFPH PH12 setting for GPIO   \hideinitializer */
    964. 

  964. #define SYS_GPH_MFPH_PH12MFP_UART3_TXD    (0x1UL<<SYS_GPH_MFPH_PH12MFP_Pos)           /*!< GPH_MFPH PH12 setting for UART3_TXD   \hideinitializer */
    965. 

  965. 

  966. //GPH_MFPH_PH13MFP
    967. 

  967. #define SYS_GPH_MFPH_PH13MFP_GPIO         (0x0UL<<SYS_GPH_MFPH_PH13MFP_Pos)           /*!< GPH_MFPH PH13 setting for GPIO   \hideinitializer */
    968. 

  968. #define SYS_GPH_MFPH_PH13MFP_UART3_RTS    (0x1UL<<SYS_GPH_MFPH_PH13MFP_Pos)           /*!< GPH_MFPH PH13 setting for UART3_RTS   \hideinitializer */
    969. 

  969. 

  970. //GPH_MFPH_PH14MFP
    971. 

  971. #define SYS_GPH_MFPH_PH14MFP_GPIO         (0x0UL<<SYS_GPH_MFPH_PH14MFP_Pos)           /*!< GPH_MFPH PH14 setting for GPIO   \hideinitializer */
    972. 

  972. #define SYS_GPH_MFPH_PH14MFP_UART3_CTS    (0x1UL<<SYS_GPH_MFPH_PH14MFP_Pos)           /*!< GPH_MFPH PH14 setting for UART3_CTS   \hideinitializer */
    973. 

  973. 

  974. //GPH_MFPH_PH15MFP
    975. 

  975. #define SYS_GPH_MFPH_PH15MFP_GPIO         (0x0UL<<SYS_GPH_MFPH_PH15MFP_Pos)           /*!< GPH_MFPH PH15 setting for GPIO   \hideinitializer */
    976. 

  976. #define SYS_GPH_MFPH_PH15MFP_SC5_CLK      (0x2UL<<SYS_GPH_MFPH_PH15MFP_Pos)           /*!< GPH_MFPH PH15 setting for SC5_CLK   \hideinitializer */
    977. 

  977. 

  978. //GPI_MFPL_PI0MFP
    979. 

  979. #define SYS_GPI_MFPL_PI0MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI0MFP_Pos)           /*!< GPI_MFPL PI0 setting for GPIO     \hideinitializer */
    980. 

  980. #define SYS_GPI_MFPL_PI0MFP_SC5_RST       (0x2UL<<SYS_GPI_MFPL_PI0MFP_Pos)            /*!< GPI_MFPL PI0 setting for SC5_RST     \hideinitializer */
    981. 

  981. 

  982. //GPI_MFPL_PI1MFP
    983. 

  983. #define SYS_GPI_MFPL_PI1MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI1MFP_Pos)            /*!< GPI_MFPL PI1 setting for GPIO    \hideinitializer */
    984. 

  984. #define SYS_GPI_MFPL_PI1MFP_SC5_PWR       (0x2UL<<SYS_GPI_MFPL_PI1MFP_Pos)            /*!< GPI_MFPL PI1 setting for SC5_PWR     \hideinitializer */
    985. 

  985. 

  986. //GPI_MFPL_PI2MFP
    987. 

  987. #define SYS_GPI_MFPL_PI2MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI2MFP_Pos)            /*!< GPI_MFPL PI2 setting for GPIO    \hideinitializer */
    988. 

  988. #define SYS_GPI_MFPL_PI2MFP_SC5_DAT       (0x2UL<<SYS_GPI_MFPL_PI2MFP_Pos)           /*!< GPI_MFPL PI2 setting for SC5_DAT      \hideinitializer */
    989. 

  989. 

  990. //GPI_MFPL_PI3MFP
    991. 

  991. #define SYS_GPI_MFPL_PI3MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI3MFP_Pos)           /*!< GPI_MFPL PI3 setting for GPIO     \hideinitializer */
    992. 

  992. #define SYS_GPI_MFPL_PI3MFP_SPI3_SS0      (0x1UL<<SYS_GPI_MFPL_PI3MFP_Pos)            /*!< GPI_MFPL PI3 setting for SPI3_SS0      \hideinitializer */
    993. 

  993. 

  994. //GPI_MFPL_PI4MFP
    995. 

  995. #define SYS_GPI_MFPL_PI4MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI4MFP_Pos)            /*!< GPI_MFPL PI4 setting for GPIO    \hideinitializer */
    996. 

  996. #define SYS_GPI_MFPL_PI4MFP_SPI3_CLK      (0x1UL<<SYS_GPI_MFPL_PI4MFP_Pos)           /*!< GPI_MFPL PI4 setting for SPI3_CLK     \hideinitializer */
    997. 

  997. 

  998. //GPI_MFPL_PI5MFP
    999. 

  999. #define SYS_GPI_MFPL_PI5MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI5MFP_Pos)           /*!< GPI_MFPL PI5 setting for GPIO     \hideinitializer */
    1000. 

  1000. #define SYS_GPI_MFPL_PI5MFP_SPI3_MISO0    (0x1UL<<SYS_GPI_MFPL_PI5MFP_Pos)           /*!< GPI_MFPL PI5 setting for SPI3_MISO0     \hideinitializer */
    1001. 

  1001. 

  1002. //GPI_MFPL_PI6MFP
    1003. 

  1003. #define SYS_GPI_MFPL_PI6MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI6MFP_Pos)           /*!< GPI_MFPL PI6 setting for GPIO     \hideinitializer */
    1004. 

  1004. #define SYS_GPI_MFPL_PI6MFP_SPI3_MOSI0    (0x1UL<<SYS_GPI_MFPL_PI6MFP_Pos)           /*!< GPI_MFPL PI6 setting for SPI3_MOSI0     \hideinitializer */
    1005. 

  1005. 

  1006. //GPI_MFPL_PI7MFP
    1007. 

  1007. #define SYS_GPI_MFPL_PI7MFP_GPIO          (0x0UL<<SYS_GPI_MFPL_PI7MFP_Pos)           /*!< GPI_MFPL PI7 setting for GPIO     \hideinitializer */
    1008. 

  1008. #define SYS_GPI_MFPL_PI7MFP_I2C2_SCL      (0x1UL<<SYS_GPI_MFPL_PI7MFP_Pos)           /*!< GPI_MFPL PI7 setting for I2C2_SCL     \hideinitializer */
    1009. 

  1009. #define SYS_GPI_MFPL_PI7MFP_SPI3_MISO1    (0x2UL<<SYS_GPI_MFPL_PI7MFP_Pos)           /*!< GPI_MFPL PI7 setting for SPI3_MISO1     \hideinitializer */
    1010. 

  1010. 

  1011. //GPI_MFPL_PI8MFP
    1012. 

  1012. #define SYS_GPI_MFPH_PI8MFP_GPIO          (0x0UL<<SYS_GPI_MFPH_PI8MFP_Pos)           /*!< GPI_MFPH PI8 setting for GPIO     \hideinitializer */
    1013. 

  1013. #define SYS_GPI_MFPH_PI8MFP_I2C2_SDA      (0x1UL<<SYS_GPI_MFPH_PI8MFP_Pos)           /*!< GPI_MFPH PI8 setting for I2C2_SDA     \hideinitializer */
    1014. 

  1014. #define SYS_GPI_MFPH_PI8MFP_SPI3_MOSI1    (0x2UL<<SYS_GPI_MFPH_PI8MFP_Pos)           /*!< GPI_MFPH PI8 setting for SPI3_MOSI1     \hideinitializer */
    1015. 

  1015. 

  1016. //GPI_MFPH_PI9MFP
    1017. 

  1017. #define SYS_GPI_MFPH_PI9MFP_GPIO          (0x0UL<<SYS_GPI_MFPH_PI9MFP_Pos)           /*!< GPI_MFPH PI9 setting for GPIO     \hideinitializer */
    1018. 

  1018. #define SYS_GPI_MFPH_PI9MFP_I2C4_SCL      (0x4UL<<SYS_GPI_MFPH_PI9MFP_Pos)           /*!< GPI_MFPH PI9 setting for I2C4_SCL     \hideinitializer */
    1019. 

  1019. 

  1020. //GPI_MFPH_PI10MFP
    1021. 

  1021. #define SYS_GPI_MFPH_PI10MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI10MFP_Pos)           /*!< GPI_MFPH PI10 setting for GPIO   \hideinitializer */
    1022. 

  1022. 

  1023. //GPI_MFPH_PI11MFP
    1024. 

  1024. #define SYS_GPI_MFPH_PI11MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI11MFP_Pos)           /*!< GPI_MFPH PI11 setting for GPIO   \hideinitializer */
    1025. 

  1025. #define SYS_GPI_MFPH_PI11MFP_SPI2_SS0     (0x1UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for SPI2_SS0  \hideinitializer */
    1026. 

  1026. #define SYS_GPI_MFPH_PI11MFP_I2S1_BCLK    (0x2UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for I2S1_BCLK  \hideinitializer */
    1027. 

  1027. #define SYS_GPI_MFPH_PI11MFP_I2C4_SCL     (0x3UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for I2C4_SCL  \hideinitializer */
    1028. 

  1028. #define SYS_GPI_MFPH_PI11MFP_SC3_PWR      (0x4UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for SC3_PWR  \hideinitializer */
    1029. 

  1029. 

  1030. //GPI_MFPH_PI12MFP
    1031. 

  1031. #define SYS_GPI_MFPH_PI12MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for GPIO  \hideinitializer */
    1032. 

  1032. #define SYS_GPI_MFPH_PI12MFP_SPI2_MISO1   (0x1UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for SPI2_MISO1    \hideinitializer */
    1033. 

  1033. #define SYS_GPI_MFPH_PI12MFP_I2S1_LRCK    (0x2UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for I2S1_LRCK     \hideinitializer */
    1034. 

  1034. #define SYS_GPI_MFPH_PI12MFP_I2C4_SDA     (0x3UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for I2C4_SDA  \hideinitializer */
    1035. 

  1035. #define SYS_GPI_MFPH_PI12MFP_SC3_CD       (0x4UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for SC3_CD    \hideinitializer */
    1036. 

  1036. 

  1037. //GPI_MFPH_PI13MFP
    1038. 

  1038. #define SYS_GPI_MFPH_PI13MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI13MFP_Pos)            /*!< GPI_MFPH PI13 setting for GPIO  \hideinitializer */
    1039. 

  1039. 

  1040. //GPI_MFPH_PI14MFP
    1041. 

  1041. #define SYS_GPI_MFPH_PI14MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI14MFP_Pos)            /*!< GPI_MFPH PI14 setting for GPIO  \hideinitializer */
    1042. 

  1042. 

  1043. //GPI_MFPH_PI15MFP
    1044. 

  1044. #define SYS_GPI_MFPH_PI15MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI15MFP_Pos)            /*!< GPI_MFPH PI15 setting for GPIO  \hideinitializer */
    1045. 

  1045. 

  1046. /*@}*/ /* end of group NUC472_442_SYS_EXPORTED_CONSTANTS */
    1047. 

  1047. 

  1048. /** @addtogroup NUC472_442_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
    1049. 

  1049.   @{
    1050. 

  1050. */
    1051. 

  1051. 

  1052. /**
    1053. 

  1053.   * @brief      Clear Brown-out detector interrupt flag
    1054. 

  1054.   * @param      None  
    1055. 

  1055.   * @return     None
    1056. 

  1056.   * @details    This macro clear Brown-out detector interrupt flag.
    1057. 

  1057.   */
    1058. 

  1058. #define SYS_CLEAR_BOD_INT_FLAG()        (SYS->BODCTL |= SYS_BODCTL_BODINTF_Msk)
    1059. 

  1059. 

  1060. /**
    1061. 

  1061.   * @brief      Set Brown-out detector function to normal mode
    1062. 

  1062.   * @param      None  
    1063. 

  1063.   * @return     None
    1064. 

  1064.   * @details    This macro set Brown-out detector to normal mode.
    1065. 

  1065.   */
    1066. 

  1066. #define SYS_CLEAR_BOD_LPM()             (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
    1067. 

  1067. 

  1068. /**
    1069. 

  1069.   * @brief      Disable Brown-out detector function
    1070. 

  1070.   * @param      None  
    1071. 

  1071.   * @return     None
    1072. 

  1072.   * @details    This macro disable Brown-out detector function.  
    1073. 

  1073.   */
    1074. 

  1074. #define SYS_DISABLE_BOD()               (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)     
    1075. 

  1075. 

  1076. /**
    1077. 

  1077.   * @brief      Enable Brown-out detector function
    1078. 

  1078.   * @param      None  
    1079. 

  1079.   * @return     None
    1080. 

  1080.   * @details    This macro enable Brown-out detector function.  
    1081. 

  1081.   */
    1082. 

  1082. #define SYS_ENABLE_BOD()                (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
    1083. 

  1083. /**
    1084. 

  1084.   * @brief      Get Brown-out detector interrupt flag
    1085. 

  1085.   * @param      None    
    1086. 

  1086.   * @retval     0   Brown-out detect interrupt flag is not set.
    1087. 

  1087.   * @retval     >=1 Brown-out detect interrupt flag is set.
    1088. 

  1088.   * @details    This macro get Brown-out detector interrupt flag.    
    1089. 

  1089.   */
    1090. 

  1090. #define SYS_GET_BOD_INT_FLAG()          (SYS->BODCTL & SYS_BODCTL_BODINTF_Msk)    
    1091. 

  1091. 

  1092. /**
    1093. 

  1093.   * @brief      Get Brown-out detector status
    1094. 

  1094.   * @param      None 
    1095. 

  1095.   * @retval     0   System voltage is higher than BOD_VL setting or BOD_EN is 0.
    1096. 

  1096.   * @retval     >=1 System voltage is lower than BOD_VL setting.
    1097. 

  1097.   * @details    This macro get Brown-out detector output status.
    1098. 

  1098.   *             If the BOD_EN is 0, this function always return 0.
    1099. 

  1099.   */
    1100. 

  1100. #define SYS_GET_BOD_OUTPUT()            (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
    1101. 

  1101. 

  1102. /**
    1103. 

  1103.   * @brief      Disable Brown-out detector interrupt function
    1104. 

  1104.   * @param      None   
    1105. 

  1105.   * @return     None
    1106. 

  1106.   * @details    This macro enable Brown-out detector interrupt function.
    1107. 

  1107.   */
    1108. 

  1108. #define SYS_DISABLE_BOD_RST()           (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
    1109. 

  1109. 

  1110. /**
    1111. 

  1111.   * @brief      Enable Brown-out detector reset function
    1112. 

  1112.   * @param      None     
    1113. 

  1113.   * @return     None
    1114. 

  1114.   * @details    This macro enable Brown-out detect reset function.  
    1115. 

  1115.   */
    1116. 

  1116. #define SYS_ENABLE_BOD_RST()            (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
    1117. 

  1117. 

  1118. 

  1119. /**
    1120. 

  1120.   * @brief      Set Brown-out detector function low power mode 
    1121. 

  1121.   * @param      None     
    1122. 

  1122.   * @return     None
    1123. 

  1123.   * @details    This macro set Brown-out detector to low power mode.  
    1124. 

  1124.   */
    1125. 

  1125. #define SYS_SET_BOD_LPM()               (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
    1126. 

  1126. 

  1127. /**
    1128. 

  1128.   * @brief      Set Brown-out detector voltage level
    1129. 

  1129.   * @param[in]  u32Level is Brown-out voltage level. Including :
    1130. 

  1130.   *             - \ref SYS_BODCTL_BODVL_4_5V
    1131. 

  1131.   *             - \ref SYS_BODCTL_BODVL_3_8V
    1132. 

  1132.   *             - \ref SYS_BODCTL_BODVL_2_7V
    1133. 

  1133.   *             - \ref SYS_BODCTL_BODVL_2_2V
    1134. 

  1134.   * @return     None
    1135. 

  1135.   * @details    This macro set Brown-out detector voltage level.  
    1136. 

  1136.   */
    1137. 

  1137. #define SYS_SET_BOD_LEVEL(u32Level)     (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32Level) 
    1138. 

  1138. 

  1139. /**
    1140. 

  1140.   * @brief      Get reset source is from Brown-out detector reset
    1141. 

  1141.   * @param      None    
    1142. 

  1142.   * @retval     0   Previous reset source is not from Brown-out detector reset
    1143. 

  1143.   * @retval     >=1 Previous reset source is from Brown-out detector reset
    1144. 

  1144.   * @details    This macro get previous reset source is from Brown-out detect reset or not.    
    1145. 

  1145.   */
    1146. 

  1146. #define SYS_IS_BOD_RST()                (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
    1147. 

  1147. 

  1148. /**
    1149. 

  1149.   * @brief      Get reset source is from CPU reset
    1150. 

  1150.   * @param      None     
    1151. 

  1151.   * @retval     0   Previous reset source is not from CPU reset
    1152. 

  1152.   * @retval     >=1 Previous reset source is from CPU reset
    1153. 

  1153.   * @details    This macro get previous reset source is from CPU reset. 
    1154. 

  1154.   */
    1155. 

  1155. #define SYS_IS_CPU_RST()                (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
    1156. 

  1156. 

  1157. /**
    1158. 

  1158.   * @brief      Get reset source is from LVR Reset
    1159. 

  1159.   * @param      None     
    1160. 

  1160.   * @retval     0   Previous reset source is not from LVR Reset
    1161. 

  1161.   * @retval     >=1 Previous reset source is from LVR Reset
    1162. 

  1162.   * @details    This macro get previous reset source is from Power-on Reset.   
    1163. 

  1163.   */
    1164. 

  1164. #define SYS_IS_LVR_RST()                (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
    1165. 

  1165. 

  1166. /**
    1167. 

  1167.   * @brief      Get reset source is from Power-on Reset
    1168. 

  1168.   * @param      None     
    1169. 

  1169.   * @retval     0   Previous reset source is not from Power-on Reset
    1170. 

  1170.   * @retval     >=1 Previous reset source is from Power-on Reset
    1171. 

  1171.   * @details    This macro get previous reset source is from Power-on Reset.   
    1172. 

  1172.   */
    1173. 

  1173. #define SYS_IS_POR_RST()                (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
    1174. 

  1174. 

  1175. /**
    1176. 

  1176.   * @brief      Get reset source is from reset pin reset
    1177. 

  1177.   * @param      None     
    1178. 

  1178.   * @retval     0   Previous reset source is not from reset pin reset
    1179. 

  1179.   * @retval     >=1 Previous reset source is from reset pin reset
    1180. 

  1180.   * @details    This macro get previous reset source is from reset pin reset.  
    1181. 

  1181.   */
    1182. 

  1182. #define SYS_IS_RSTPIN_RST()             (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
    1183. 

  1183. 

  1184. /**
    1185. 

  1185.   * @brief      Get reset source is from system reset
    1186. 

  1186.   * @param      None     
    1187. 

  1187.   * @retval     0   Previous reset source is not from system reset
    1188. 

  1188.   * @retval     >=1 Previous reset source is from system reset
    1189. 

  1189.   * @details    This macro get previous reset source is from system reset.   
    1190. 

  1190.   */
    1191. 

  1191. #define SYS_IS_SYSTEM_RST()             (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
    1192. 

  1192. 

  1193. /**
    1194. 

  1194.   * @brief      Get reset source is from window watch dog reset
    1195. 

  1195.   * @param      None
    1196. 

  1196.   * @retval     0   Previous reset source is not from window watch dog reset
    1197. 

  1197.   * @retval     >=1 Previous reset source is from window watch dog reset
    1198. 

  1198.   * @details    This macro get previous reset source is from window watch dog reset.    
    1199. 

  1199.   */
    1200. 

  1200. #define SYS_IS_WDT_RST()                (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
    1201. 

  1201. 

  1202. /**
    1203. 

  1203.   * @brief      Disable Low-Voltage-Reset function
    1204. 

  1204.   * @param      None  
    1205. 

  1205.   * @return     None
    1206. 

  1206.   * @details    This macro disable Low-Voltage-Reset function.      
    1207. 

  1207.   */
    1208. 

  1208. #define SYS_DISABLE_LVR()               (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
    1209. 

  1209. 

  1210. /**
    1211. 

  1211.   * @brief      Enable Low-Voltage-Reset function
    1212. 

  1212.   * @param      None  
    1213. 

  1213.   * @return     None
    1214. 

  1214.   * @details    This macro enable Low-Voltage-Reset function.  
    1215. 

  1215.   */
    1216. 

  1216. #define SYS_ENABLE_LVR()                (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
    1217. 

  1217. 

  1218. /**
    1219. 

  1219.   * @brief      Disable Power-on Reset function
    1220. 

  1220.   * @param      None  
    1221. 

  1221.   * @return     None
    1222. 

  1222.   * @details    This macro disable Power-on Reset function.  
    1223. 

  1223.   */
    1224. 

  1224. #define SYS_DISABLE_POR()               (SYS->PORCTL = 0x5AA5)
    1225. 

  1225. 

  1226. /**
    1227. 

  1227.   * @brief      Enable Power-on Reset function
    1228. 

  1228.   * @param      None  
    1229. 

  1229.   * @return     None
    1230. 

  1230.   * @details    This macro enable Power-on Reset function.  
    1231. 

  1231.   */
    1232. 

  1232. #define SYS_ENABLE_POR()                (SYS->PORCTL = 0)
    1233. 

  1233. 

  1234. 

  1235. /**
    1236. 

  1236.   * @brief      Clear reset source flag
    1237. 

  1237.   * @param[in]  u32RstSrc is reset source. Including:
    1238. 

  1238.   *             - \ref SYS_RSTSTS_PORF_Msk
    1239. 

  1239.   *             - \ref SYS_RSTSTS_PINRF_Msk  
    1240. 

  1240.   *             - \ref SYS_RSTSTS_WDTRF_Msk
    1241. 

  1241.   *             - \ref SYS_RSTSTS_LVRF_Msk 
    1242. 

  1242.   *             - \ref SYS_RSTSTS_BODRF_Msk 
    1243. 

  1243.   *             - \ref SYS_RSTSTS_SYSRF_Msk   
    1244. 

  1244. 	*             - \ref SYS_RSTSTS_CPURF_Msk
    1245. 

  1245.   * @return     None
    1246. 

  1246.   * @details    This macro clear reset source flag.   
    1247. 

  1247.   */
    1248. 

  1248. #define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSTS = u32RstSrc )
    1249. 

  1249. 

  1250. void SYS_ClearResetSrc(uint32_t u32Src);
    1251. 

  1251. uint32_t SYS_GetBODStatus(void);
    1252. 

  1252. uint32_t SYS_GetResetSrc(void);
    1253. 

  1253. uint32_t SYS_IsRegLocked(void);
    1254. 

  1254. void SYS_LockReg(void);
    1255. 

  1255. void SYS_UnlockReg(void);
    1256. 

  1256. uint32_t  SYS_ReadPDID(void);
    1257. 

  1257. void SYS_ResetChip(void);
    1258. 

  1258. void SYS_ResetCPU(void);
    1259. 

  1259. void SYS_ResetModule(uint32_t u32ModuleIndex);
    1260. 

  1260. void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
    1261. 

  1261. void SYS_DisableBOD(void);
    1262. 

  1262. 

  1263. /*@}*/ /* end of group NUC472_442_SYS_EXPORTED_FUNCTIONS */
    1264. 

  1264. 

  1265. /*@}*/ /* end of group NUC472_442_SYS_Driver */
    1266. 

  1266. 

  1267. /*@}*/ /* end of group NUC472_442_Device_Driver */
    1268. 

  1268. 

  1269. #ifdef __cplusplus
    1270. 

  1270. }
    1271. 

  1271. #endif
    1272. 

  1272. 

  1273. #endif //__SYS_H__
    1274. 

  1274. 

  1275. /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
    1276.