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- /*
- * Copyright (c) 2013 Nuvoton Technology Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Description: NUC472 EMAC driver header file
- */
- #include "lwip/def.h"
- #include "lwip/pbuf.h"
- #include "NUC472_442.h"
- #ifndef _NUC472_ETH_
- #define _NUC472_ETH_
- /* Generic MII registers. */
- #define MII_BMCR 0x00 /* Basic mode control register */
- #define MII_BMSR 0x01 /* Basic mode status register */
- #define MII_PHYSID1 0x02 /* PHYS ID 1 */
- #define MII_PHYSID2 0x03 /* PHYS ID 2 */
- #define MII_ADVERTISE 0x04 /* Advertisement control reg */
- #define MII_LPA 0x05 /* Link partner ability reg */
- #define MII_EXPANSION 0x06 /* Expansion register */
- #define MII_DCOUNTER 0x12 /* Disconnect counter */
- #define MII_FCSCOUNTER 0x13 /* False carrier counter */
- #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
- #define MII_RERRCOUNTER 0x15 /* Receive error counter */
- #define MII_SREVISION 0x16 /* Silicon revision */
- #define MII_RESV1 0x17 /* Reserved... */
- #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
- #define MII_PHYADDR 0x19 /* PHY address */
- #define MII_RESV2 0x1a /* Reserved... */
- #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
- #define MII_NCONFIG 0x1c /* Network interface config */
- /* Basic mode control register. */
- #define BMCR_RESV 0x007f /* Unused... */
- #define BMCR_CTST 0x0080 /* Collision test */
- #define BMCR_FULLDPLX 0x0100 /* Full duplex */
- #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
- #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
- #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
- #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
- #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
- #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
- #define BMCR_RESET 0x8000 /* Reset the DP83840 */
- /* Basic mode status register. */
- #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
- #define BMSR_JCD 0x0002 /* Jabber detected */
- #define BMSR_LSTATUS 0x0004 /* Link status */
- #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
- #define BMSR_RFAULT 0x0010 /* Remote fault detected */
- #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
- #define BMSR_RESV 0x07c0 /* Unused... */
- #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
- #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
- #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
- #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
- #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
- /* Advertisement control register. */
- #define ADVERTISE_SLCT 0x001f /* Selector bits */
- #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
- #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
- #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
- #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
- #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
- #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
- #define ADVERTISE_RESV 0x1c00 /* Unused... */
- #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
- #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
- #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
- #define RX_DESCRIPTOR_NUM 4 // Max Number of Rx Frame Descriptors
- #define TX_DESCRIPTOR_NUM 2 // Max number of Tx Frame Descriptors
- #define PACKET_BUFFER_SIZE 1520
- #define CONFIG_PHY_ADDR 1
- // Frame Descriptor's Owner bit
- #define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
- //#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
- // Rx Frame Descriptor Status
- #define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
- #define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
- // Tx Frame Descriptor's Control bits
- #define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
- #define TXFD_INTEN 0x04 // Interrupt Enable
- #define TXFD_CRCAPP 0x02 // Append CRC
- #define TXFD_PADEN 0x01 // Padding Enable
- // Tx Frame Descriptor Status
- #define TXFD_TXCP 0x00080000 // Transmission Completion
- #define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
- // Tx/Rx buffer descriptor structure
- struct eth_descriptor {
- u32_t status1;
- u8_t *buf;
- u32_t status2;
- struct eth_descriptor *next;
- };
- #endif /* _NUC472_ETH_ */
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