nuc472_eth.h 5.8 KB

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  1. /*
  2. * Copyright (c) 2013 Nuvoton Technology Corp.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. * Description: NUC472 EMAC driver header file
  23. */
  24. #include "lwip/def.h"
  25. #include "lwip/pbuf.h"
  26. #include "NUC472_442.h"
  27. #ifndef _NUC472_ETH_
  28. #define _NUC472_ETH_
  29. /* Generic MII registers. */
  30. #define MII_BMCR 0x00 /* Basic mode control register */
  31. #define MII_BMSR 0x01 /* Basic mode status register */
  32. #define MII_PHYSID1 0x02 /* PHYS ID 1 */
  33. #define MII_PHYSID2 0x03 /* PHYS ID 2 */
  34. #define MII_ADVERTISE 0x04 /* Advertisement control reg */
  35. #define MII_LPA 0x05 /* Link partner ability reg */
  36. #define MII_EXPANSION 0x06 /* Expansion register */
  37. #define MII_DCOUNTER 0x12 /* Disconnect counter */
  38. #define MII_FCSCOUNTER 0x13 /* False carrier counter */
  39. #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
  40. #define MII_RERRCOUNTER 0x15 /* Receive error counter */
  41. #define MII_SREVISION 0x16 /* Silicon revision */
  42. #define MII_RESV1 0x17 /* Reserved... */
  43. #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
  44. #define MII_PHYADDR 0x19 /* PHY address */
  45. #define MII_RESV2 0x1a /* Reserved... */
  46. #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
  47. #define MII_NCONFIG 0x1c /* Network interface config */
  48. /* Basic mode control register. */
  49. #define BMCR_RESV 0x007f /* Unused... */
  50. #define BMCR_CTST 0x0080 /* Collision test */
  51. #define BMCR_FULLDPLX 0x0100 /* Full duplex */
  52. #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
  53. #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
  54. #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
  55. #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
  56. #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
  57. #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
  58. #define BMCR_RESET 0x8000 /* Reset the DP83840 */
  59. /* Basic mode status register. */
  60. #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
  61. #define BMSR_JCD 0x0002 /* Jabber detected */
  62. #define BMSR_LSTATUS 0x0004 /* Link status */
  63. #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
  64. #define BMSR_RFAULT 0x0010 /* Remote fault detected */
  65. #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
  66. #define BMSR_RESV 0x07c0 /* Unused... */
  67. #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
  68. #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
  69. #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
  70. #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
  71. #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
  72. /* Advertisement control register. */
  73. #define ADVERTISE_SLCT 0x001f /* Selector bits */
  74. #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
  75. #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
  76. #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
  77. #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
  78. #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
  79. #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
  80. #define ADVERTISE_RESV 0x1c00 /* Unused... */
  81. #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
  82. #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
  83. #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
  84. #define RX_DESCRIPTOR_NUM 4 // Max Number of Rx Frame Descriptors
  85. #define TX_DESCRIPTOR_NUM 2 // Max number of Tx Frame Descriptors
  86. #define PACKET_BUFFER_SIZE 1520
  87. #define CONFIG_PHY_ADDR 1
  88. // Frame Descriptor's Owner bit
  89. #define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
  90. //#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
  91. // Rx Frame Descriptor Status
  92. #define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
  93. #define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
  94. // Tx Frame Descriptor's Control bits
  95. #define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
  96. #define TXFD_INTEN 0x04 // Interrupt Enable
  97. #define TXFD_CRCAPP 0x02 // Append CRC
  98. #define TXFD_PADEN 0x01 // Padding Enable
  99. // Tx Frame Descriptor Status
  100. #define TXFD_TXCP 0x00080000 // Transmission Completion
  101. #define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
  102. // Tx/Rx buffer descriptor structure
  103. struct eth_descriptor {
  104. u32_t status1;
  105. u8_t *buf;
  106. u32_t status2;
  107. struct eth_descriptor *next;
  108. };
  109. #endif /* _NUC472_ETH_ */