sdadc.c 9.9 KB

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  1. /**
  2. * \file
  3. *
  4. * \brief SAM Sigma-Delta Analog-to-Digital Converter (SDADC) Driver
  5. *
  6. * Copyright (C) 2015 Atmel Corporation. All rights reserved.
  7. *
  8. * \asf_license_start
  9. *
  10. * \page License
  11. *
  12. * Redistribution and use in source and binary forms, with or without
  13. * modification, are permitted provided that the following conditions are met:
  14. *
  15. * 1. Redistributions of source code must retain the above copyright notice,
  16. * this list of conditions and the following disclaimer.
  17. *
  18. * 2. Redistributions in binary form must reproduce the above copyright notice,
  19. * this list of conditions and the following disclaimer in the documentation
  20. * and/or other materials provided with the distribution.
  21. *
  22. * 3. The name of Atmel may not be used to endorse or promote products derived
  23. * from this software without specific prior written permission.
  24. *
  25. * 4. This software may only be redistributed and used in connection with an
  26. * Atmel microcontroller product.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
  29. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  30. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  31. * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
  32. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. *
  40. * \asf_license_stop
  41. *
  42. */
  43. /*
  44. * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
  45. */
  46. #include "sdadc.h"
  47. /**
  48. * \internal Configure MUX settings for the analog pins
  49. *
  50. * This function will set the given SDADC input pins
  51. * to the analog function in the pinmux, giving
  52. * the SDADC access to the analog signal
  53. *
  54. * \param [in] pin AINxx pin to configure
  55. */
  56. static inline void _sdadc_configure_ain_pin(uint32_t pin)
  57. {
  58. /* Pinmapping table for AINxx -> GPIO pin number */
  59. const uint32_t pinmapping[] = {
  60. #if (SAMC21E)
  61. PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
  62. #elif (SAMC21G)
  63. PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
  64. PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
  65. #elif (SAMC21J)
  66. PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
  67. PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
  68. PIN_PB06B_SDADC_INN2, PIN_PB07B_SDADC_INP2,
  69. #else
  70. # error SDADC pin mappings are not defined for this device.
  71. #endif
  72. };
  73. uint32_t pin_map_result;
  74. struct system_pinmux_config config;
  75. system_pinmux_get_config_defaults(&config);
  76. config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
  77. config.mux_position = 1;
  78. pin_map_result = pinmapping[pin * 2];
  79. system_pinmux_pin_set_config(pin_map_result, &config);
  80. pin_map_result = pinmapping[pin * 2 + 1];
  81. system_pinmux_pin_set_config(pin_map_result, &config);
  82. }
  83. /**
  84. * \internal Writes an SDADC configuration to the hardware module
  85. *
  86. * Writes out a given SDADC module configuration to the hardware module.
  87. *
  88. * \param[out] module_inst Pointer to the SDADC software instance struct
  89. * \param[in] config Pointer to configuration struct
  90. *
  91. * \return Status of the configuration procedure.
  92. * \retval STATUS_OK The configuration was successful
  93. * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
  94. */
  95. static enum status_code _sdadc_set_config(
  96. struct sdadc_module *const module_inst,
  97. struct sdadc_config *const config)
  98. {
  99. /* Get the hardware module pointer */
  100. Sdadc *const sdadc_module = module_inst->hw;
  101. /* Configure GCLK channel and enable clock */
  102. struct system_gclk_chan_config gclk_chan_conf;
  103. system_gclk_chan_get_config_defaults(&gclk_chan_conf);
  104. gclk_chan_conf.source_generator = config->clock_source;
  105. system_gclk_chan_set_config(SDADC_GCLK_ID, &gclk_chan_conf);
  106. system_gclk_chan_enable(SDADC_GCLK_ID);
  107. /* Setup pinmuxing for analog inputs */
  108. _sdadc_configure_ain_pin(config->mux_input);
  109. /* Configure run in standby */
  110. sdadc_module->CTRLA.reg = (config->run_in_standby << SDADC_CTRLA_RUNSTDBY_Pos)
  111. | (config->on_command << SDADC_CTRLA_ONDEMAND_Pos);
  112. while (sdadc_is_syncing(module_inst)) {
  113. /* Wait for synchronization */
  114. }
  115. /* Configure reference */
  116. sdadc_module->REFCTRL.reg = (config->reference.ref_sel) | (config->reference.ref_range) |
  117. (config->reference.on_ref_buffer << SDADC_REFCTRL_ONREFBUF_Pos);
  118. /* Configure CTRLB */
  119. sdadc_module->CTRLB.reg =
  120. (config->skip_count << SDADC_CTRLB_SKPCNT_Pos) |
  121. (config->clock_prescaler / 2 - 1) | config->osr;
  122. while (sdadc_is_syncing(module_inst)) {
  123. /* Wait for synchronization */
  124. }
  125. /* Configure CTRLC */
  126. sdadc_module->CTRLC.reg =
  127. (config->freerunning << SDADC_CTRLC_FREERUN_Pos);
  128. /* Configure SEQCTRL */
  129. sdadc_module->SEQCTRL.reg =
  130. (config->seq_enable[0]) | (config->seq_enable[1] << 1) | (config->seq_enable[2] << 2);
  131. /* Check validity of window thresholds */
  132. if (config->window.window_mode != SDADC_WINDOW_MODE_DISABLE) {
  133. if (config->window.window_lower_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
  134. config->window.window_lower_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1) ||
  135. config->window.window_upper_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
  136. config->window.window_upper_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1)) {
  137. /* Invalid value */
  138. return STATUS_ERR_INVALID_ARG;
  139. } else if (config->window.window_lower_value > (int32_t)SDADC_RESULT_RESULT_Msk ||
  140. config->window.window_upper_value > (int32_t)SDADC_RESULT_RESULT_Msk){
  141. /* Invalid value */
  142. return STATUS_ERR_INVALID_ARG;
  143. }
  144. }
  145. while (sdadc_is_syncing(module_inst)) {
  146. /* Wait for synchronization */
  147. }
  148. /* Configure window mode */
  149. sdadc_module->WINCTRL.reg = config->window.window_mode;
  150. while (sdadc_is_syncing(module_inst)) {
  151. /* Wait for synchronization */
  152. }
  153. /* Configure lower threshold */
  154. sdadc_module->WINLT.reg =
  155. config->window.window_lower_value << SDADC_WINLT_WINLT_Pos;
  156. while (sdadc_is_syncing(module_inst)) {
  157. /* Wait for synchronization */
  158. }
  159. /* Configure lower threshold */
  160. sdadc_module->WINUT.reg = config->window.window_upper_value <<
  161. SDADC_WINUT_WINUT_Pos;
  162. while (sdadc_is_syncing(module_inst)) {
  163. /* Wait for synchronization */
  164. }
  165. /* Configure pin scan mode and positive and negative input pins */
  166. sdadc_module->INPUTCTRL.reg = config->mux_input;
  167. /* Configure events */
  168. sdadc_module->EVCTRL.reg = config->event_action;
  169. /* Disable all interrupts */
  170. sdadc_module->INTENCLR.reg = (1 << SDADC_INTENCLR_WINMON_Pos) |
  171. (1 << SDADC_INTENCLR_OVERRUN_Pos) | (1 << SDADC_INTENCLR_RESRDY_Pos);
  172. /* Make sure offset correction value is valid */
  173. if (config->correction.offset_correction > (int32_t)(SDADC_OFFSETCORR_MASK / 2) ||
  174. config->correction.offset_correction < - (int32_t)(SDADC_OFFSETCORR_MASK / 2 + 1)) {
  175. return STATUS_ERR_INVALID_ARG;
  176. } else {
  177. while (sdadc_is_syncing(module_inst)) {
  178. /* Wait for synchronization */
  179. }
  180. /* Set offset correction value */
  181. sdadc_module->OFFSETCORR.reg = config->correction.offset_correction <<
  182. SDADC_OFFSETCORR_OFFSETCORR_Pos;
  183. }
  184. /* Make sure gain_correction value is valid */
  185. if (config->correction.gain_correction > SDADC_GAINCORR_MASK) {
  186. return STATUS_ERR_INVALID_ARG;
  187. } else {
  188. while (sdadc_is_syncing(module_inst)) {
  189. /* Wait for synchronization */
  190. }
  191. /* Set gain correction value */
  192. sdadc_module->GAINCORR.reg = config->correction.gain_correction <<
  193. SDADC_GAINCORR_GAINCORR_Pos;
  194. }
  195. /* Make sure shift_correction value is valid */
  196. if (config->correction.shift_correction > SDADC_SHIFTCORR_MASK) {
  197. return STATUS_ERR_INVALID_ARG;
  198. } else {
  199. while (sdadc_is_syncing(module_inst)) {
  200. /* Wait for synchronization */
  201. }
  202. /* Set shift correction value */
  203. sdadc_module->SHIFTCORR.reg = config->correction.shift_correction <<
  204. SDADC_SHIFTCORR_SHIFTCORR_Pos;
  205. }
  206. return STATUS_OK;
  207. }
  208. /**
  209. * \brief Initializes the SDADC.
  210. *
  211. * Initializes the SDADC device struct and the hardware module based on the
  212. * given configuration struct values.
  213. *
  214. * \param[out] module_inst Pointer to the SDADC software instance struct
  215. * \param[in] hw Pointer to the SDADC module instance
  216. * \param[in] config Pointer to the configuration struct
  217. *
  218. * \return Status of the initialization procedure.
  219. * \retval STATUS_OK The initialization was successful
  220. * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
  221. * \retval STATUS_BUSY The module is busy with a reset operation
  222. * \retval STATUS_ERR_DENIED The module is enabled
  223. */
  224. enum status_code sdadc_init(
  225. struct sdadc_module *const module_inst,
  226. Sdadc *hw,
  227. struct sdadc_config *config)
  228. {
  229. /* Sanity check arguments */
  230. Assert(module_inst);
  231. Assert(hw);
  232. Assert(config);
  233. /* Associate the software module instance with the hardware module */
  234. module_inst->hw = hw;
  235. /* Turn on the digital interface clock */
  236. system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SDADC);
  237. if (hw->CTRLA.reg & SDADC_CTRLA_SWRST) {
  238. /* We are in the middle of a reset. Abort. */
  239. return STATUS_BUSY;
  240. }
  241. if (hw->CTRLA.reg & SDADC_CTRLA_ENABLE) {
  242. /* Module must be disabled before initialization. Abort. */
  243. return STATUS_ERR_DENIED;
  244. }
  245. /* Store the selected reference for later use */
  246. module_inst->reference = config->reference;
  247. #if SDADC_CALLBACK_MODE == true
  248. for (uint8_t i = 0; i < SDADC_CALLBACK_N; i++) {
  249. module_inst->callback[i] = NULL;
  250. };
  251. module_inst->registered_callback_mask = 0;
  252. module_inst->enabled_callback_mask = 0;
  253. module_inst->remaining_conversions = 0;
  254. module_inst->job_status = STATUS_OK;
  255. _sdadc_instances[0] = module_inst;
  256. if (config->event_action == SDADC_EVENT_ACTION_DISABLED &&
  257. !config->freerunning) {
  258. module_inst->software_trigger = true;
  259. } else {
  260. module_inst->software_trigger = false;
  261. }
  262. #endif
  263. /* Write configuration to module */
  264. return _sdadc_set_config(module_inst, config);
  265. }