drv_sdram.c 12 KB

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  1. /*
  2. * File : usart.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2009, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2017-08-17 Tanek first implementation
  13. */
  14. #include <rtthread.h>
  15. #include "stm32f4xx_hal.h"
  16. #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
  17. #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
  18. #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
  19. #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
  20. #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
  21. #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
  22. #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
  23. #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
  24. #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
  25. #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
  26. #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
  27. #define BUFFER_SIZE ((uint32_t)0x0100)
  28. #define WRITE_READ_ADDR ((uint32_t)0x0800)
  29. #define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90MHz SDRAM clock) */
  30. static FMC_SDRAM_CommandTypeDef command;
  31. static SDRAM_HandleTypeDef hsdram1;
  32. static FMC_SDRAM_TimingTypeDef SdramTiming;
  33. static void HAL_FMC_MspInit(void)
  34. {
  35. GPIO_InitTypeDef GPIO_InitStruct;
  36. /* Peripheral clock enable */
  37. __HAL_RCC_FMC_CLK_ENABLE();
  38. /* GPIO Ports Clock Enable */
  39. __HAL_RCC_GPIOD_CLK_ENABLE();
  40. __HAL_RCC_GPIOE_CLK_ENABLE();
  41. __HAL_RCC_GPIOF_CLK_ENABLE();
  42. __HAL_RCC_GPIOG_CLK_ENABLE();
  43. __HAL_RCC_GPIOH_CLK_ENABLE();
  44. __HAL_RCC_GPIOI_CLK_ENABLE();
  45. /** FMC GPIO Configuration
  46. PI9 ------> FMC_D30
  47. PI10 ------> FMC_D31
  48. PF0 ------> FMC_A0
  49. PF1 ------> FMC_A1
  50. PF2 ------> FMC_A2
  51. PF3 ------> FMC_A3
  52. PF4 ------> FMC_A4
  53. PF5 ------> FMC_A5
  54. PH2 ------> FMC_SDCKE0
  55. PH3 ------> FMC_SDNE0
  56. PH5 ------> FMC_SDNWE
  57. PF11 ------> FMC_SDNRAS
  58. PF12 ------> FMC_A6
  59. PF13 ------> FMC_A7
  60. PF14 ------> FMC_A8
  61. PF15 ------> FMC_A9
  62. PG0 ------> FMC_A10
  63. PG1 ------> FMC_A11
  64. PE7 ------> FMC_D4
  65. PE8 ------> FMC_D5
  66. PE9 ------> FMC_D6
  67. PE10 ------> FMC_D7
  68. PE11 ------> FMC_D8
  69. PE12 ------> FMC_D9
  70. PE13 ------> FMC_D10
  71. PE14 ------> FMC_D11
  72. PE15 ------> FMC_D12
  73. PH8 ------> FMC_D16
  74. PH9 ------> FMC_D17
  75. PH10 ------> FMC_D18
  76. PH11 ------> FMC_D19
  77. PH12 ------> FMC_D20
  78. PD8 ------> FMC_D13
  79. PD9 ------> FMC_D14
  80. PD10 ------> FMC_D15
  81. PD14 ------> FMC_D0
  82. PD15 ------> FMC_D1
  83. PG4 ------> FMC_BA0
  84. PG5 ------> FMC_BA1
  85. PG8 ------> FMC_SDCLK
  86. PH13 ------> FMC_D21
  87. PH14 ------> FMC_D22
  88. PH15 ------> FMC_D23
  89. PI0 ------> FMC_D24
  90. PI1 ------> FMC_D25
  91. PI2 ------> FMC_D26
  92. PI3 ------> FMC_D27
  93. PD0 ------> FMC_D2
  94. PD1 ------> FMC_D3
  95. PG15 ------> FMC_SDNCAS
  96. PE0 ------> FMC_NBL0
  97. PE1 ------> FMC_NBL1
  98. PI4 ------> FMC_NBL2
  99. PI5 ------> FMC_NBL3
  100. PI6 ------> FMC_D28
  101. PI7 ------> FMC_D29
  102. */
  103. GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1
  104. |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5
  105. |GPIO_PIN_6|GPIO_PIN_7;
  106. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  107. GPIO_InitStruct.Pull = GPIO_NOPULL;
  108. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  109. GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  110. HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
  111. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
  112. |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
  113. |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
  114. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  115. GPIO_InitStruct.Pull = GPIO_NOPULL;
  116. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  117. GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  118. HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
  119. GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_8
  120. |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12
  121. |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
  122. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  123. GPIO_InitStruct.Pull = GPIO_NOPULL;
  124. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  125. GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  126. HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
  127. GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5
  128. |GPIO_PIN_8|GPIO_PIN_15;
  129. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  130. GPIO_InitStruct.Pull = GPIO_NOPULL;
  131. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  132. GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  133. HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
  134. GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
  135. |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
  136. |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
  137. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  138. GPIO_InitStruct.Pull = GPIO_NOPULL;
  139. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  140. GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  141. HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
  142. GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
  143. |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
  144. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  145. GPIO_InitStruct.Pull = GPIO_NOPULL;
  146. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  147. GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  148. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  149. }
  150. void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
  151. HAL_FMC_MspInit();
  152. }
  153. static void HAL_FMC_MspDeInit(void)
  154. {
  155. /* Peripheral clock enable */
  156. __HAL_RCC_FMC_CLK_DISABLE();
  157. /** FMC GPIO Configuration
  158. PI9 ------> FMC_D30
  159. PI10 ------> FMC_D31
  160. PF0 ------> FMC_A0
  161. PF1 ------> FMC_A1
  162. PF2 ------> FMC_A2
  163. PF3 ------> FMC_A3
  164. PF4 ------> FMC_A4
  165. PF5 ------> FMC_A5
  166. PH2 ------> FMC_SDCKE0
  167. PH3 ------> FMC_SDNE0
  168. PH5 ------> FMC_SDNWE
  169. PF11 ------> FMC_SDNRAS
  170. PF12 ------> FMC_A6
  171. PF13 ------> FMC_A7
  172. PF14 ------> FMC_A8
  173. PF15 ------> FMC_A9
  174. PG0 ------> FMC_A10
  175. PG1 ------> FMC_A11
  176. PE7 ------> FMC_D4
  177. PE8 ------> FMC_D5
  178. PE9 ------> FMC_D6
  179. PE10 ------> FMC_D7
  180. PE11 ------> FMC_D8
  181. PE12 ------> FMC_D9
  182. PE13 ------> FMC_D10
  183. PE14 ------> FMC_D11
  184. PE15 ------> FMC_D12
  185. PH8 ------> FMC_D16
  186. PH9 ------> FMC_D17
  187. PH10 ------> FMC_D18
  188. PH11 ------> FMC_D19
  189. PH12 ------> FMC_D20
  190. PD8 ------> FMC_D13
  191. PD9 ------> FMC_D14
  192. PD10 ------> FMC_D15
  193. PD14 ------> FMC_D0
  194. PD15 ------> FMC_D1
  195. PG4 ------> FMC_BA0
  196. PG5 ------> FMC_BA1
  197. PG8 ------> FMC_SDCLK
  198. PH13 ------> FMC_D21
  199. PH14 ------> FMC_D22
  200. PH15 ------> FMC_D23
  201. PI0 ------> FMC_D24
  202. PI1 ------> FMC_D25
  203. PI2 ------> FMC_D26
  204. PI3 ------> FMC_D27
  205. PD0 ------> FMC_D2
  206. PD1 ------> FMC_D3
  207. PG15 ------> FMC_SDNCAS
  208. PE0 ------> FMC_NBL0
  209. PE1 ------> FMC_NBL1
  210. PI4 ------> FMC_NBL2
  211. PI5 ------> FMC_NBL3
  212. PI6 ------> FMC_D28
  213. PI7 ------> FMC_D29
  214. */
  215. HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1
  216. |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5
  217. |GPIO_PIN_6|GPIO_PIN_7);
  218. HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
  219. |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
  220. |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
  221. HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_8
  222. |GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12
  223. |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
  224. HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5
  225. |GPIO_PIN_8|GPIO_PIN_15);
  226. HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
  227. |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
  228. |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
  229. HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
  230. |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
  231. }
  232. void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram)
  233. {
  234. HAL_FMC_MspDeInit();
  235. }
  236. /**
  237. * @brief Perform the SDRAM exernal memory inialization sequence
  238. * @param hsdram: SDRAM handle
  239. * @param Command: Pointer to SDRAM command structure
  240. * @retval None
  241. */
  242. static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
  243. {
  244. __IO uint32_t tmpmrd =0;
  245. /* Step 3: Configure a clock configuration enable command */
  246. Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
  247. Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
  248. Command->AutoRefreshNumber = 1;
  249. Command->ModeRegisterDefinition = 0;
  250. /* Send the command */
  251. HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
  252. /* Step 4: Insert 100 ms delay */
  253. //HAL_Delay(100);
  254. for (tmpmrd = 0; tmpmrd < 0xfffff; tmpmrd ++)
  255. ;
  256. /* Step 5: Configure a PALL (precharge all) command */
  257. Command->CommandMode = FMC_SDRAM_CMD_PALL;
  258. Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
  259. Command->AutoRefreshNumber = 1;
  260. Command->ModeRegisterDefinition = 0;
  261. /* Send the command */
  262. HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
  263. /* Step 6 : Configure a Auto-Refresh command */
  264. Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
  265. Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
  266. Command->AutoRefreshNumber = 8;
  267. Command->ModeRegisterDefinition = 0;
  268. /* Send the command */
  269. HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
  270. /* Step 7: Program the external memory mode register */
  271. tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
  272. SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
  273. SDRAM_MODEREG_CAS_LATENCY_3 |
  274. SDRAM_MODEREG_OPERATING_MODE_STANDARD |
  275. SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
  276. Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
  277. Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
  278. Command->AutoRefreshNumber = 1;
  279. Command->ModeRegisterDefinition = tmpmrd;
  280. /* Send the command */
  281. HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
  282. /* Step 8: Set the refresh rate counter */
  283. /* (15.62 us x Freq) - 20 */
  284. /* Set the device refresh counter */
  285. HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
  286. }
  287. int stm32_hw_0_sdram_init(void)
  288. {
  289. /** Perform the SDRAM1 memory initialization sequence
  290. */
  291. hsdram1.Instance = FMC_SDRAM_DEVICE;
  292. /* hsdram1.Init */
  293. hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
  294. hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
  295. hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
  296. hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
  297. hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
  298. hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
  299. hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
  300. hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
  301. hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
  302. hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
  303. /* SdramTiming */
  304. SdramTiming.LoadToActiveDelay = 2;
  305. SdramTiming.ExitSelfRefreshDelay = 7;
  306. SdramTiming.SelfRefreshTime = 2;
  307. SdramTiming.RowCycleDelay = 4;
  308. SdramTiming.WriteRecoveryTime = 2;
  309. SdramTiming.RPDelay = 2;
  310. SdramTiming.RCDDelay = 2;
  311. if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
  312. {
  313. RT_ASSERT(RT_NULL);
  314. }
  315. SDRAM_Initialization_Sequence(&hsdram1, &command);
  316. return 0;
  317. }
  318. INIT_BOARD_EXPORT(stm32_hw_0_sdram_init);