stm32f7xx_hal_qspi.c 75 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_hal_qspi.c
  4. * @author MCD Application Team
  5. * @brief QSPI HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the QuadSPI interface (QSPI).
  8. * + Initialization and de-initialization functions
  9. * + Indirect functional mode management
  10. * + Memory-mapped functional mode management
  11. * + Auto-polling functional mode management
  12. * + Interrupts and flags management
  13. * + DMA channel configuration for indirect functional mode
  14. * + Errors management and abort functionality
  15. *
  16. *
  17. @verbatim
  18. ===============================================================================
  19. ##### How to use this driver #####
  20. ===============================================================================
  21. [..]
  22. *** Initialization ***
  23. ======================
  24. [..]
  25. (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
  26. (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
  27. (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
  28. (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
  29. (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
  30. (++) If interrupt mode is used, enable and configure QuadSPI global
  31. interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
  32. (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
  33. with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
  34. link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
  35. DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
  36. (#) Configure the flash size, the clock prescaler, the fifo threshold, the
  37. clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
  38. *** Indirect functional mode ***
  39. ================================
  40. [..]
  41. (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
  42. functions :
  43. (++) Instruction phase : the mode used and if present the instruction opcode.
  44. (++) Address phase : the mode used and if present the size and the address value.
  45. (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  46. bytes values.
  47. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  48. (++) Data phase : the mode used and if present the number of bytes.
  49. (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  50. if activated.
  51. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  52. (#) If no data is required for the command, it is sent directly to the memory :
  53. (++) In polling mode, the output of the function is done when the transfer is complete.
  54. (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
  55. (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
  56. HAL_QSPI_Transmit_IT() after the command configuration :
  57. (++) In polling mode, the output of the function is done when the transfer is complete.
  58. (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
  59. is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
  60. (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
  61. HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
  62. (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
  63. HAL_QSPI_Receive_IT() after the command configuration :
  64. (++) In polling mode, the output of the function is done when the transfer is complete.
  65. (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
  66. is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
  67. (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
  68. HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
  69. *** Auto-polling functional mode ***
  70. ====================================
  71. [..]
  72. (#) Configure the command sequence and the auto-polling functional mode using the
  73. HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
  74. (++) Instruction phase : the mode used and if present the instruction opcode.
  75. (++) Address phase : the mode used and if present the size and the address value.
  76. (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  77. bytes values.
  78. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  79. (++) Data phase : the mode used.
  80. (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  81. if activated.
  82. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  83. (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
  84. the polling interval and the automatic stop activation.
  85. (#) After the configuration :
  86. (++) In polling mode, the output of the function is done when the status match is reached. The
  87. automatic stop is activated to avoid an infinite loop.
  88. (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
  89. *** Memory-mapped functional mode ***
  90. =====================================
  91. [..]
  92. (#) Configure the command sequence and the memory-mapped functional mode using the
  93. HAL_QSPI_MemoryMapped() functions :
  94. (++) Instruction phase : the mode used and if present the instruction opcode.
  95. (++) Address phase : the mode used and the size.
  96. (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  97. bytes values.
  98. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  99. (++) Data phase : the mode used.
  100. (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  101. if activated.
  102. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  103. (++) The timeout activation and the timeout period.
  104. (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
  105. the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
  106. *** Errors management and abort functionality ***
  107. ==================================================
  108. [..]
  109. (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
  110. (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
  111. flushes the fifo :
  112. (++) In polling mode, the output of the function is done when the transfer
  113. complete bit is set and the busy bit cleared.
  114. (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
  115. the transfer complete bi is set.
  116. *** Control functions ***
  117. =========================
  118. [..]
  119. (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
  120. (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
  121. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
  122. (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
  123. *** Workarounds linked to Silicon Limitation ***
  124. ====================================================
  125. [..]
  126. (#) Workarounds Implemented inside HAL Driver
  127. (++) Extra data written in the FIFO at the end of a read transfer
  128. @endverbatim
  129. ******************************************************************************
  130. * @attention
  131. *
  132. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  133. *
  134. * Redistribution and use in source and binary forms, with or without modification,
  135. * are permitted provided that the following conditions are met:
  136. * 1. Redistributions of source code must retain the above copyright notice,
  137. * this list of conditions and the following disclaimer.
  138. * 2. Redistributions in binary form must reproduce the above copyright notice,
  139. * this list of conditions and the following disclaimer in the documentation
  140. * and/or other materials provided with the distribution.
  141. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  142. * may be used to endorse or promote products derived from this software
  143. * without specific prior written permission.
  144. *
  145. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  146. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  147. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  148. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  149. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  150. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  151. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  152. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  153. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  154. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  155. *
  156. ******************************************************************************
  157. */
  158. /* Includes ------------------------------------------------------------------*/
  159. #include "stm32f7xx_hal.h"
  160. /** @addtogroup STM32F7xx_HAL_Driver
  161. * @{
  162. */
  163. /** @defgroup QSPI QSPI
  164. * @brief HAL QSPI module driver
  165. * @{
  166. */
  167. #ifdef HAL_QSPI_MODULE_ENABLED
  168. /* Private typedef -----------------------------------------------------------*/
  169. /* Private define ------------------------------------------------------------*/
  170. /** @addtogroup QSPI_Private_Constants
  171. * @{
  172. */
  173. #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U) /*!<Indirect write mode*/
  174. #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
  175. #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
  176. #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
  177. /**
  178. * @}
  179. */
  180. /* Private macro -------------------------------------------------------------*/
  181. /** @addtogroup QSPI_Private_Macros QSPI Private Macros
  182. * @{
  183. */
  184. #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
  185. ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
  186. ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
  187. ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
  188. /**
  189. * @}
  190. */
  191. /* Private variables ---------------------------------------------------------*/
  192. /* Private function prototypes -----------------------------------------------*/
  193. /** @addtogroup QSPI_Private_Functions QSPI Private Functions
  194. * @{
  195. */
  196. static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
  197. static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
  198. static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
  199. static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
  200. static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
  201. static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
  202. static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
  203. static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
  204. /**
  205. * @}
  206. */
  207. /* Exported functions ---------------------------------------------------------*/
  208. /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
  209. * @{
  210. */
  211. /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
  212. * @brief Initialization and Configuration functions
  213. *
  214. @verbatim
  215. ===============================================================================
  216. ##### Initialization and Configuration functions #####
  217. ===============================================================================
  218. [..]
  219. This subsection provides a set of functions allowing to :
  220. (+) Initialize the QuadSPI.
  221. (+) De-initialize the QuadSPI.
  222. @endverbatim
  223. * @{
  224. */
  225. /**
  226. * @brief Initializes the QSPI mode according to the specified parameters
  227. * in the QSPI_InitTypeDef and creates the associated handle.
  228. * @param hqspi qspi handle
  229. * @retval HAL status
  230. */
  231. HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
  232. {
  233. HAL_StatusTypeDef status = HAL_ERROR;
  234. uint32_t tickstart = HAL_GetTick();
  235. /* Check the QSPI handle allocation */
  236. if(hqspi == NULL)
  237. {
  238. return HAL_ERROR;
  239. }
  240. /* Check the parameters */
  241. assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
  242. assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
  243. assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
  244. assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
  245. assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
  246. assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
  247. assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
  248. assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
  249. if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
  250. {
  251. assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
  252. }
  253. /* Process locked */
  254. __HAL_LOCK(hqspi);
  255. if(hqspi->State == HAL_QSPI_STATE_RESET)
  256. {
  257. /* Allocate lock resource and initialize it */
  258. hqspi->Lock = HAL_UNLOCKED;
  259. /* Init the low level hardware : GPIO, CLOCK */
  260. HAL_QSPI_MspInit(hqspi);
  261. /* Configure the default timeout for the QSPI memory access */
  262. HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
  263. }
  264. /* Configure QSPI FIFO Threshold */
  265. MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
  266. /* Wait till BUSY flag reset */
  267. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  268. if(status == HAL_OK)
  269. {
  270. /* Configure QSPI Clock Prescaler and Sample Shift */
  271. MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
  272. /* Configure QSPI Flash Size, CS High Time and Clock Mode */
  273. MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
  274. ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
  275. /* Enable the QSPI peripheral */
  276. __HAL_QSPI_ENABLE(hqspi);
  277. /* Set QSPI error code to none */
  278. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  279. /* Initialize the QSPI state */
  280. hqspi->State = HAL_QSPI_STATE_READY;
  281. }
  282. /* Release Lock */
  283. __HAL_UNLOCK(hqspi);
  284. /* Return function status */
  285. return status;
  286. }
  287. /**
  288. * @brief DeInitializes the QSPI peripheral
  289. * @param hqspi qspi handle
  290. * @retval HAL status
  291. */
  292. HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
  293. {
  294. /* Check the QSPI handle allocation */
  295. if(hqspi == NULL)
  296. {
  297. return HAL_ERROR;
  298. }
  299. /* Process locked */
  300. __HAL_LOCK(hqspi);
  301. /* Disable the QSPI Peripheral Clock */
  302. __HAL_QSPI_DISABLE(hqspi);
  303. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  304. HAL_QSPI_MspDeInit(hqspi);
  305. /* Set QSPI error code to none */
  306. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  307. /* Initialize the QSPI state */
  308. hqspi->State = HAL_QSPI_STATE_RESET;
  309. /* Release Lock */
  310. __HAL_UNLOCK(hqspi);
  311. return HAL_OK;
  312. }
  313. /**
  314. * @brief QSPI MSP Init
  315. * @param hqspi QSPI handle
  316. * @retval None
  317. */
  318. __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
  319. {
  320. /* Prevent unused argument(s) compilation warning */
  321. UNUSED(hqspi);
  322. /* NOTE : This function should not be modified, when the callback is needed,
  323. the HAL_QSPI_MspInit can be implemented in the user file
  324. */
  325. }
  326. /**
  327. * @brief QSPI MSP DeInit
  328. * @param hqspi QSPI handle
  329. * @retval None
  330. */
  331. __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
  332. {
  333. /* Prevent unused argument(s) compilation warning */
  334. UNUSED(hqspi);
  335. /* NOTE : This function should not be modified, when the callback is needed,
  336. the HAL_QSPI_MspDeInit can be implemented in the user file
  337. */
  338. }
  339. /**
  340. * @}
  341. */
  342. /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
  343. * @brief QSPI Transmit/Receive functions
  344. *
  345. @verbatim
  346. ===============================================================================
  347. ##### IO operation functions #####
  348. ===============================================================================
  349. [..]
  350. This subsection provides a set of functions allowing to :
  351. (+) Handle the interrupts.
  352. (+) Handle the command sequence.
  353. (+) Transmit data in blocking, interrupt or DMA mode.
  354. (+) Receive data in blocking, interrupt or DMA mode.
  355. (+) Manage the auto-polling functional mode.
  356. (+) Manage the memory-mapped functional mode.
  357. @endverbatim
  358. * @{
  359. */
  360. /**
  361. * @brief This function handles QSPI interrupt request.
  362. * @param hqspi QSPI handle
  363. * @retval None.
  364. */
  365. void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
  366. {
  367. __IO uint32_t *data_reg;
  368. uint32_t flag = READ_REG(hqspi->Instance->SR);
  369. uint32_t itsource = READ_REG(hqspi->Instance->CR);
  370. /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
  371. if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
  372. {
  373. data_reg = &hqspi->Instance->DR;
  374. if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
  375. {
  376. /* Transmission process */
  377. while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
  378. {
  379. if (hqspi->TxXferCount > 0)
  380. {
  381. /* Fill the FIFO until it is full */
  382. *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
  383. hqspi->TxXferCount--;
  384. }
  385. else
  386. {
  387. /* No more data available for the transfer */
  388. /* Disable the QSPI FIFO Threshold Interrupt */
  389. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
  390. break;
  391. }
  392. }
  393. }
  394. else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
  395. {
  396. /* Receiving Process */
  397. while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
  398. {
  399. if (hqspi->RxXferCount > 0)
  400. {
  401. /* Read the FIFO until it is empty */
  402. *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
  403. hqspi->RxXferCount--;
  404. }
  405. else
  406. {
  407. /* All data have been received for the transfer */
  408. /* Disable the QSPI FIFO Threshold Interrupt */
  409. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
  410. break;
  411. }
  412. }
  413. }
  414. /* FIFO Threshold callback */
  415. HAL_QSPI_FifoThresholdCallback(hqspi);
  416. }
  417. /* QSPI Transfer Complete interrupt occurred -------------------------------*/
  418. else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
  419. {
  420. /* Clear interrupt */
  421. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
  422. /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
  423. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
  424. /* Transfer complete callback */
  425. if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
  426. {
  427. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
  428. {
  429. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  430. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  431. /* Disable the DMA channel */
  432. __HAL_DMA_DISABLE(hqspi->hdma);
  433. }
  434. #if defined(QSPI1_V1_0)
  435. /* Clear Busy bit */
  436. HAL_QSPI_Abort_IT(hqspi);
  437. #endif
  438. /* Change state of QSPI */
  439. hqspi->State = HAL_QSPI_STATE_READY;
  440. /* TX Complete callback */
  441. HAL_QSPI_TxCpltCallback(hqspi);
  442. }
  443. else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
  444. {
  445. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
  446. {
  447. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  448. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  449. /* Disable the DMA channel */
  450. __HAL_DMA_DISABLE(hqspi->hdma);
  451. }
  452. else
  453. {
  454. data_reg = &hqspi->Instance->DR;
  455. while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
  456. {
  457. if (hqspi->RxXferCount > 0)
  458. {
  459. /* Read the last data received in the FIFO until it is empty */
  460. *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
  461. hqspi->RxXferCount--;
  462. }
  463. else
  464. {
  465. /* All data have been received for the transfer */
  466. break;
  467. }
  468. }
  469. }
  470. #if defined(QSPI1_V1_0)
  471. /* Workaround - Extra data written in the FIFO at the end of a read transfer */
  472. HAL_QSPI_Abort_IT(hqspi);
  473. #endif /* QSPI_V1_0*/
  474. /* Change state of QSPI */
  475. hqspi->State = HAL_QSPI_STATE_READY;
  476. /* RX Complete callback */
  477. HAL_QSPI_RxCpltCallback(hqspi);
  478. }
  479. else if(hqspi->State == HAL_QSPI_STATE_BUSY)
  480. {
  481. /* Change state of QSPI */
  482. hqspi->State = HAL_QSPI_STATE_READY;
  483. /* Command Complete callback */
  484. HAL_QSPI_CmdCpltCallback(hqspi);
  485. }
  486. else if(hqspi->State == HAL_QSPI_STATE_ABORT)
  487. {
  488. /* Change state of QSPI */
  489. hqspi->State = HAL_QSPI_STATE_READY;
  490. if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
  491. {
  492. /* Abort called by the user */
  493. /* Abort Complete callback */
  494. HAL_QSPI_AbortCpltCallback(hqspi);
  495. }
  496. else
  497. {
  498. /* Abort due to an error (eg : DMA error) */
  499. /* Error callback */
  500. HAL_QSPI_ErrorCallback(hqspi);
  501. }
  502. }
  503. }
  504. /* QSPI Status Match interrupt occurred ------------------------------------*/
  505. else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
  506. {
  507. /* Clear interrupt */
  508. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
  509. /* Check if the automatic poll mode stop is activated */
  510. if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
  511. {
  512. /* Disable the QSPI Transfer Error and Status Match Interrupts */
  513. __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
  514. /* Change state of QSPI */
  515. hqspi->State = HAL_QSPI_STATE_READY;
  516. }
  517. /* Status match callback */
  518. HAL_QSPI_StatusMatchCallback(hqspi);
  519. }
  520. /* QSPI Transfer Error interrupt occurred ----------------------------------*/
  521. else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
  522. {
  523. /* Clear interrupt */
  524. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
  525. /* Disable all the QSPI Interrupts */
  526. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
  527. /* Set error code */
  528. hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
  529. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
  530. {
  531. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  532. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  533. /* Disable the DMA channel */
  534. hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
  535. HAL_DMA_Abort_IT(hqspi->hdma);
  536. }
  537. else
  538. {
  539. /* Change state of QSPI */
  540. hqspi->State = HAL_QSPI_STATE_READY;
  541. /* Error callback */
  542. HAL_QSPI_ErrorCallback(hqspi);
  543. }
  544. }
  545. /* QSPI Timeout interrupt occurred -----------------------------------------*/
  546. else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
  547. {
  548. /* Clear interrupt */
  549. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
  550. /* Time out callback */
  551. HAL_QSPI_TimeOutCallback(hqspi);
  552. }
  553. }
  554. /**
  555. * @brief Sets the command configuration.
  556. * @param hqspi QSPI handle
  557. * @param cmd structure that contains the command configuration information
  558. * @param Timeout Time out duration
  559. * @note This function is used only in Indirect Read or Write Modes
  560. * @retval HAL status
  561. */
  562. HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
  563. {
  564. HAL_StatusTypeDef status = HAL_ERROR;
  565. uint32_t tickstart = HAL_GetTick();
  566. /* Check the parameters */
  567. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  568. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  569. {
  570. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  571. }
  572. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  573. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  574. {
  575. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  576. }
  577. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  578. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  579. {
  580. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  581. }
  582. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  583. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  584. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  585. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  586. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  587. /* Process locked */
  588. __HAL_LOCK(hqspi);
  589. if(hqspi->State == HAL_QSPI_STATE_READY)
  590. {
  591. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  592. /* Update QSPI state */
  593. hqspi->State = HAL_QSPI_STATE_BUSY;
  594. /* Wait till BUSY flag reset */
  595. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
  596. if (status == HAL_OK)
  597. {
  598. /* Call the configuration function */
  599. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  600. if (cmd->DataMode == QSPI_DATA_NONE)
  601. {
  602. /* When there is no data phase, the transfer start as soon as the configuration is done
  603. so wait until TC flag is set to go back in idle state */
  604. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
  605. if (status == HAL_OK)
  606. {
  607. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  608. /* Update QSPI state */
  609. hqspi->State = HAL_QSPI_STATE_READY;
  610. }
  611. }
  612. else
  613. {
  614. /* Update QSPI state */
  615. hqspi->State = HAL_QSPI_STATE_READY;
  616. }
  617. }
  618. }
  619. else
  620. {
  621. status = HAL_BUSY;
  622. }
  623. /* Process unlocked */
  624. __HAL_UNLOCK(hqspi);
  625. /* Return function status */
  626. return status;
  627. }
  628. /**
  629. * @brief Sets the command configuration in interrupt mode.
  630. * @param hqspi QSPI handle
  631. * @param cmd structure that contains the command configuration information
  632. * @note This function is used only in Indirect Read or Write Modes
  633. * @retval HAL status
  634. */
  635. HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
  636. {
  637. HAL_StatusTypeDef status = HAL_ERROR;
  638. uint32_t tickstart = HAL_GetTick();
  639. /* Check the parameters */
  640. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  641. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  642. {
  643. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  644. }
  645. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  646. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  647. {
  648. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  649. }
  650. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  651. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  652. {
  653. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  654. }
  655. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  656. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  657. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  658. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  659. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  660. /* Process locked */
  661. __HAL_LOCK(hqspi);
  662. if(hqspi->State == HAL_QSPI_STATE_READY)
  663. {
  664. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  665. /* Update QSPI state */
  666. hqspi->State = HAL_QSPI_STATE_BUSY;
  667. /* Wait till BUSY flag reset */
  668. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  669. if (status == HAL_OK)
  670. {
  671. if (cmd->DataMode == QSPI_DATA_NONE)
  672. {
  673. /* Clear interrupt */
  674. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
  675. }
  676. /* Call the configuration function */
  677. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  678. if (cmd->DataMode == QSPI_DATA_NONE)
  679. {
  680. /* When there is no data phase, the transfer start as soon as the configuration is done
  681. so activate TC and TE interrupts */
  682. /* Process unlocked */
  683. __HAL_UNLOCK(hqspi);
  684. /* Enable the QSPI Transfer Error Interrupt */
  685. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
  686. }
  687. else
  688. {
  689. /* Update QSPI state */
  690. hqspi->State = HAL_QSPI_STATE_READY;
  691. /* Process unlocked */
  692. __HAL_UNLOCK(hqspi);
  693. }
  694. }
  695. else
  696. {
  697. /* Process unlocked */
  698. __HAL_UNLOCK(hqspi);
  699. }
  700. }
  701. else
  702. {
  703. status = HAL_BUSY;
  704. /* Process unlocked */
  705. __HAL_UNLOCK(hqspi);
  706. }
  707. /* Return function status */
  708. return status;
  709. }
  710. /**
  711. * @brief Transmit an amount of data in blocking mode.
  712. * @param hqspi QSPI handle
  713. * @param pData pointer to data buffer
  714. * @param Timeout Time out duration
  715. * @note This function is used only in Indirect Write Mode
  716. * @retval HAL status
  717. */
  718. HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
  719. {
  720. HAL_StatusTypeDef status = HAL_OK;
  721. uint32_t tickstart = HAL_GetTick();
  722. __IO uint32_t *data_reg = &hqspi->Instance->DR;
  723. /* Process locked */
  724. __HAL_LOCK(hqspi);
  725. if(hqspi->State == HAL_QSPI_STATE_READY)
  726. {
  727. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  728. if(pData != NULL )
  729. {
  730. /* Update state */
  731. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
  732. /* Configure counters and size of the handle */
  733. hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
  734. hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
  735. hqspi->pTxBuffPtr = pData;
  736. /* Configure QSPI: CCR register with functional as indirect write */
  737. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  738. while(hqspi->TxXferCount > 0)
  739. {
  740. /* Wait until FT flag is set to send data */
  741. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
  742. if (status != HAL_OK)
  743. {
  744. break;
  745. }
  746. *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
  747. hqspi->TxXferCount--;
  748. }
  749. if (status == HAL_OK)
  750. {
  751. /* Wait until TC flag is set to go back in idle state */
  752. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
  753. if (status == HAL_OK)
  754. {
  755. /* Clear Transfer Complete bit */
  756. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  757. #if defined(QSPI1_V1_0)
  758. /* Clear Busy bit */
  759. status = HAL_QSPI_Abort(hqspi);
  760. #endif /* QSPI_V1_0 */
  761. }
  762. }
  763. /* Update QSPI state */
  764. hqspi->State = HAL_QSPI_STATE_READY;
  765. }
  766. else
  767. {
  768. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  769. status = HAL_ERROR;
  770. }
  771. }
  772. else
  773. {
  774. status = HAL_BUSY;
  775. }
  776. /* Process unlocked */
  777. __HAL_UNLOCK(hqspi);
  778. return status;
  779. }
  780. /**
  781. * @brief Receive an amount of data in blocking mode
  782. * @param hqspi QSPI handle
  783. * @param pData pointer to data buffer
  784. * @param Timeout Time out duration
  785. * @note This function is used only in Indirect Read Mode
  786. * @retval HAL status
  787. */
  788. HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
  789. {
  790. HAL_StatusTypeDef status = HAL_OK;
  791. uint32_t tickstart = HAL_GetTick();
  792. uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
  793. __IO uint32_t *data_reg = &hqspi->Instance->DR;
  794. /* Process locked */
  795. __HAL_LOCK(hqspi);
  796. if(hqspi->State == HAL_QSPI_STATE_READY)
  797. {
  798. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  799. if(pData != NULL )
  800. {
  801. /* Update state */
  802. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
  803. /* Configure counters and size of the handle */
  804. hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
  805. hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
  806. hqspi->pRxBuffPtr = pData;
  807. /* Configure QSPI: CCR register with functional as indirect read */
  808. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
  809. /* Start the transfer by re-writing the address in AR register */
  810. WRITE_REG(hqspi->Instance->AR, addr_reg);
  811. while(hqspi->RxXferCount > 0)
  812. {
  813. /* Wait until FT or TC flag is set to read received data */
  814. status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
  815. if (status != HAL_OK)
  816. {
  817. break;
  818. }
  819. *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
  820. hqspi->RxXferCount--;
  821. }
  822. if (status == HAL_OK)
  823. {
  824. /* Wait until TC flag is set to go back in idle state */
  825. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
  826. if (status == HAL_OK)
  827. {
  828. /* Clear Transfer Complete bit */
  829. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  830. #if defined(QSPI1_V1_0)
  831. /* Workaround - Extra data written in the FIFO at the end of a read transfer */
  832. status = HAL_QSPI_Abort(hqspi);
  833. #endif /* QSPI_V1_0 */
  834. }
  835. }
  836. /* Update QSPI state */
  837. hqspi->State = HAL_QSPI_STATE_READY;
  838. }
  839. else
  840. {
  841. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  842. status = HAL_ERROR;
  843. }
  844. }
  845. else
  846. {
  847. status = HAL_BUSY;
  848. }
  849. /* Process unlocked */
  850. __HAL_UNLOCK(hqspi);
  851. return status;
  852. }
  853. /**
  854. * @brief Send an amount of data in interrupt mode
  855. * @param hqspi QSPI handle
  856. * @param pData pointer to data buffer
  857. * @note This function is used only in Indirect Write Mode
  858. * @retval HAL status
  859. */
  860. HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  861. {
  862. HAL_StatusTypeDef status = HAL_OK;
  863. /* Process locked */
  864. __HAL_LOCK(hqspi);
  865. if(hqspi->State == HAL_QSPI_STATE_READY)
  866. {
  867. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  868. if(pData != NULL )
  869. {
  870. /* Update state */
  871. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
  872. /* Configure counters and size of the handle */
  873. hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
  874. hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
  875. hqspi->pTxBuffPtr = pData;
  876. /* Configure QSPI: CCR register with functional as indirect write */
  877. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  878. /* Clear interrupt */
  879. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
  880. /* Process unlocked */
  881. __HAL_UNLOCK(hqspi);
  882. /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
  883. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
  884. }
  885. else
  886. {
  887. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  888. status = HAL_ERROR;
  889. /* Process unlocked */
  890. __HAL_UNLOCK(hqspi);
  891. }
  892. }
  893. else
  894. {
  895. status = HAL_BUSY;
  896. /* Process unlocked */
  897. __HAL_UNLOCK(hqspi);
  898. }
  899. return status;
  900. }
  901. /**
  902. * @brief Receive an amount of data in no-blocking mode with Interrupt
  903. * @param hqspi QSPI handle
  904. * @param pData pointer to data buffer
  905. * @note This function is used only in Indirect Read Mode
  906. * @retval HAL status
  907. */
  908. HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  909. {
  910. HAL_StatusTypeDef status = HAL_OK;
  911. uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
  912. /* Process locked */
  913. __HAL_LOCK(hqspi);
  914. if(hqspi->State == HAL_QSPI_STATE_READY)
  915. {
  916. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  917. if(pData != NULL )
  918. {
  919. /* Update state */
  920. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
  921. /* Configure counters and size of the handle */
  922. hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
  923. hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
  924. hqspi->pRxBuffPtr = pData;
  925. /* Configure QSPI: CCR register with functional as indirect read */
  926. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
  927. /* Start the transfer by re-writing the address in AR register */
  928. WRITE_REG(hqspi->Instance->AR, addr_reg);
  929. /* Clear interrupt */
  930. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
  931. /* Process unlocked */
  932. __HAL_UNLOCK(hqspi);
  933. /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
  934. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
  935. }
  936. else
  937. {
  938. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  939. status = HAL_ERROR;
  940. /* Process unlocked */
  941. __HAL_UNLOCK(hqspi);
  942. }
  943. }
  944. else
  945. {
  946. status = HAL_BUSY;
  947. /* Process unlocked */
  948. __HAL_UNLOCK(hqspi);
  949. }
  950. return status;
  951. }
  952. /**
  953. * @brief Sends an amount of data in non blocking mode with DMA.
  954. * @param hqspi QSPI handle
  955. * @param pData pointer to data buffer
  956. * @note This function is used only in Indirect Write Mode
  957. * @note If DMA peripheral access is configured as halfword, the number
  958. * of data and the fifo threshold should be aligned on halfword
  959. * @note If DMA peripheral access is configured as word, the number
  960. * of data and the fifo threshold should be aligned on word
  961. * @retval HAL status
  962. */
  963. HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  964. {
  965. HAL_StatusTypeDef status = HAL_OK;
  966. uint32_t *tmp;
  967. uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
  968. /* Process locked */
  969. __HAL_LOCK(hqspi);
  970. if(hqspi->State == HAL_QSPI_STATE_READY)
  971. {
  972. /* Clear the error code */
  973. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  974. if(pData != NULL )
  975. {
  976. /* Configure counters of the handle */
  977. if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
  978. {
  979. hqspi->TxXferCount = data_size;
  980. }
  981. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
  982. {
  983. if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
  984. {
  985. /* The number of data or the fifo threshold is not aligned on halfword
  986. => no transfer possible with DMA peripheral access configured as halfword */
  987. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  988. status = HAL_ERROR;
  989. /* Process unlocked */
  990. __HAL_UNLOCK(hqspi);
  991. }
  992. else
  993. {
  994. hqspi->TxXferCount = (data_size >> 1);
  995. }
  996. }
  997. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
  998. {
  999. if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
  1000. {
  1001. /* The number of data or the fifo threshold is not aligned on word
  1002. => no transfer possible with DMA peripheral access configured as word */
  1003. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1004. status = HAL_ERROR;
  1005. /* Process unlocked */
  1006. __HAL_UNLOCK(hqspi);
  1007. }
  1008. else
  1009. {
  1010. hqspi->TxXferCount = (data_size >> 2);
  1011. }
  1012. }
  1013. if (status == HAL_OK)
  1014. {
  1015. /* Update state */
  1016. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
  1017. /* Clear interrupt */
  1018. __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
  1019. /* Configure size and pointer of the handle */
  1020. hqspi->TxXferSize = hqspi->TxXferCount;
  1021. hqspi->pTxBuffPtr = pData;
  1022. /* Configure QSPI: CCR register with functional mode as indirect write */
  1023. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  1024. /* Set the QSPI DMA transfer complete callback */
  1025. hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
  1026. /* Set the QSPI DMA Half transfer complete callback */
  1027. hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
  1028. /* Set the DMA error callback */
  1029. hqspi->hdma->XferErrorCallback = QSPI_DMAError;
  1030. /* Clear the DMA abort callback */
  1031. hqspi->hdma->XferAbortCallback = NULL;
  1032. /* Configure the direction of the DMA */
  1033. hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
  1034. MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
  1035. /* Enable the QSPI transmit DMA Channel */
  1036. tmp = (uint32_t*)&pData;
  1037. HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
  1038. /* Process unlocked */
  1039. __HAL_UNLOCK(hqspi);
  1040. /* Enable the QSPI transfer error Interrupt */
  1041. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
  1042. /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
  1043. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1044. }
  1045. }
  1046. else
  1047. {
  1048. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1049. status = HAL_ERROR;
  1050. /* Process unlocked */
  1051. __HAL_UNLOCK(hqspi);
  1052. }
  1053. }
  1054. else
  1055. {
  1056. status = HAL_BUSY;
  1057. /* Process unlocked */
  1058. __HAL_UNLOCK(hqspi);
  1059. }
  1060. return status;
  1061. }
  1062. /**
  1063. * @brief Receives an amount of data in non blocking mode with DMA.
  1064. * @param hqspi QSPI handle
  1065. * @param pData pointer to data buffer.
  1066. * @note This function is used only in Indirect Read Mode
  1067. * @note If DMA peripheral access is configured as halfword, the number
  1068. * of data and the fifo threshold should be aligned on halfword
  1069. * @note If DMA peripheral access is configured as word, the number
  1070. * of data and the fifo threshold should be aligned on word
  1071. * @retval HAL status
  1072. */
  1073. HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  1074. {
  1075. HAL_StatusTypeDef status = HAL_OK;
  1076. uint32_t *tmp;
  1077. uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
  1078. uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
  1079. /* Process locked */
  1080. __HAL_LOCK(hqspi);
  1081. if(hqspi->State == HAL_QSPI_STATE_READY)
  1082. {
  1083. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1084. if(pData != NULL )
  1085. {
  1086. /* Configure counters of the handle */
  1087. if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
  1088. {
  1089. hqspi->RxXferCount = data_size;
  1090. }
  1091. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
  1092. {
  1093. if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
  1094. {
  1095. /* The number of data or the fifo threshold is not aligned on halfword
  1096. => no transfer possible with DMA peripheral access configured as halfword */
  1097. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1098. status = HAL_ERROR;
  1099. /* Process unlocked */
  1100. __HAL_UNLOCK(hqspi);
  1101. }
  1102. else
  1103. {
  1104. hqspi->RxXferCount = (data_size >> 1);
  1105. }
  1106. }
  1107. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
  1108. {
  1109. if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
  1110. {
  1111. /* The number of data or the fifo threshold is not aligned on word
  1112. => no transfer possible with DMA peripheral access configured as word */
  1113. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1114. status = HAL_ERROR;
  1115. /* Process unlocked */
  1116. __HAL_UNLOCK(hqspi);
  1117. }
  1118. else
  1119. {
  1120. hqspi->RxXferCount = (data_size >> 2);
  1121. }
  1122. }
  1123. if (status == HAL_OK)
  1124. {
  1125. /* Update state */
  1126. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
  1127. /* Clear interrupt */
  1128. __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
  1129. /* Configure size and pointer of the handle */
  1130. hqspi->RxXferSize = hqspi->RxXferCount;
  1131. hqspi->pRxBuffPtr = pData;
  1132. /* Set the QSPI DMA transfer complete callback */
  1133. hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
  1134. /* Set the QSPI DMA Half transfer complete callback */
  1135. hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
  1136. /* Set the DMA error callback */
  1137. hqspi->hdma->XferErrorCallback = QSPI_DMAError;
  1138. /* Clear the DMA abort callback */
  1139. hqspi->hdma->XferAbortCallback = NULL;
  1140. /* Configure the direction of the DMA */
  1141. hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
  1142. MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
  1143. /* Enable the DMA Channel */
  1144. tmp = (uint32_t*)&pData;
  1145. HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
  1146. /* Configure QSPI: CCR register with functional as indirect read */
  1147. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
  1148. /* Start the transfer by re-writing the address in AR register */
  1149. WRITE_REG(hqspi->Instance->AR, addr_reg);
  1150. /* Process unlocked */
  1151. __HAL_UNLOCK(hqspi);
  1152. /* Enable the QSPI transfer error Interrupt */
  1153. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
  1154. /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
  1155. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1156. }
  1157. }
  1158. else
  1159. {
  1160. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1161. status = HAL_ERROR;
  1162. /* Process unlocked */
  1163. __HAL_UNLOCK(hqspi);
  1164. }
  1165. }
  1166. else
  1167. {
  1168. status = HAL_BUSY;
  1169. /* Process unlocked */
  1170. __HAL_UNLOCK(hqspi);
  1171. }
  1172. return status;
  1173. }
  1174. /**
  1175. * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
  1176. * @param hqspi QSPI handle
  1177. * @param cmd structure that contains the command configuration information.
  1178. * @param cfg structure that contains the polling configuration information.
  1179. * @param Timeout Time out duration
  1180. * @note This function is used only in Automatic Polling Mode
  1181. * @retval HAL status
  1182. */
  1183. HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
  1184. {
  1185. HAL_StatusTypeDef status = HAL_ERROR;
  1186. uint32_t tickstart = HAL_GetTick();
  1187. /* Check the parameters */
  1188. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  1189. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  1190. {
  1191. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  1192. }
  1193. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  1194. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1195. {
  1196. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  1197. }
  1198. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  1199. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1200. {
  1201. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  1202. }
  1203. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  1204. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  1205. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  1206. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  1207. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  1208. assert_param(IS_QSPI_INTERVAL(cfg->Interval));
  1209. assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
  1210. assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
  1211. /* Process locked */
  1212. __HAL_LOCK(hqspi);
  1213. if(hqspi->State == HAL_QSPI_STATE_READY)
  1214. {
  1215. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1216. /* Update state */
  1217. hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
  1218. /* Wait till BUSY flag reset */
  1219. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
  1220. if (status == HAL_OK)
  1221. {
  1222. /* Configure QSPI: PSMAR register with the status match value */
  1223. WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
  1224. /* Configure QSPI: PSMKR register with the status mask value */
  1225. WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
  1226. /* Configure QSPI: PIR register with the interval value */
  1227. WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
  1228. /* Configure QSPI: CR register with Match mode and Automatic stop enabled
  1229. (otherwise there will be an infinite loop in blocking mode) */
  1230. MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
  1231. (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
  1232. /* Call the configuration function */
  1233. cmd->NbData = cfg->StatusBytesSize;
  1234. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
  1235. /* Wait until SM flag is set to go back in idle state */
  1236. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
  1237. if (status == HAL_OK)
  1238. {
  1239. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
  1240. /* Update state */
  1241. hqspi->State = HAL_QSPI_STATE_READY;
  1242. }
  1243. }
  1244. }
  1245. else
  1246. {
  1247. status = HAL_BUSY;
  1248. }
  1249. /* Process unlocked */
  1250. __HAL_UNLOCK(hqspi);
  1251. /* Return function status */
  1252. return status;
  1253. }
  1254. /**
  1255. * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
  1256. * @param hqspi QSPI handle
  1257. * @param cmd structure that contains the command configuration information.
  1258. * @param cfg structure that contains the polling configuration information.
  1259. * @note This function is used only in Automatic Polling Mode
  1260. * @retval HAL status
  1261. */
  1262. HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
  1263. {
  1264. HAL_StatusTypeDef status = HAL_ERROR;
  1265. uint32_t tickstart = HAL_GetTick();
  1266. /* Check the parameters */
  1267. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  1268. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  1269. {
  1270. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  1271. }
  1272. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  1273. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1274. {
  1275. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  1276. }
  1277. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  1278. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1279. {
  1280. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  1281. }
  1282. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  1283. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  1284. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  1285. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  1286. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  1287. assert_param(IS_QSPI_INTERVAL(cfg->Interval));
  1288. assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
  1289. assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
  1290. assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
  1291. /* Process locked */
  1292. __HAL_LOCK(hqspi);
  1293. if(hqspi->State == HAL_QSPI_STATE_READY)
  1294. {
  1295. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1296. /* Update state */
  1297. hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
  1298. /* Wait till BUSY flag reset */
  1299. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  1300. if (status == HAL_OK)
  1301. {
  1302. /* Configure QSPI: PSMAR register with the status match value */
  1303. WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
  1304. /* Configure QSPI: PSMKR register with the status mask value */
  1305. WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
  1306. /* Configure QSPI: PIR register with the interval value */
  1307. WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
  1308. /* Configure QSPI: CR register with Match mode and Automatic stop mode */
  1309. MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
  1310. (cfg->MatchMode | cfg->AutomaticStop));
  1311. /* Clear interrupt */
  1312. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
  1313. /* Call the configuration function */
  1314. cmd->NbData = cfg->StatusBytesSize;
  1315. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
  1316. /* Process unlocked */
  1317. __HAL_UNLOCK(hqspi);
  1318. /* Enable the QSPI Transfer Error and status match Interrupt */
  1319. __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
  1320. }
  1321. else
  1322. {
  1323. /* Process unlocked */
  1324. __HAL_UNLOCK(hqspi);
  1325. }
  1326. }
  1327. else
  1328. {
  1329. status = HAL_BUSY;
  1330. /* Process unlocked */
  1331. __HAL_UNLOCK(hqspi);
  1332. }
  1333. /* Return function status */
  1334. return status;
  1335. }
  1336. /**
  1337. * @brief Configure the Memory Mapped mode.
  1338. * @param hqspi QSPI handle
  1339. * @param cmd structure that contains the command configuration information.
  1340. * @param cfg structure that contains the memory mapped configuration information.
  1341. * @note This function is used only in Memory mapped Mode
  1342. * @retval HAL status
  1343. */
  1344. HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
  1345. {
  1346. HAL_StatusTypeDef status = HAL_ERROR;
  1347. uint32_t tickstart = HAL_GetTick();
  1348. /* Check the parameters */
  1349. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  1350. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  1351. {
  1352. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  1353. }
  1354. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  1355. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1356. {
  1357. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  1358. }
  1359. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  1360. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1361. {
  1362. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  1363. }
  1364. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  1365. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  1366. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  1367. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  1368. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  1369. assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
  1370. /* Process locked */
  1371. __HAL_LOCK(hqspi);
  1372. if(hqspi->State == HAL_QSPI_STATE_READY)
  1373. {
  1374. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1375. /* Update state */
  1376. hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
  1377. /* Wait till BUSY flag reset */
  1378. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  1379. if (status == HAL_OK)
  1380. {
  1381. /* Configure QSPI: CR register with timeout counter enable */
  1382. MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
  1383. if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
  1384. {
  1385. assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
  1386. /* Configure QSPI: LPTR register with the low-power timeout value */
  1387. WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
  1388. /* Clear interrupt */
  1389. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
  1390. /* Enable the QSPI TimeOut Interrupt */
  1391. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
  1392. }
  1393. /* Call the configuration function */
  1394. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
  1395. }
  1396. }
  1397. else
  1398. {
  1399. status = HAL_BUSY;
  1400. }
  1401. /* Process unlocked */
  1402. __HAL_UNLOCK(hqspi);
  1403. /* Return function status */
  1404. return status;
  1405. }
  1406. /**
  1407. * @brief Transfer Error callbacks
  1408. * @param hqspi QSPI handle
  1409. * @retval None
  1410. */
  1411. __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
  1412. {
  1413. /* Prevent unused argument(s) compilation warning */
  1414. UNUSED(hqspi);
  1415. /* NOTE : This function Should not be modified, when the callback is needed,
  1416. the HAL_QSPI_ErrorCallback could be implemented in the user file
  1417. */
  1418. }
  1419. /**
  1420. * @brief Abort completed callback.
  1421. * @param hqspi QSPI handle
  1422. * @retval None
  1423. */
  1424. __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
  1425. {
  1426. /* Prevent unused argument(s) compilation warning */
  1427. UNUSED(hqspi);
  1428. /* NOTE: This function should not be modified, when the callback is needed,
  1429. the HAL_QSPI_AbortCpltCallback could be implemented in the user file
  1430. */
  1431. }
  1432. /**
  1433. * @brief Command completed callback.
  1434. * @param hqspi QSPI handle
  1435. * @retval None
  1436. */
  1437. __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
  1438. {
  1439. /* Prevent unused argument(s) compilation warning */
  1440. UNUSED(hqspi);
  1441. /* NOTE: This function Should not be modified, when the callback is needed,
  1442. the HAL_QSPI_CmdCpltCallback could be implemented in the user file
  1443. */
  1444. }
  1445. /**
  1446. * @brief Rx Transfer completed callbacks.
  1447. * @param hqspi QSPI handle
  1448. * @retval None
  1449. */
  1450. __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
  1451. {
  1452. /* Prevent unused argument(s) compilation warning */
  1453. UNUSED(hqspi);
  1454. /* NOTE: This function Should not be modified, when the callback is needed,
  1455. the HAL_QSPI_RxCpltCallback could be implemented in the user file
  1456. */
  1457. }
  1458. /**
  1459. * @brief Tx Transfer completed callbacks.
  1460. * @param hqspi QSPI handle
  1461. * @retval None
  1462. */
  1463. __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
  1464. {
  1465. /* Prevent unused argument(s) compilation warning */
  1466. UNUSED(hqspi);
  1467. /* NOTE: This function Should not be modified, when the callback is needed,
  1468. the HAL_QSPI_TxCpltCallback could be implemented in the user file
  1469. */
  1470. }
  1471. /**
  1472. * @brief Rx Half Transfer completed callbacks.
  1473. * @param hqspi QSPI handle
  1474. * @retval None
  1475. */
  1476. __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
  1477. {
  1478. /* Prevent unused argument(s) compilation warning */
  1479. UNUSED(hqspi);
  1480. /* NOTE: This function Should not be modified, when the callback is needed,
  1481. the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
  1482. */
  1483. }
  1484. /**
  1485. * @brief Tx Half Transfer completed callbacks.
  1486. * @param hqspi QSPI handle
  1487. * @retval None
  1488. */
  1489. __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
  1490. {
  1491. /* Prevent unused argument(s) compilation warning */
  1492. UNUSED(hqspi);
  1493. /* NOTE: This function Should not be modified, when the callback is needed,
  1494. the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
  1495. */
  1496. }
  1497. /**
  1498. * @brief FIFO Threshold callbacks
  1499. * @param hqspi QSPI handle
  1500. * @retval None
  1501. */
  1502. __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
  1503. {
  1504. /* Prevent unused argument(s) compilation warning */
  1505. UNUSED(hqspi);
  1506. /* NOTE : This function Should not be modified, when the callback is needed,
  1507. the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
  1508. */
  1509. }
  1510. /**
  1511. * @brief Status Match callbacks
  1512. * @param hqspi QSPI handle
  1513. * @retval None
  1514. */
  1515. __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
  1516. {
  1517. /* Prevent unused argument(s) compilation warning */
  1518. UNUSED(hqspi);
  1519. /* NOTE : This function Should not be modified, when the callback is needed,
  1520. the HAL_QSPI_StatusMatchCallback could be implemented in the user file
  1521. */
  1522. }
  1523. /**
  1524. * @brief Timeout callbacks
  1525. * @param hqspi QSPI handle
  1526. * @retval None
  1527. */
  1528. __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
  1529. {
  1530. /* Prevent unused argument(s) compilation warning */
  1531. UNUSED(hqspi);
  1532. /* NOTE : This function Should not be modified, when the callback is needed,
  1533. the HAL_QSPI_TimeOutCallback could be implemented in the user file
  1534. */
  1535. }
  1536. /**
  1537. * @}
  1538. */
  1539. /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
  1540. * @brief QSPI control and State functions
  1541. *
  1542. @verbatim
  1543. ===============================================================================
  1544. ##### Peripheral Control and State functions #####
  1545. ===============================================================================
  1546. [..]
  1547. This subsection provides a set of functions allowing to :
  1548. (+) Check in run-time the state of the driver.
  1549. (+) Check the error code set during last operation.
  1550. (+) Abort any operation.
  1551. .....
  1552. @endverbatim
  1553. * @{
  1554. */
  1555. /**
  1556. * @brief Return the QSPI handle state.
  1557. * @param hqspi QSPI handle
  1558. * @retval HAL state
  1559. */
  1560. HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
  1561. {
  1562. /* Return QSPI handle state */
  1563. return hqspi->State;
  1564. }
  1565. /**
  1566. * @brief Return the QSPI error code
  1567. * @param hqspi QSPI handle
  1568. * @retval QSPI Error Code
  1569. */
  1570. uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
  1571. {
  1572. return hqspi->ErrorCode;
  1573. }
  1574. /**
  1575. * @brief Abort the current transmission
  1576. * @param hqspi QSPI handle
  1577. * @retval HAL status
  1578. */
  1579. HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
  1580. {
  1581. HAL_StatusTypeDef status = HAL_OK;
  1582. uint32_t tickstart = HAL_GetTick();
  1583. /* Check if the state is in one of the busy states */
  1584. if ((hqspi->State & 0x2) != 0)
  1585. {
  1586. /* Process unlocked */
  1587. __HAL_UNLOCK(hqspi);
  1588. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
  1589. {
  1590. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  1591. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1592. /* Abort DMA channel */
  1593. status = HAL_DMA_Abort(hqspi->hdma);
  1594. if(status != HAL_OK)
  1595. {
  1596. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  1597. }
  1598. }
  1599. /* Configure QSPI: CR register with Abort request */
  1600. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
  1601. /* Wait until TC flag is set to go back in idle state */
  1602. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
  1603. if(status == HAL_OK)
  1604. {
  1605. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  1606. /* Wait until BUSY flag is reset */
  1607. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  1608. }
  1609. if (status == HAL_OK)
  1610. {
  1611. /* Update state */
  1612. hqspi->State = HAL_QSPI_STATE_READY;
  1613. }
  1614. }
  1615. return status;
  1616. }
  1617. /**
  1618. * @brief Abort the current transmission (non-blocking function)
  1619. * @param hqspi QSPI handle
  1620. * @retval HAL status
  1621. */
  1622. HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
  1623. {
  1624. HAL_StatusTypeDef status = HAL_OK;
  1625. /* Check if the state is in one of the busy states */
  1626. if ((hqspi->State & 0x2) != 0)
  1627. {
  1628. /* Process unlocked */
  1629. __HAL_UNLOCK(hqspi);
  1630. /* Update QSPI state */
  1631. hqspi->State = HAL_QSPI_STATE_ABORT;
  1632. /* Disable all interrupts */
  1633. __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
  1634. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
  1635. {
  1636. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  1637. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1638. /* Abort DMA channel */
  1639. hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
  1640. HAL_DMA_Abort_IT(hqspi->hdma);
  1641. }
  1642. else
  1643. {
  1644. /* Clear interrupt */
  1645. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  1646. /* Enable the QSPI Transfer Complete Interrupt */
  1647. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  1648. /* Configure QSPI: CR register with Abort request */
  1649. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
  1650. }
  1651. }
  1652. return status;
  1653. }
  1654. /** @brief Set QSPI timeout
  1655. * @param hqspi QSPI handle.
  1656. * @param Timeout Timeout for the QSPI memory access.
  1657. * @retval None
  1658. */
  1659. void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
  1660. {
  1661. hqspi->Timeout = Timeout;
  1662. }
  1663. /** @brief Set QSPI Fifo threshold.
  1664. * @param hqspi QSPI handle.
  1665. * @param Threshold Threshold of the Fifo (value between 1 and 16).
  1666. * @retval HAL status
  1667. */
  1668. HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
  1669. {
  1670. HAL_StatusTypeDef status = HAL_OK;
  1671. /* Process locked */
  1672. __HAL_LOCK(hqspi);
  1673. if(hqspi->State == HAL_QSPI_STATE_READY)
  1674. {
  1675. /* Synchronize init structure with new FIFO threshold value */
  1676. hqspi->Init.FifoThreshold = Threshold;
  1677. /* Configure QSPI FIFO Threshold */
  1678. MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
  1679. ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos));
  1680. }
  1681. else
  1682. {
  1683. status = HAL_BUSY;
  1684. }
  1685. /* Process unlocked */
  1686. __HAL_UNLOCK(hqspi);
  1687. /* Return function status */
  1688. return status;
  1689. }
  1690. /** @brief Get QSPI Fifo threshold.
  1691. * @param hqspi QSPI handle.
  1692. * @retval Fifo threshold (value between 1 and 16)
  1693. */
  1694. uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
  1695. {
  1696. return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1);
  1697. }
  1698. /**
  1699. * @}
  1700. */
  1701. /* Private functions ---------------------------------------------------------*/
  1702. /**
  1703. * @brief DMA QSPI receive process complete callback.
  1704. * @param hdma DMA handle
  1705. * @retval None
  1706. */
  1707. static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
  1708. {
  1709. QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1710. hqspi->RxXferCount = 0;
  1711. /* Enable the QSPI transfer complete Interrupt */
  1712. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  1713. }
  1714. /**
  1715. * @brief DMA QSPI transmit process complete callback.
  1716. * @param hdma DMA handle
  1717. * @retval None
  1718. */
  1719. static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
  1720. {
  1721. QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1722. hqspi->TxXferCount = 0;
  1723. /* Enable the QSPI transfer complete Interrupt */
  1724. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  1725. }
  1726. /**
  1727. * @brief DMA QSPI receive process half complete callback
  1728. * @param hdma DMA handle
  1729. * @retval None
  1730. */
  1731. static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  1732. {
  1733. QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1734. HAL_QSPI_RxHalfCpltCallback(hqspi);
  1735. }
  1736. /**
  1737. * @brief DMA QSPI transmit process half complete callback
  1738. * @param hdma DMA handle
  1739. * @retval None
  1740. */
  1741. static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  1742. {
  1743. QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
  1744. HAL_QSPI_TxHalfCpltCallback(hqspi);
  1745. }
  1746. /**
  1747. * @brief DMA QSPI communication error callback.
  1748. * @param hdma DMA handle
  1749. * @retval None
  1750. */
  1751. static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
  1752. {
  1753. QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1754. /* if DMA error is FIFO error ignore it */
  1755. if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
  1756. {
  1757. hqspi->RxXferCount = 0;
  1758. hqspi->TxXferCount = 0;
  1759. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  1760. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  1761. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1762. /* Abort the QSPI */
  1763. HAL_QSPI_Abort_IT(hqspi);
  1764. }
  1765. }
  1766. /**
  1767. * @brief DMA QSPI abort complete callback.
  1768. * @param hdma DMA handle
  1769. * @retval None
  1770. */
  1771. static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
  1772. {
  1773. QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1774. hqspi->RxXferCount = 0;
  1775. hqspi->TxXferCount = 0;
  1776. if(hqspi->State == HAL_QSPI_STATE_ABORT)
  1777. {
  1778. /* DMA Abort called by QSPI abort */
  1779. /* Clear interrupt */
  1780. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  1781. /* Enable the QSPI Transfer Complete Interrupt */
  1782. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  1783. /* Configure QSPI: CR register with Abort request */
  1784. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
  1785. }
  1786. else
  1787. {
  1788. /* DMA Abort called due to a transfer error interrupt */
  1789. /* Change state of QSPI */
  1790. hqspi->State = HAL_QSPI_STATE_READY;
  1791. /* Error callback */
  1792. HAL_QSPI_ErrorCallback(hqspi);
  1793. }
  1794. }
  1795. /**
  1796. * @brief Wait for a flag state until timeout.
  1797. * @param hqspi QSPI handle
  1798. * @param Flag Flag checked
  1799. * @param State Value of the flag expected
  1800. * @param tickstart Start tick value
  1801. * @param Timeout Duration of the time out
  1802. * @retval HAL status
  1803. */
  1804. static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
  1805. FlagStatus State, uint32_t tickstart, uint32_t Timeout)
  1806. {
  1807. /* Wait until flag is in expected state */
  1808. while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
  1809. {
  1810. /* Check for the Timeout */
  1811. if (Timeout != HAL_MAX_DELAY)
  1812. {
  1813. if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
  1814. {
  1815. hqspi->State = HAL_QSPI_STATE_ERROR;
  1816. hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
  1817. return HAL_ERROR;
  1818. }
  1819. }
  1820. }
  1821. return HAL_OK;
  1822. }
  1823. /**
  1824. * @brief Configure the communication registers.
  1825. * @param hqspi QSPI handle
  1826. * @param cmd structure that contains the command configuration information
  1827. * @param FunctionalMode functional mode to configured
  1828. * This parameter can be one of the following values:
  1829. * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
  1830. * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
  1831. * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
  1832. * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
  1833. * @retval None
  1834. */
  1835. static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
  1836. {
  1837. assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
  1838. if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
  1839. {
  1840. /* Configure QSPI: DLR register with the number of data to read or write */
  1841. WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
  1842. }
  1843. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  1844. {
  1845. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1846. {
  1847. /* Configure QSPI: ABR register with alternate bytes value */
  1848. WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
  1849. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1850. {
  1851. /*---- Command with instruction, address and alternate bytes ----*/
  1852. /* Configure QSPI: CCR register with all communications parameters */
  1853. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1854. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
  1855. cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
  1856. cmd->InstructionMode | cmd->Instruction | FunctionalMode));
  1857. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  1858. {
  1859. /* Configure QSPI: AR register with address value */
  1860. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  1861. }
  1862. }
  1863. else
  1864. {
  1865. /*---- Command with instruction and alternate bytes ----*/
  1866. /* Configure QSPI: CCR register with all communications parameters */
  1867. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1868. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
  1869. cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
  1870. cmd->Instruction | FunctionalMode));
  1871. }
  1872. }
  1873. else
  1874. {
  1875. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1876. {
  1877. /*---- Command with instruction and address ----*/
  1878. /* Configure QSPI: CCR register with all communications parameters */
  1879. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1880. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
  1881. cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
  1882. cmd->Instruction | FunctionalMode));
  1883. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  1884. {
  1885. /* Configure QSPI: AR register with address value */
  1886. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  1887. }
  1888. }
  1889. else
  1890. {
  1891. /*---- Command with only instruction ----*/
  1892. /* Configure QSPI: CCR register with all communications parameters */
  1893. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1894. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
  1895. cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
  1896. FunctionalMode));
  1897. }
  1898. }
  1899. }
  1900. else
  1901. {
  1902. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1903. {
  1904. /* Configure QSPI: ABR register with alternate bytes value */
  1905. WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
  1906. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1907. {
  1908. /*---- Command with address and alternate bytes ----*/
  1909. /* Configure QSPI: CCR register with all communications parameters */
  1910. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1911. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
  1912. cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
  1913. cmd->InstructionMode | FunctionalMode));
  1914. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  1915. {
  1916. /* Configure QSPI: AR register with address value */
  1917. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  1918. }
  1919. }
  1920. else
  1921. {
  1922. /*---- Command with only alternate bytes ----*/
  1923. /* Configure QSPI: CCR register with all communications parameters */
  1924. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1925. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
  1926. cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
  1927. FunctionalMode));
  1928. }
  1929. }
  1930. else
  1931. {
  1932. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1933. {
  1934. /*---- Command with only address ----*/
  1935. /* Configure QSPI: CCR register with all communications parameters */
  1936. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1937. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
  1938. cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
  1939. FunctionalMode));
  1940. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  1941. {
  1942. /* Configure QSPI: AR register with address value */
  1943. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  1944. }
  1945. }
  1946. else
  1947. {
  1948. /*---- Command with only data phase ----*/
  1949. if (cmd->DataMode != QSPI_DATA_NONE)
  1950. {
  1951. /* Configure QSPI: CCR register with all communications parameters */
  1952. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  1953. cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
  1954. cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
  1955. }
  1956. }
  1957. }
  1958. }
  1959. }
  1960. /**
  1961. * @}
  1962. */
  1963. #endif /* HAL_QSPI_MODULE_ENABLED */
  1964. /**
  1965. * @}
  1966. */
  1967. /**
  1968. * @}
  1969. */
  1970. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/