drv_dma.h 5.2 KB

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  1. /*
  2. * File : drv_dma.h
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * Change Logs:
  21. * Date Author Notes
  22. * 2015-11-19 Urey the first version
  23. */
  24. #ifndef _DRV_DMA_H_
  25. #define _DRV_DMA_H_
  26. #include <stdint.h>
  27. #define NR_DMA_CHANNELS 8
  28. #define CH_DSA 0x00
  29. #define CH_DTA 0x04
  30. #define CH_DTC 0x08
  31. #define CH_DRT 0x0C
  32. #define CH_DCS 0x10
  33. #define CH_DCM 0x14
  34. #define CH_DDA 0x18
  35. #define CH_DSD 0x1C
  36. #define TCSM 0x2000
  37. #define DMAC 0x1000
  38. #define DIRQP 0x1004
  39. #define DESIRQP 0x1010
  40. #define DIC 0x1014
  41. #define DDR 0x1008
  42. #define DDRS 0x100C
  43. #define DMACP 0x101C
  44. #define DSIRQP 0x1020
  45. #define DSIRQM 0x1024
  46. #define DCIRQP 0x1028
  47. #define DCIRQM 0x102C
  48. /* MCU of PDMA */
  49. #define DMCS 0x1030
  50. #define DMNMB 0x1034
  51. #define DMSMB 0x1038
  52. #define DMINT 0x103C
  53. /* MCU of PDMA */
  54. #define DMINT_S_IP BIT(17)
  55. #define DMINT_N_IP BIT(16)
  56. #define DMAC_HLT BIT(3)
  57. #define DMAC_AR BIT(2)
  58. #define DCS_NDES BIT(31)
  59. #define DCS_AR BIT(4)
  60. #define DCS_TT BIT(3)
  61. #define DCS_HLT BIT(2)
  62. #define DCS_CTE BIT(0)
  63. #define DCM_SAI BIT(23)
  64. #define DCM_DAI BIT(22)
  65. #define DCM_SP_MSK (0x3 << 14)
  66. #define DCM_SP_32 DCM_SP_MSK
  67. #define DCM_SP_16 BIT(15)
  68. #define DCM_SP_8 BIT(14)
  69. #define DCM_DP_MSK (0x3 << 12)
  70. #define DCM_DP_32 DCM_DP_MSK
  71. #define DCM_DP_16 BIT(13)
  72. #define DCM_DP_8 BIT(12)
  73. #define DCM_TSZ_MSK (0x7 << 8)
  74. #define DCM_TSZ_SHF 8
  75. #define DCM_STDE BIT(2)
  76. #define DCM_TIE BIT(1)
  77. #define DCM_LINK BIT(0)
  78. #define DCM_CH1_SRC_TCSM (0x0 << 26)
  79. #define DCM_CH1_SRC_NEMC (0x1 << 26)
  80. #define DCM_CH1_SRC_DDR (0x2 << 26)
  81. #define DCM_CH1_DST_TCSM (0x0 << 24)
  82. #define DCM_CH1_DST_NEMC (0x1 << 24)
  83. #define DCM_CH1_DST_DDR (0x2 << 24)
  84. #define DCM_CH1_DDR_TO_NAND (DCM_CH1_SRC_DDR | DCM_CH1_DST_NEMC)
  85. #define DCM_CH1_NAND_TO_DDR (DCM_CH1_SRC_NEMC | DCM_CH1_DST_DDR)
  86. #define DCM_CH1_TCSM_TO_NAND (DCM_CH1_SRC_TCSM | DCM_CH1_DST_NEMC)
  87. #define DCM_CH1_NAND_TO_TCSM (DCM_CH1_SRC_NEMC | DCM_CH1_DST_TCSM)
  88. #define DCM_CH1_TCSM_TO_DDR (DCM_CH1_SRC_TCSM | DCM_CH1_DST_DDR)
  89. #define DCM_CH1_DDR_TO_TCSM (DCM_CH1_SRC_DDR | DCM_CH1_DST_TCSM)
  90. #define MCU_MSG_TYPE_NORMAL 0x1
  91. #define MCU_MSG_TYPE_INTC 0x2
  92. #define MCU_MSG_TYPE_INTC_MASKA 0x3
  93. enum jzdma_req_type {
  94. #define _RTP(NAME) JZDMA_REQ_##NAME##_TX,JZDMA_REQ_##NAME##_RX
  95. JZDMA_REQ_RESERVED0 = 0x03,
  96. _RTP(DMIC),
  97. _RTP(I2S0),
  98. JZDMA_REQ_AUTO_TXRX = 0x08,
  99. JZDMA_REQ_SADC_RX,
  100. JZDMA_REQ_RESERVED1 = 0x0b,
  101. _RTP(UART4),
  102. _RTP(UART3),
  103. _RTP(UART2),
  104. _RTP(UART1),
  105. _RTP(UART0),
  106. _RTP(SSI0),
  107. _RTP(SSI1),
  108. _RTP(MSC0),
  109. _RTP(MSC1),
  110. _RTP(MSC2),
  111. _RTP(PCM0),
  112. _RTP(PCM1),
  113. _RTP(I2C0),
  114. _RTP(I2C1),
  115. _RTP(I2C2),
  116. _RTP(I2C3),
  117. _RTP(I2C4),
  118. _RTP(DES),
  119. #undef _RTP
  120. };
  121. enum jzdma_type {
  122. JZDMA_REQ_INVAL = 0,
  123. #define _RTP(NAME) JZDMA_REQ_##NAME = JZDMA_REQ_##NAME##_TX
  124. _RTP(DMIC),
  125. _RTP(I2S0),
  126. JZDMA_REQ_AUTO = JZDMA_REQ_AUTO_TXRX,
  127. JZDMA_REQ_SADC = JZDMA_REQ_SADC_RX,
  128. _RTP(UART4),
  129. _RTP(UART3),
  130. _RTP(UART2),
  131. _RTP(UART1),
  132. _RTP(UART0),
  133. _RTP(SSI0),
  134. _RTP(SSI1),
  135. _RTP(MSC0),
  136. _RTP(MSC1),
  137. _RTP(MSC2),
  138. _RTP(PCM0),
  139. _RTP(PCM1),
  140. _RTP(I2C0),
  141. _RTP(I2C1),
  142. _RTP(I2C2),
  143. _RTP(I2C3),
  144. _RTP(I2C4),
  145. _RTP(DES),
  146. JZDMA_REQ_NAND0 = JZDMA_REQ_AUTO_TXRX | (1 << 16),
  147. JZDMA_REQ_NAND1 = JZDMA_REQ_AUTO_TXRX | (2 << 16),
  148. JZDMA_REQ_NAND2 = JZDMA_REQ_AUTO_TXRX | (3 << 16),
  149. JZDMA_REQ_NAND3 = JZDMA_REQ_AUTO_TXRX | (4 << 16),
  150. JZDMA_REQ_NAND4 = JZDMA_REQ_AUTO_TXRX | (5 << 16),
  151. TYPE_MASK = 0xffff,
  152. #undef _RTP
  153. };
  154. #define GET_MAP_TYPE(type) (type & (TYPE_MASK))
  155. enum channel_status
  156. {
  157. STAT_STOPED,STAT_SUBED,STAT_PREPED,STAT_RUNNING,
  158. };
  159. struct jzdma_desc
  160. {
  161. uint32_t dcm;
  162. uint32_t dsa;
  163. uint32_t dta;
  164. uint32_t dtc;
  165. uint32_t sd;
  166. uint32_t drt;
  167. uint32_t reserved[2];
  168. };
  169. struct jzdma_channel
  170. {
  171. // int id;
  172. uint32_t iomem;
  173. uint32_t dcs_saved;
  174. uint32_t dcm_def;
  175. enum jzdma_type type;
  176. enum channel_status status;
  177. //´«Êä¿ØÖÆÃèÊö·û
  178. struct jzdma_desc desc;
  179. uint32_t desc_nr;
  180. // struct rt_dma_channel *parant;
  181. };
  182. struct jzdma_master
  183. {
  184. uint32_t base;
  185. struct clk *clk;
  186. int irq;
  187. int irq_pdmad; /* irq_pdmad for PDMA_DESC irq */
  188. struct jzdma_channel channel[NR_DMA_CHANNELS];
  189. };
  190. extern struct rt_dma_funcs _g_jzdma_funcs;
  191. #endif /* _DRV_DMA_H_ */