mips_addrspace.h 4.2 KB

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  1. /*
  2. * Copyright (c) 2006-2019, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-12-04 Jiaxun Yang Initial version
  9. */
  10. #ifndef _MIPS_ADDRSPACE_H_
  11. #define _MIPS_ADDRSPACE_H_
  12. /*
  13. * Configure language
  14. */
  15. #ifdef __ASSEMBLY__
  16. #define _ATYPE_
  17. #define _ATYPE32_
  18. #define _ATYPE64_
  19. #define _CONST64_(x) x
  20. #else
  21. #define _ATYPE_ __PTRDIFF_TYPE__
  22. #define _ATYPE32_ int
  23. #define _ATYPE64_ __s64
  24. #ifdef CONFIG_64BIT
  25. #define _CONST64_(x) x ## L
  26. #else
  27. #define _CONST64_(x) x ## LL
  28. #endif
  29. #endif
  30. /*
  31. * 32-bit MIPS address spaces
  32. */
  33. #ifdef __ASSEMBLY__
  34. #define _ACAST32_
  35. #define _ACAST64_
  36. #else
  37. #define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
  38. #define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
  39. #endif
  40. /*
  41. * Returns the kernel segment base of a given address
  42. */
  43. #define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
  44. /*
  45. * Returns the physical address of a CKSEGx / XKPHYS address
  46. */
  47. #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
  48. #define XPHYSADDR(a) ((_ACAST64_(a)) & \
  49. _CONST64_(0x000000ffffffffff))
  50. #ifdef CONFIG_64BIT
  51. /*
  52. * Memory segments (64bit kernel mode addresses)
  53. * The compatibility segments use the full 64-bit sign extended value. Note
  54. * the R8000 doesn't have them so don't reference these in generic MIPS code.
  55. */
  56. #define XKUSEG _CONST64_(0x0000000000000000)
  57. #define XKSSEG _CONST64_(0x4000000000000000)
  58. #define XKPHYS _CONST64_(0x8000000000000000)
  59. #define XKSEG _CONST64_(0xc000000000000000)
  60. #define CKSEG0 _CONST64_(0xffffffff80000000)
  61. #define CKSEG1 _CONST64_(0xffffffffa0000000)
  62. #define CKSSEG _CONST64_(0xffffffffc0000000)
  63. #define CKSEG3 _CONST64_(0xffffffffe0000000)
  64. #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
  65. #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
  66. #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
  67. #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
  68. #else
  69. #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
  70. #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
  71. #define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
  72. #define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
  73. /*
  74. * Map an address to a certain kernel segment
  75. */
  76. #define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
  77. #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
  78. #define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
  79. #define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
  80. /*
  81. * Memory segments (32bit kernel mode addresses)
  82. * These are the traditional names used in the 32-bit universe.
  83. */
  84. #define KUSEGBASE 0x00000000
  85. #define KSEG0BASE 0x80000000
  86. #define KSEG1BASE 0xa0000000
  87. #define KSEG2BASE 0xc0000000
  88. #define KSEG3BASE 0xe0000000
  89. #define CKUSEG 0x00000000
  90. #define CKSEG0 0x80000000
  91. #define CKSEG1 0xa0000000
  92. #define CKSEG2 0xc0000000
  93. #define CKSEG3 0xe0000000
  94. #endif
  95. /*
  96. * Cache modes for XKPHYS address conversion macros
  97. */
  98. #define K_CALG_COH_EXCL1_NOL2 0
  99. #define K_CALG_COH_SHRL1_NOL2 1
  100. #define K_CALG_UNCACHED 2
  101. #define K_CALG_NONCOHERENT 3
  102. #define K_CALG_COH_EXCL 4
  103. #define K_CALG_COH_SHAREABLE 5
  104. #define K_CALG_NOTUSED 6
  105. #define K_CALG_UNCACHED_ACCEL 7
  106. /*
  107. * 64-bit address conversions
  108. */
  109. #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
  110. #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
  111. #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
  112. #define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
  113. (_CONST64_(cm) << 59) | (a))
  114. /*
  115. * Returns the uncached address of a sdram address
  116. */
  117. #ifndef __ASSEMBLY__
  118. /*
  119. * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
  120. * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
  121. * R8000 implements most with its 48-bit physical address space.
  122. */
  123. #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
  124. #define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
  125. #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
  126. #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
  127. #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
  128. #endif
  129. #ifndef __ASSEMBLY__
  130. #define REG8( addr ) (*(volatile u8 *) (addr))
  131. #define REG16( addr ) (*(volatile u16 *)(addr))
  132. #define REG32( addr ) (*(volatile u32 *)(addr))
  133. #define REG64( addr ) (*(volatile u64 *)(addr))
  134. #endif
  135. #endif /* _MIPS_ADDRSPACE_H_ */